MPC860_SCC_UART.rar

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基于 CPU 通用I/O SCC 模块实现UART功能代码
MPC860_SCC_UART.rar
  • MPC860_SCC_UART
  • 860UARTcode.c
    10KB
  • 860SCCinit.pdf
    10.4KB
内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/624727c754457c44d0a1c212/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/624727c754457c44d0a1c212/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">MPC860 UART Protocol<span class="_ _0"> </span> 1</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">How to Initialize an 860 SCCx for UART (1 of 5)</div><div class="t m0 x3 h4 y3 ff1 fs2 fc0 sc0 ls1 ws0">Step<span class="_ _1"> </span>Action<span class="_ _2"> </span>Example</div><div class="t m0 x4 h4 y4 ff1 fs2 fc0 sc0 ls0 ws0">1<span class="_ _3"> </span>Initialize SDCR</div><div class="t m0 x5 h4 y5 ff1 fs2 fc0 sc0 ls0 ws0">Introduction</div><div class="t m0 x6 h4 y6 ff1 fs2 fc0 sc0 ls0 ws0">Here we describe the steps in initializing an SCC on the MPC860 using interrupts. </div><div class="t m0 x5 h4 y7 ff1 fs2 fc0 sc0 ls0 ws0">Action<span class="_ _4"> </span>Here are the steps in initialization :</div><div class="t m0 x7 h4 y8 ff1 fs2 fc0 sc0 ls0 ws0">pimm-&gt;PAPAR = 0x108;</div><div class="t m0 x7 h4 y9 ff1 fs2 fc0 sc0 ls0 ws0">/*ENBL TxD2, &amp; CLK2 */</div><div class="t m0 x4 h4 ya ff1 fs2 fc0 sc0 ls0 ws0">2<span class="_ _5"> </span>Configure ports as required</div><div class="t m0 x5 h4 yb ff1 fs2 fc0 sc0 ls1 ws0">Assumptions</div><div class="t m0 x6 h4 yc ff1 fs2 fc0 sc0 ls0 ws0">- IMMR has been initialized previously. If not, the user must initialize it.</div><div class="t m0 x6 h4 yd ff1 fs2 fc0 sc0 ls0 ws0">- CICR has been initialized previously. If not and if interrupts are to be used, the user</div><div class="t m0 x6 h4 ye ff1 fs2 fc0 sc0 ls1 ws0"> must initialize it.</div><div class="t m0 x6 h4 yf ff1 fs2 fc0 sc0 ls0 ws0">- Except for the above, reset conditions exist.</div><div class="t m0 x4 h4 y10 ff1 fs2 fc0 sc0 ls0 ws0">3</div><div class="t m0 x8 h4 y11 ff1 fs2 fc0 sc0 ls0 ws0">Initialize a Baud Rate Configuration Reg,</div><div class="t m0 x8 h4 y12 ff1 fs2 fc0 sc0 ls2 ws0">BRGCx</div><div class="t m0 x9 h4 y13 ff1 fs2 fc0 sc0 ls0 ws0">CD0_CD11:clock divider</div><div class="t m0 x9 h4 y14 ff1 fs2 fc0 sc0 ls0 ws0">DIV16:BRG clk prescalar divide by 16</div><div class="t m0 x9 h4 y15 ff1 fs2 fc0 sc0 ls0 ws0">EXTC1_EXTC0:clock source</div><div class="t m0 x9 h4 y16 ff1 fs2 fc0 sc0 ls1 ws0">EN:enable BRG count</div><div class="t m0 x9 h4 y17 ff1 fs2 fc0 sc0 ls0 ws0">ATB:autobaud</div><div class="t m0 x9 h4 y18 ff1 fs2 fc0 sc0 ls1 ws0">RST:reset BRG</div><div class="t m0 x7 h4 y11 ff1 fs2 fc0 sc0 ls1 ws0">pimm-&gt;BRGC3 = 0x10821;</div><div class="t m0 x7 h4 y12 ff1 fs2 fc0 sc0 ls0 ws0">/* SET BAUD RATE TO 1200 FOR</div><div class="t m0 x7 h4 y19 ff1 fs2 fc0 sc0 ls0 ws0"> 20 MHz CLOCK */</div><div class="t m0 x4 h4 y1a ff1 fs2 fc0 sc0 ls0 ws0">4</div><div class="t m0 x8 h4 y1b ff1 fs2 fc0 sc0 ls0 ws0">Initialize the Serial Interface Clock Route</div><div class="t m0 x8 h4 y1c ff1 fs2 fc0 sc0 ls1 ws0">Reg, SICR</div><div class="t m0 x9 h4 y1d ff1 fs2 fc0 sc0 ls0 ws0">SCx:select NMSI or TDM for SCCx</div><div class="t m0 x9 h4 y1e ff1 fs2 fc0 sc0 ls0 ws0">RxCS:select recv clk source for SCCx</div><div class="t m0 x9 h4 y1f ff1 fs2 fc0 sc0 ls0 ws0">TxCS:select xmit clk source for SCCx</div><div class="t m0 x9 h4 y20 ff1 fs2 fc0 sc0 ls0 ws0">GRx:select grant mechanism support</div><div class="t m0 x9 h4 y21 ff1 fs2 fc0 sc0 ls0 ws0">x is 1, 2, 3, or 4</div><div class="t m0 x7 h4 y1b ff1 fs2 fc0 sc0 ls0 ws0">pimm-&gt;SICR |= 0x3800;</div><div class="t m0 x7 h4 y1c ff1 fs2 fc0 sc0 ls0 ws0">/* SCC2 RECEIVE CLK IS CLK4*/</div><div class="t m0 x7 h4 y22 ff1 fs2 fc0 sc0 ls0 ws0">pimm-&gt;SDCR = 2;</div><div class="t m0 x7 h4 y23 ff1 fs2 fc0 sc0 ls0 ws0">/* MAKE SDMA ARB PRI=2 */</div><div class="t m0 xa h4 y24 ff1 fs2 fc0 sc0 ls0 ws0">FRZ:SDMAs freeze next bus cycle</div><div class="t m0 xa h4 y25 ff1 fs2 fc0 sc0 ls0 ws0">RAID: RISC controller arbitration ID</div><div class="t m0 xb h4 y26 ff1 fs2 fc0 sc0 ls2 ws0">(16-80)</div><div class="t m0 xc h4 y27 ff1 fs2 fc0 sc0 ls1 ws0">(16-454)</div><div class="t m0 xc h4 y28 ff1 fs2 fc0 sc0 ls1 ws0">(16-141)</div><div class="t m0 xc h4 y29 ff1 fs2 fc0 sc0 ls1 ws0">(16-121)</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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