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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626d944d40256a40ce61571e/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">VLSI Technology</div><div class="t m0 x2 h3 y3 ff1 fs0 fc1 sc0 ls0 ws0">VLSI Technology</div><div class="t m0 x3 h4 y4 ff2 fs1 fc2 sc0 ls0 ws0"></div><div class="t m0 x4 h5 y5 ff3 fs2 fc0 sc0 ls0 ws0">Scaling</div><div class="t m0 x5 h5 y6 ff3 fs2 fc3 sc0 ls0 ws0">Scaling</div><div class="t m0 x3 h4 y7 ff2 fs1 fc2 sc0 ls0 ws0"></div><div class="t m0 x4 h5 y8 ff3 fs2 fc0 sc0 ls0 ws0">Moore’s Law</div><div class="t m0 x5 h5 y9 ff3 fs2 fc3 sc0 ls0 ws0">Moore’s Law</div><div class="t m0 x3 h4 ya ff2 fs1 fc2 sc0 ls0 ws0"></div><div class="t m0 x4 h5 yb ff3 fs2 fc0 sc0 ls0 ws0">3D </div><div class="t m0 x5 h5 yc ff3 fs2 fc3 sc0 ls0 ws0">3D </div><div class="t m0 x6 h5 yb ff3 fs2 fc0 sc0 ls0 ws0">VLSI</div><div class="t m0 x7 h5 yc ff3 fs2 fc3 sc0 ls0 ws0">VLSI</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626d944d40256a40ce61571e/bg2.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x8 h6 yd ff1 fs3 fc0 sc0 ls0 ws0">The beginning</div><div class="t m0 x9 h6 ye ff1 fs3 fc1 sc0 ls0 ws0">The beginning</div><div class="t m0 xa h7 yf ff4 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xb h7 y10 ff4 fs1 fc3 sc0 ls0 ws0"> </div><div class="t m0 xc h8 y11 ff3 fs1 fc0 sc0 ls0 ws0">Microproce<span class="_ _0"></span>ssors are essent<span class="_ _0"></span>ial to many of<span class="_ _0"></span> the </div><div class="t m0 xd h8 y12 ff3 fs1 fc3 sc0 ls0 ws0">Microproce<span class="_ _0"></span>ssors are essent<span class="_ _0"></span>ial to many of<span class="_ _0"></span> the </div><div class="t m0 xc h8 y13 ff3 fs1 fc0 sc0 ls0 ws0">products we use ever<span class="_ _0"></span>y day such as TVs, cars, radios<span class="_ _0"></span>, </div><div class="t m0 xd h8 y14 ff3 fs1 fc3 sc0 ls0 ws0">products we use ever<span class="_ _0"></span>y day such as TVs, cars, radios<span class="_ _0"></span>, </div><div class="t m0 xc h8 y15 ff3 fs1 fc0 sc0 ls0 ws0">home appliances<span class="_ _0"></span> and of course, co<span class="_ _0"></span>mputers. </div><div class="t m0 xd h8 y16 ff3 fs1 fc3 sc0 ls0 ws0">home appliances<span class="_ _0"></span> and of course, co<span class="_ _0"></span>mputers. </div><div class="t m0 xc h8 y17 ff3 fs1 fc0 sc0 ls0 ws0">Transistors are<span class="_ _0"></span> the main com<span class="_ _0"></span>ponents of </div><div class="t m0 xd h8 y18 ff3 fs1 fc3 sc0 ls0 ws0">Transistors are<span class="_ _0"></span> the main com<span class="_ _0"></span>ponents of </div><div class="t m0 xc h8 y19 ff3 fs1 fc0 sc0 ls0 ws0">microproces<span class="_ _0"></span>sors.</div><div class="t m0 xd h8 y1a ff3 fs1 fc3 sc0 ls0 ws0">microproces<span class="_ _0"></span>sors.</div><div class="t m0 xc h8 y1b ff3 fs1 fc0 sc0 ls0 ws0">At their most bas<span class="_ _0"></span>ic level, t<span class="_ _0"></span>ransistors m<span class="_ _0"></span>ay seem </div><div class="t m0 xd h8 y1c ff3 fs1 fc3 sc0 ls0 ws0">At their most bas<span class="_ _0"></span>ic level, t<span class="_ _0"></span>ransistors m<span class="_ _0"></span>ay seem </div><div class="t m0 xc h8 y1d ff3 fs1 fc0 sc0 ls0 ws0">simple. But thei<span class="_ _0"></span>r development<span class="_ _0"></span> actually re<span class="_ _0"></span>quired </div><div class="t m0 xd h8 y1e ff3 fs1 fc3 sc0 ls0 ws0">simple. But thei<span class="_ _0"></span>r development<span class="_ _0"></span> actually re<span class="_ _0"></span>quired </div><div class="t m0 xc h8 y1f ff3 fs1 fc0 sc0 ls0 ws0">many years of pa<span class="_ _0"></span>instaking researc<span class="_ _0"></span>h. Before </div><div class="t m0 xd h8 y20 ff3 fs1 fc3 sc0 ls0 ws0">many years of pa<span class="_ _0"></span>instaking researc<span class="_ _0"></span>h. Before </div><div class="t m0 xc h8 y21 ff3 fs1 fc0 sc0 ls0 ws0">transistors<span class="_ _0"></span>, computers rel<span class="_ _0"></span>ied on slow, ineffi<span class="_ _0"></span>cient </div><div class="t m0 xd h8 y22 ff3 fs1 fc3 sc0 ls0 ws0">transistors<span class="_ _0"></span>, computers rel<span class="_ _0"></span>ied on slow, ineffi<span class="_ _0"></span>cient </div><div class="t m0 xc h8 y23 ff3 fs1 fc0 sc0 ls0 ws0">vacuum tubes and me<span class="_ _0"></span>chanical <span class="_ _0"></span>switches to proce<span class="_ _0"></span>ss </div><div class="t m0 xd h8 y24 ff3 fs1 fc3 sc0 ls0 ws0">vacuum tubes and me<span class="_ _0"></span>chanical <span class="_ _0"></span>switches to proce<span class="_ _0"></span>ss </div><div class="t m0 xc h8 y25 ff3 fs1 fc0 sc0 ls0 ws0">information. In 19<span class="_ _0"></span>58, engineers</div><div class="t m0 xd h8 y26 ff3 fs1 fc3 sc0 ls0 ws0">information. In 19<span class="_ _0"></span>58, engineers</div><div class="t m0 xe h8 y25 ff3 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xf h8 y26 ff3 fs1 fc3 sc0 ls0 ws0"> </div><div class="t m0 x10 h8 y25 ff3 fs1 fc0 sc0 ls0 ws0">managed to put two </div><div class="t m0 x11 h8 y26 ff3 fs1 fc3 sc0 ls0 ws0">managed to put two </div><div class="t m0 xc h8 y27 ff3 fs1 fc0 sc0 ls0 ws0">transistors<span class="_ _0"></span> onto a </div><div class="t m0 xd h8 y28 ff3 fs1 fc3 sc0 ls0 ws0">transistors<span class="_ _0"></span> onto a </div><div class="t m0 x12 h8 y27 ff3 fs1 fc0 sc0 ls0 ws0">Silicon</div><div class="t m0 x13 h8 y28 ff3 fs1 fc3 sc0 ls0 ws0">Silicon</div><div class="t m0 x14 h8 y27 ff3 fs1 fc0 sc0 ls0 ws0"> crystal and c<span class="_ _0"></span>reate the<span class="_ _0"></span> first </div><div class="t m0 x15 h8 y28 ff3 fs1 fc3 sc0 ls0 ws0"> crystal and c<span class="_ _0"></span>reate the<span class="_ _0"></span> first </div><div class="t m0 xc h8 y29 ff3 fs1 fc0 sc0 ls0 ws0">integrated c<span class="_ _0"></span>ircuit, which</div><div class="t m0 xd h8 y2a ff3 fs1 fc3 sc0 ls0 ws0">integrated c<span class="_ _0"></span>ircuit, which</div><div class="t m0 x16 h8 y29 ff3 fs1 fc0 sc0 ls0 ws0"> subsequently </div><div class="t m0 x17 h8 y2a ff3 fs1 fc3 sc0 ls0 ws0"> subsequently </div><div class="t m0 x18 h8 y29 ff3 fs1 fc0 sc0 ls0 ws0">led to the</div><div class="t m0 x19 h8 y2a ff3 fs1 fc3 sc0 ls0 ws0">led to the</div><div class="t m0 x1a h8 y29 ff3 fs1 fc0 sc0 ls0 ws0"> first </div><div class="t m0 x1b h8 y2a ff3 fs1 fc3 sc0 ls0 ws0"> first </div><div class="t m0 xc h8 y2b ff3 fs1 fc0 sc0 ls0 ws0">microproces<span class="_ _0"></span>sor.*************************************************</div><div class="t m0 xd h8 y2c ff3 fs1 fc3 sc0 ls0 ws0">microproces<span class="_ _0"></span>sor.*************************************************</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626d944d40256a40ce61571e/bg3.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1c h9 y2d ff3 fs3 fc0 sc0 ls0 ws0">Transistor Size Scaling</div><div class="t m0 x1d h9 y2e ff3 fs3 fc1 sc0 ls0 ws0">Transistor Size Scaling</div><div class="t m0 x1e ha y2f ff5 fs4 fc3 sc0 ls0 ws0">MOSFET<span class="fs5"> </span></div><div class="t m0 x1e ha y30 ff5 fs5 fc3 sc0 ls0 ws0">performance </div><div class="t m0 x1e ha y31 ff5 fs5 fc3 sc0 ls0 ws0">improves as size is </div><div class="t m0 x1e ha y32 ff5 fs5 fc3 sc0 ls0 ws0">decreased:</div><div class="t m0 x1e ha y33 ff5 fs5 fc3 sc0 ls0 ws0">shorter switching </div><div class="t m0 x1e ha y34 ff5 fs5 fc3 sc0 ls0 ws0">time, lower power </div><div class="t m0 x1e ha y35 ff5 fs5 fc3 sc0 ls0 ws0">consumption.</div><div class="t m0 x1f hb y36 ff5 fs1 fc3 sc0 ls0 ws0">2 orders of magnitude reduction in <span class="_ _0"></span>transistor size in </div><div class="t m0 x20 hb y37 ff5 fs1 fc3 sc0 ls0 ws0">30 years. </div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626d944d40256a40ce61571e/bg4.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x2 h9 y38 ff3 fs3 fc0 sc0 ls0 ws0">Significant Breakthroug<span class="_ _0"></span>hs</div><div class="t m0 x21 h9 y39 ff3 fs3 fc1 sc0 ls0 ws0">Significant Breakthroug<span class="_ _0"></span>hs</div><div class="t m0 x22 hc y3a ff1 fs5 fc3 sc0 ls0 ws0">Transistor size<span class="ff3">:<span class="_ _0"></span> Intel’s <span class="_ _0"></span>research labs ha<span class="_ _0"></span>ve recentl<span class="_ _0"></span>y shown the world’s small<span class="_ _0"></span>est </span></div><div class="t m0 x22 hc y3b ff3 fs5 fc3 sc0 ls0 ws0">transistor, with <span class="_ _0"></span>a <span class="_ _0"></span>gate lengt<span class="_ _0"></span>h of 15nm. <span class="_ _0"></span>We continue<span class="_ _0"></span> to build <span class="_ _0"></span>smaller and <span class="_ _0"></span>smaller </div><div class="t m0 x22 hc y3c ff3 fs5 fc3 sc0 ls0 ws0">transistors that a<span class="_ _0"></span>re faster a<span class="_ _0"></span>nd<span class="_ _0"></span> faster.<span class="_ _0"></span> We've reduc<span class="_ _0"></span>ed the size<span class="_ _0"></span> from 70 nanom<span class="_ _0"></span>eter <span class="_ _0"></span>to 30<span class="_ _1"></span> </div><div class="t m0 x22 hc y3d ff3 fs5 fc3 sc0 ls0 ws0">nanometer t<span class="_ _0"></span>o 20 nanomet<span class="_ _0"></span>er, and now t<span class="_ _0"></span>o<span class="_ _0"></span> 15 nan<span class="_ _0"></span>ometer gate<span class="_ _0"></span>s.</div><div class="t m0 x23 hc y3e ff1 fs5 fc3 sc0 ls0 ws0">Manufacturing process<span class="ff3">: A ne<span class="_ _0"></span>w manufac<span class="_ _0"></span>turing process ca<span class="_ _0"></span>lled 130 nanom<span class="_ _0"></span>eter </span></div><div class="t m0 x23 hc y3f ff3 fs5 fc3 sc0 ls0 ws0">process technology <span class="_ _0"></span>(a nanome<span class="_ _0"></span>ter is a <span class="_ _0"></span>billionth of <span class="_ _0"></span>a meter)<span class="_ _0"></span> allows Intel <span class="_ _0"></span>today to </div><div class="t m0 x23 hc y40 ff3 fs5 fc3 sc0 ls0 ws0">manufacture <span class="_ _0"></span>chips with<span class="_ _0"></span> circ<span class="_ _0"></span>uitry so small<span class="_ _0"></span> it would ta<span class="_ _0"></span>ke almost <span class="_ _0"></span>1,000 of <span class="_ _0"></span>these "wires" </div><div class="t m0 x23 hc y41 ff3 fs5 fc3 sc0 ls0 ws0">placed side-by-side<span class="_ _0"></span> to equal <span class="_ _0"></span>the<span class="_ _0"></span> <span class="_ _0"></span>width of a hum<span class="_ _0"></span>an hair. <span class="_ _0"></span>This new 130-nanomet<span class="_ _0"></span>er </div><div class="t m0 x23 hc y42 ff3 fs5 fc3 sc0 ls0 ws0">process has 60nm gat<span class="_ _0"></span>e-length tra<span class="_ _0"></span>nsistors and<span class="_ _0"></span> six l<span class="_ _0"></span>ayers of c<span class="_ _0"></span>opper interconne<span class="_ _0"></span>ct. Thi<span class="_ _0"></span>s </div><div class="t m0 x23 hc y43 ff3 fs5 fc3 sc0 ls0 ws0">process is producing m<span class="_ _0"></span>icroprocessors today with<span class="_ _0"></span> millions<span class="_ _1"></span> of transistors a<span class="_ _0"></span>nd running </div><div class="t m0 x23 hc y44 ff3 fs5 fc3 sc0 ls0 ws0">at multi<span class="_ _0"></span>-gigahertz c<span class="_ _0"></span>lock speeds.</div><div class="t m0 x23 hc y45 ff1 fs5 fc3 sc0 ls0 ws0">Wafer size<span class="_ _0"></span><span class="ff3">: W<span class="_ _0"></span>afers, which a<span class="_ _0"></span>re round polished <span class="_ _0"></span>disks made of sil<span class="_ _0"></span>icon, provide <span class="_ _0"></span>the ba<span class="_ _0"></span>se </span></div><div class="t m0 x23 hc y46 ff3 fs5 fc3 sc0 ls0 ws0">on which <span class="_ _0"></span>chips are m<span class="_ _0"></span>anufactured. <span class="_ _0"></span>Use a bigger wafe<span class="_ _0"></span>r and you <span class="_ _0"></span>can reduce </div><div class="t m0 x23 hc y47 ff3 fs5 fc3 sc0 ls0 ws0">manufacturing <span class="_ _0"></span>costs. Intel <span class="_ _0"></span>has<span class="_ _0"></span> begun <span class="_ _0"></span>using a 300 mi<span class="_ _0"></span>llimeter <span class="_ _0"></span>(about 12 inc<span class="_ _0"></span>hes) </div><div class="t m0 x23 hc y48 ff3 fs5 fc3 sc0 ls0 ws0">diameter <span class="_ _0"></span>silicon wafer <span class="_ _0"></span>size, up from<span class="_ _0"></span> the previ<span class="_ _0"></span>ous<span class="_ _0"></span> <span class="_ _0"></span>wafer size of <span class="_ _0"></span>200mm (a<span class="_ _0"></span>bout 8 </div><div class="t m0 x23 hc y49 ff3 fs5 fc3 sc0 ls0 ws0">inches).</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626d944d40256a40ce61571e/bg5.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x24 h9 y4a ff3 fs3 fc0 sc0 ls0 ws0">Major Design Challenges</div><div class="t m0 x25 h9 y4b ff3 fs3 fc1 sc0 ls0 ws0">Major Design Challenges</div><div class="t m0 x26 hd y4c ff2 fs6 fc2 sc0 ls0 ws0"></div><div class="t m0 x27 he y4d ff3 fs7 fc0 sc0 ls0 ws0">Microscopic issues</div><div class="t m0 x28 he y4e ff3 fs7 fc3 sc0 ls0 ws0">Microscopic issues</div><div class="t m0 x3 he y4f ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 x29 he y50 ff3 fs7 fc0 sc0 ls0 ws0">ultra-high speeds</div><div class="t m0 x2a he y51 ff3 fs7 fc3 sc0 ls0 ws0">ultra-high speeds</div><div class="t m0 x3 he y52 ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 x29 he y53 ff3 fs7 fc0 sc0 ls0 ws0">power dissipation and </div><div class="t m0 x2a he y54 ff3 fs7 fc3 sc0 ls0 ws0">power dissipation and </div><div class="t m0 x29 he y55 ff3 fs7 fc0 sc0 ls0 ws0">supply rail drop</div><div class="t m0 x2a he y56 ff3 fs7 fc3 sc0 ls0 ws0">supply rail drop</div><div class="t m0 x3 he y57 ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 x29 he y58 ff3 fs7 fc0 sc0 ls0 ws0">growing importan<span class="_ _0"></span>ce of </div><div class="t m0 x2a he y59 ff3 fs7 fc3 sc0 ls0 ws0">growing importan<span class="_ _0"></span>ce of </div><div class="t m0 x29 he y5a ff3 fs7 fc0 sc0 ls0 ws0">interconnect</div><div class="t m0 x2a he y5b ff3 fs7 fc3 sc0 ls0 ws0">interconnect</div><div class="t m0 x3 he y5c ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 x29 he y5d ff3 fs7 fc0 sc0 ls0 ws0">noise, crosstalk</div><div class="t m0 x2a he y5e ff3 fs7 fc3 sc0 ls0 ws0">noise, crosstalk</div><div class="t m0 x3 he y5f ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 x29 he y60 ff3 fs7 fc0 sc0 ls0 ws0">reliability, </div><div class="t m0 x2a he y61 ff3 fs7 fc3 sc0 ls0 ws0">reliability, </div><div class="t m0 x29 he y62 ff3 fs7 fc0 sc0 ls0 ws0">manufacturability</div><div class="t m0 x2a he y63 ff3 fs7 fc3 sc0 ls0 ws0">manufacturability</div><div class="t m0 x3 he y64 ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 x29 he y65 ff3 fs7 fc0 sc0 ls0 ws0">clock distributio<span class="_ _0"></span>n</div><div class="t m0 x2a he y66 ff3 fs7 fc3 sc0 ls0 ws0">clock distributio<span class="_ _0"></span>n</div><div class="t m0 x2b hd y67 ff2 fs6 fc2 sc0 ls0 ws0"></div><div class="t m0 x2c he y4d ff3 fs7 fc0 sc0 ls0 ws0">Macroscopic issues</div><div class="t m0 x2d he y4e ff3 fs7 fc3 sc0 ls0 ws0">Macroscopic issues</div><div class="t m0 x2e he y4f ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y50 ff3 fs7 fc0 sc0 ls0 ws0">time-to-market</div><div class="t m0 xf he y51 ff3 fs7 fc3 sc0 ls0 ws0">time-to-market</div><div class="t m0 x2e he y52 ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y68 ff3 fs7 fc0 sc0 ls0 ws0">design complexity </div><div class="t m0 xf he y69 ff3 fs7 fc3 sc0 ls0 ws0">design complexity </div><div class="t m0 xe he y55 ff3 fs7 fc0 sc0 ls0 ws0">(millions of gates)</div><div class="t m0 xf he y56 ff3 fs7 fc3 sc0 ls0 ws0">(millions of gates)</div><div class="t m0 x2e he y6a ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y58 ff3 fs7 fc0 sc0 ls0 ws0">high levels of </div><div class="t m0 xf he y59 ff3 fs7 fc3 sc0 ls0 ws0">high levels of </div><div class="t m0 xe he y6b ff3 fs7 fc0 sc0 ls0 ws0">abstractions</div><div class="t m0 xf he y6c ff3 fs7 fc3 sc0 ls0 ws0">abstractions</div><div class="t m0 x2e he y5c ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y6d ff3 fs7 fc0 sc0 ls0 ws0">design for test</div><div class="t m0 xf he y6e ff3 fs7 fc3 sc0 ls0 ws0">design for test</div><div class="t m0 x2e he y5f ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y60 ff3 fs7 fc0 sc0 ls0 ws0">reuse and IP, portability</div><div class="t m0 xf he y61 ff3 fs7 fc3 sc0 ls0 ws0">reuse and IP, portability</div><div class="t m0 x2e he y6f ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y70 ff3 fs7 fc0 sc0 ls0 ws0">systems on a chip (SoC)</div><div class="t m0 xf he y71 ff3 fs7 fc3 sc0 ls0 ws0">systems on a chip (SoC)</div><div class="t m0 x2e he y72 ff3 fs7 fc3 sc0 ls0 ws0">–</div><div class="t m0 xe he y73 ff3 fs7 fc0 sc0 ls0 ws0">tool interoperabil<span class="_ _0"></span>ity</div><div class="t m0 xf he y74 ff3 fs7 fc3 sc0 ls0 ws0">tool interoperabil<span class="_ _0"></span>ity</div><div class="t m0 x2f hc y75 ff3 fs5 fc0 sc0 ls0 ws0">Year</div><div class="t m0 x29 hc y76 ff3 fs5 fc3 sc0 ls0 ws0">Year</div><div class="t m0 x30 hc y75 ff3 fs5 fc0 sc0 ls0 ws0">Tech.</div><div class="t m0 x31 hc y76 ff3 fs5 fc3 sc0 ls0 ws0">Tech.</div><div class="t m0 x32 hc y75 ff3 fs5 fc0 sc0 ls0 ws0">Complexity</div><div class="t m0 x33 hc y76 ff3 fs5 fc3 sc0 ls0 ws0">Complexity</div><div class="t m0 x34 hc y75 ff3 fs5 fc0 sc0 ls0 ws0">Frequency</div><div class="t m0 x35 hc y76 ff3 fs5 fc3 sc0 ls0 ws0">Frequency</div><div class="t m0 x36 hc y75 ff3 fs5 fc0 sc0 ls0 ws0">Staff Size</div><div class="t m0 x37 hc y76 ff3 fs5 fc3 sc0 ls0 ws0">Staff Size</div><div class="t m0 x38 hc y75 ff3 fs5 fc0 sc0 ls0 ws0">Staff Costs</div><div class="t m0 x39 hc y76 ff3 fs5 fc3 sc0 ls0 ws0">Staff Costs</div><div class="t m0 x2f hc y77 ff3 fs5 fc0 sc0 ls0 ws0">1997</div><div class="t m0 x29 hc y78 ff3 fs5 fc3 sc0 ls0 ws0">1997</div><div class="t m0 x3a hc y77 ff3 fs5 fc0 sc0 ls0 ws0">0.35</div><div class="t m0 x3b hc y78 ff3 fs5 fc3 sc0 ls0 ws0">0.35</div><div class="t m0 x8 hc y77 ff3 fs5 fc0 sc0 ls0 ws0">13 M Tr.</div><div class="t m0 x9 hc y78 ff3 fs5 fc3 sc0 ls0 ws0">13 M Tr.</div><div class="t m0 x3c hc y77 ff3 fs5 fc0 sc0 ls0 ws0">400 MHz</div><div class="t m0 x12 hc y78 ff3 fs5 fc3 sc0 ls0 ws0">400 MHz</div><div class="t m0 x3d hc y77 ff3 fs5 fc0 sc0 ls0 ws0">210</div><div class="t m0 x3e hc y78 ff3 fs5 fc3 sc0 ls0 ws0">210</div><div class="t m0 x3f hc y77 ff3 fs5 fc0 sc0 ls0 ws0">$90 M</div><div class="t m0 x40 hc y78 ff3 fs5 fc3 sc0 ls0 ws0">$90 M</div><div class="t m0 x2f hc y79 ff3 fs5 fc0 sc0 ls0 ws0">1998</div><div class="t m0 x29 hc y7a ff3 fs5 fc3 sc0 ls0 ws0">1998</div><div class="t m0 x3a hc y79 ff3 fs5 fc0 sc0 ls0 ws0">0.25</div><div class="t m0 x3b hc y7a ff3 fs5 fc3 sc0 ls0 ws0">0.25</div><div class="t m0 x8 hc y79 ff3 fs5 fc0 sc0 ls0 ws0">20 M Tr.</div><div class="t m0 x9 hc y7a ff3 fs5 fc3 sc0 ls0 ws0">20 M Tr.</div><div class="t m0 x3c hc y79 ff3 fs5 fc0 sc0 ls0 ws0">500 MHz</div><div class="t m0 x12 hc y7a ff3 fs5 fc3 sc0 ls0 ws0">500 MHz</div><div class="t m0 x3d hc y79 ff3 fs5 fc0 sc0 ls0 ws0">270</div><div class="t m0 x3e hc y7a ff3 fs5 fc3 sc0 ls0 ws0">270</div><div class="t m0 x41 hc y79 ff3 fs5 fc0 sc0 ls0 ws0">$120 M</div><div class="t m0 x42 hc y7a ff3 fs5 fc3 sc0 ls0 ws0">$120 M</div><div class="t m0 x2f hc y7b ff3 fs5 fc0 sc0 ls0 ws0">1999</div><div class="t m0 x29 hc y7c ff3 fs5 fc3 sc0 ls0 ws0">1999</div><div class="t m0 x3a hc y7b ff3 fs5 fc0 sc0 ls0 ws0">0.18</div><div class="t m0 x3b hc y7c ff3 fs5 fc3 sc0 ls0 ws0">0.18</div><div class="t m0 x8 hc y7b ff3 fs5 fc0 sc0 ls0 ws0">32 M Tr.</div><div class="t m0 x9 hc y7c ff3 fs5 fc3 sc0 ls0 ws0">32 M Tr.</div><div class="t m0 x3c hc y7b ff3 fs5 fc0 sc0 ls0 ws0">600 MHz</div><div class="t m0 x12 hc y7c ff3 fs5 fc3 sc0 ls0 ws0">600 MHz</div><div class="t m0 x3d hc y7b ff3 fs5 fc0 sc0 ls0 ws0">360</div><div class="t m0 x3e hc y7c ff3 fs5 fc3 sc0 ls0 ws0">360</div><div class="t m0 x41 hc y7b ff3 fs5 fc0 sc0 ls0 ws0">$160 M</div><div class="t m0 x42 hc y7c ff3 fs5 fc3 sc0 ls0 ws0">$160 M</div><div class="t m0 x2f hc y7d ff3 fs5 fc0 sc0 ls0 ws0">2002</div><div class="t m0 x29 hc y7e ff3 fs5 fc3 sc0 ls0 ws0">2002</div><div class="t m0 x3a hc y7d ff3 fs5 fc0 sc0 ls0 ws0">0.13</div><div class="t m0 x3b hc y7e ff3 fs5 fc3 sc0 ls0 ws0">0.13</div><div class="t m0 x43 hc y7d ff3 fs5 fc0 sc0 ls0 ws0">130 M Tr.</div><div class="t m0 x44 hc y7e ff3 fs5 fc3 sc0 ls0 ws0">130 M Tr.</div><div class="t m0 x3c hc y7d ff3 fs5 fc0 sc0 ls0 ws0">800 MHz</div><div class="t m0 x12 hc y7e ff3 fs5 fc3 sc0 ls0 ws0">800 MHz</div><div class="t m0 x3d hc y7d ff3 fs5 fc0 sc0 ls0 ws0">800</div><div class="t m0 x3e hc y7e ff3 fs5 fc3 sc0 ls0 ws0">800</div><div class="t m0 x41 hc y7d ff3 fs5 fc0 sc0 ls0 ws0">$360 M</div><div class="t m0 x42 hc y7e ff3 fs5 fc3 sc0 ls0 ws0">$360 M</div></div></div><div class="pi" data-data='{"ctm":[1.333333,0.000000,0.000000,1.333333,0.000000,0.000000]}'></div></div>
