mxl111sf-demod.rar

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  • 2014-03-31 11:52
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driver for the MaxLinear MXL111SF DVB-T demodulator.
mxl111sf-demod.rar
  • mxl111sf-demod.c
    13.8KB
  • mxl111sf-demod.h
    994B
内容介绍
#include "mxl111sf-demod.h" #include "mxl111sf-reg.h" /* debug */ static int mxl111sf_demod_debug; module_param_named(debug, mxl111sf_demod_debug, int, 0644); MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); #define mxl_dbg(fmt, arg...) \ if (mxl111sf_demod_debug) \ mxl_printk(KERN_DEBUG, fmt, ##arg) /* ------------------------------------------------------------------------ */ struct mxl111sf_demod_state { struct mxl111sf_state *mxl_state; struct mxl111sf_demod_config *cfg; struct dvb_frontend fe; }; /* ------------------------------------------------------------------------ */ static int mxl111sf_demod_read_reg(struct mxl111sf_demod_state *state, u8 addr, u8 *data) { return (state->cfg->read_reg) ? state->cfg->read_reg(state->mxl_state, addr, data) : -EINVAL; } static int mxl111sf_demod_write_reg(struct mxl111sf_demod_state *state, u8 addr, u8 data) { return (state->cfg->write_reg) ? state->cfg->write_reg(state->mxl_state, addr, data) : -EINVAL; } static int mxl111sf_demod_program_regs(struct mxl111sf_demod_state *state, struct mxl111sf_reg_ctrl_info *ctrl_reg_info) { return (state->cfg->program_regs) ? state->cfg->program_regs(state->mxl_state, ctrl_reg_info) : -EINVAL; } /* ------------------------------------------------------------------------ */ /* TPS */ static int mxl1x1sf_demod_get_tps_code_rate(struct mxl111sf_demod_state *state, fe_code_rate_t *code_rate) { u8 val; int ret = mxl111sf_demod_read_reg(state, V6_CODE_RATE_TPS_REG, &val); /* bit<2:0> - 000:1/2, 001:2/3, 010:3/4, 011:5/6, 100:7/8 */ if (mxl_fail(ret)) goto fail; switch (val & V6_CODE_RATE_TPS_MASK) { case 0: *code_rate = FEC_1_2; break; case 1: *code_rate = FEC_2_3; break; case 2: *code_rate = FEC_3_4; break; case 3: *code_rate = FEC_5_6; break; case 4: *code_rate = FEC_7_8; break; } fail: return ret; } static int mxl1x1sf_demod_get_tps_modulation(struct mxl111sf_demod_state *state, fe_modulation_t *modulation) { u8 val; int ret = mxl111sf_demod_read_reg(state, V6_MODORDER_TPS_REG, &val); /* Constellation, 00 : QPSK, 01 : 16QAM, 10:64QAM */ if (mxl_fail(ret)) goto fail; switch ((val & V6_PARAM_CONSTELLATION_MASK) >> 4) { case 0: *modulation = QPSK; break; case 1: *modulation = QAM_16; break; case 2: *modulation = QAM_64; break; } fail: return ret; } static int mxl1x1sf_demod_get_tps_guard_fft_mode(struct mxl111sf_demod_state *state, fe_transmit_mode_t *fft_mode) { u8 val; int ret = mxl111sf_demod_read_reg(state, V6_MODE_TPS_REG, &val); /* FFT Mode, 00:2K, 01:8K, 10:4K */ if (mxl_fail(ret)) goto fail; switch ((val & V6_PARAM_FFT_MODE_MASK) >> 2) { case 0: *fft_mode = TRANSMISSION_MODE_2K; break; case 1: *fft_mode = TRANSMISSION_MODE_8K; break; case 2: *fft_mode = TRANSMISSION_MODE_4K; break; } fail: return ret; } static int mxl1x1sf_demod_get_tps_guard_interval(struct mxl111sf_demod_state *state, fe_guard_interval_t *guard) { u8 val; int ret = mxl111sf_demod_read_reg(state, V6_CP_TPS_REG, &val); /* 00:1/32, 01:1/16, 10:1/8, 11:1/4 */ if (mxl_fail(ret)) goto fail; switch ((val & V6_PARAM_GI_MASK) >> 4) { case 0: *guard = GUARD_INTERVAL_1_32; break; case 1: *guard = GUARD_INTERVAL_1_16; break; case 2: *guard = GUARD_INTERVAL_1_8; break; case 3: *guard = GUARD_INTERVAL_1_4; break; } fail: return ret; } static int mxl1x1sf_demod_get_tps_hierarchy(struct mxl111sf_demod_state *state, fe_hierarchy_t *hierarchy) { u8 val; int ret = mxl111sf_demod_read_reg(state, V6_TPS_HIERACHY_REG, &val); /* bit<6:4> - 000:Non hierarchy, 001:1, 010:2, 011:4 */ if (mxl_fail(ret)) goto fail; switch ((val & V6_TPS_HIERARCHY_INFO_MASK) >> 6) { case 0: *hierarchy = HIERARCHY_NONE; break; case 1: *hierarchy = HIERARCHY_1; break; case 2: *hierarchy = HIERARCHY_2; break; case 3: *hierarchy = HIERARCHY_4; break; } fail: return ret; } /* ------------------------------------------------------------------------ */ /* LOCKS */ static int mxl1x1sf_demod_get_sync_lock_status(struct mxl111sf_demod_state *state, int *sync_lock) { u8 val = 0; int ret = mxl111sf_demod_read_reg(state, V6_SYNC_LOCK_REG, &val); if (mxl_fail(ret)) goto fail; *sync_lock = (val & SYNC_LOCK_MASK) >> 4; fail: return ret; } static int mxl1x1sf_demod_get_rs_lock_status(struct mxl111sf_demod_state *state, int *rs_lock) { u8 val = 0; int ret = mxl111sf_demod_read_reg(state, V6_RS_LOCK_DET_REG, &val); if (mxl_fail(ret)) goto fail; *rs_lock = (val & RS_LOCK_DET_MASK) >> 3; fail: return ret; } static int mxl1x1sf_demod_get_tps_lock_status(struct mxl111sf_demod_state *state, int *tps_lock) { u8 val = 0; int ret = mxl111sf_demod_read_reg(state, V6_TPS_LOCK_REG, &val); if (mxl_fail(ret)) goto fail; *tps_lock = (val & V6_PARAM_TPS_LOCK_MASK) >> 6; fail: return ret; } static int mxl1x1sf_demod_get_fec_lock_status(struct mxl111sf_demod_state *state, int *fec_lock) { u8 val = 0; int ret = mxl111sf_demod_read_reg(state, V6_IRQ_STATUS_REG, &val); if (mxl_fail(ret)) goto fail; *fec_lock = (val & IRQ_MASK_FEC_LOCK) >> 4; fail: return ret; } #if 0 static int mxl1x1sf_demod_get_cp_lock_status(struct mxl111sf_demod_state *state, int *cp_lock) { u8 val = 0; int ret = mxl111sf_demod_read_reg(state, V6_CP_LOCK_DET_REG, &val); if (mxl_fail(ret)) goto fail; *cp_lock = (val & V6_CP_LOCK_DET_MASK) >> 2; fail: return ret; } #endif static int mxl1x1sf_demod_reset_irq_status(struct mxl111sf_demod_state *state) { return mxl111sf_demod_write_reg(state, 0x0e, 0xff); } /* ------------------------------------------------------------------------ */ static int mxl111sf_demod_set_frontend(struct dvb_frontend *fe) { struct mxl111sf_demod_state *state = fe->demodulator_priv; int ret = 0; struct mxl111sf_reg_ctrl_info phy_pll_patch[] = { {0x00, 0xff, 0x01}, /* change page to 1 */ {0x40, 0xff, 0x05}, {0x40, 0xff, 0x01}, {0x41, 0xff, 0xca}, {0x41, 0xff, 0xc0}, {0x00, 0xff, 0x00}, /* change page to 0 */ {0, 0, 0} }; mxl_dbg("()"); if (fe->ops.tuner_ops.set_params) { ret = fe->ops.tuner_ops.set_params(fe); if (mxl_fail(ret)) goto fail; msleep(50); } ret = mxl111sf_demod_program_regs(state, phy_pll_patch); mxl_fail(ret); msleep(50); ret = mxl1x1sf_demod_reset_irq_status(state); mxl_fail(ret); msleep(100); fail: return ret; } /* ------------------------------------------------------------------------ */ #if 0 /* resets TS Packet error count */ /* After setting 7th bit of V5_PER_COUNT_RESET_REG, it should be reset to 0. */ static int mxl1x1sf_demod_reset_packet_error_count(struct mxl111sf_demod_state *state) { struct mxl111sf_reg_ctrl_info reset_per_count[] = { {0x20, 0x01, 0x01}, {0x20, 0x01, 0x00}, {0, 0, 0} }; return mxl111sf_demod_program_regs(state, reset_per_count); } #endif /* returns TS Packet error count */ /* PER Count = FEC_PER_COUNT * (2 ** (FEC_PER_SCALE * 4)) */ static int mxl111sf_demod_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) { struct mxl111sf_demod_state *state = fe->demodulator_priv; u32 fec_per_count, fec_per_scale; u8 val; int ret; *ucblocks = 0; /* FEC_PER_COUNT Register */ ret = mxl111sf_demod_read_reg(state, V6_FEC_PER_COUNT_REG, &val); if (mxl_fail(ret)) goto fail; fec_per_count = val; /* FEC_PER_SCALE Register */ ret = mxl111sf_demod_read_reg(state, V6_FEC_PER_SCALE_REG, &val); if (mxl_fail(ret)) goto fail; val &= V6_FEC_PER_SCALE_MASK; val *= 4; fec_per_scale = 1 << val; fec_per_count *= fec_per_scale; *ucblocks = fec_per_count; fail: return ret; } #ifdef MXL111SF_DEMOD_ENABLE_CALCULATIONS /* FIXME: leaving this enabled breaks the build on some architectures, * and we shouldn't have any floating point math in the kernel, anyway. * * These macros need to be re-written, but it's harmless to simply * return zero fo
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