PIC24H.zip_pic24h_www。diopic。com_单片机开发_嵌入式/单片机/硬件编程下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/62512b1674bc5c010595a7a0/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62512b1674bc5c010595a7a0/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"><span class="ff2 ls1 ws1"> 2009-2012 Microchip Technology Inc.<span class="_ _0"> </span><span class="ls2 ws2">DS70592D-page 1</span></span></div><div class="t m0 x2 h3 y2 ff3 fs1 fc0 sc0 ls3 ws0">PIC24HJXXXGPX06A/X08A/X10A</div><div class="t m0 x1 h4 y3 ff3 fs2 fc0 sc0 ls4 ws3">Operating Condi<span class="_ _1"></span>tions</div><div class="t m0 x1 h5 y4 ff2 fs3 fc0 sc0 ls5 ws4">•<span class="_ _2"> </span>3.0V to 3.<span class="_ _1"></span>6V<span class="_ _3"></span>, -40ºC to +<span class="_ _1"></span>150ºC, DC to 2<span class="_ _1"></span>0 MIPS</div><div class="t m0 x1 h5 y5 ff2 fs3 fc0 sc0 ls5 ws4">•<span class="_ _2"> </span>3.0V to 3.<span class="_ _1"></span>6V<span class="_ _3"></span>, -40ºC to +<span class="_ _1"></span>125ºC, DC to 4<span class="_ _1"></span>0 MIPS</div><div class="t m0 x1 h4 y6 ff3 fs2 fc0 sc0 ls4 ws3">Core: 16-bi<span class="_ _1"></span>t PIC24H CPU</div><div class="t m0 x1 h5 y7 ff2 fs3 fc0 sc0 ls6 ws5">•<span class="_ _2"> </span>Code-e<span class="_ _1"></span>ffi<span class="_ _1"></span>cient (C<span class="_ _1"></span> and Asse<span class="_ _1"></span>mbly)<span class="_ _1"></span> archit<span class="_ _1"></span>ecture</div><div class="t m0 x1 h5 y8 ff2 fs3 fc0 sc0 ls7 ws6">•<span class="_ _2"> </span>Singl<span class="_ _1"></span>e-cycle<span class="_ _1"></span> mixe<span class="_ _1"></span>d-sign MUL<span class="_ _1"></span> plus<span class="_ _1"></span> hardware<span class="_ _1"></span> divid<span class="_ _1"></span>e</div><div class="t m0 x1 h4 y9 ff3 fs2 fc0 sc0 ls8 ws7">Clock Management</div><div class="t m0 x1 h5 ya ff2 fs3 fc0 sc0 ls9 ws8">•<span class="_ _2"> </span>±2% in<span class="_ _1"></span>ternal <span class="_ _1"></span>oscilla<span class="_ _1"></span>tor</div><div class="t m0 x1 h5 yb ff2 fs3 fc0 sc0 lsa ws9">•<span class="_ _2"> </span>Program<span class="_ _1"></span>mable PL<span class="_ _1"></span>Ls and<span class="_ _1"></span> oscill<span class="_ _1"></span>ator cl<span class="_ _1"></span>ock sou<span class="_ _1"></span>rces</div><div class="t m0 x1 h5 yc ff2 fs3 fc0 sc0 lsb wsa">•<span class="_ _2"> </span>Fail-Safe<span class="_ _1"></span> Clock <span class="_ _1"></span>Monit<span class="_ _1"></span>or (FSCM)</div><div class="t m0 x1 h5 yd ff2 fs3 fc0 sc0 lsc wsb">•<span class="_ _2"> </span>Indepen<span class="_ _1"></span>dent W<span class="_ _4"></span>atchdog<span class="_ _4"></span> Timer (W<span class="_ _4"></span>DT)</div><div class="t m0 x1 h5 ye ff2 fs3 fc0 sc0 lsb wsa">•<span class="_ _2"> </span>Fast w<span class="_ _1"></span>ake-up an<span class="_ _1"></span>d start-<span class="_ _4"></span>up</div><div class="t m0 x1 h4 yf ff3 fs2 fc0 sc0 lsd wsc">Power Management</div><div class="t m0 x1 h5 y10 ff2 fs3 fc0 sc0 ls6 ws5">•<span class="_ _2"> </span>Low-po<span class="_ _4"></span>wer management m<span class="_ _4"></span>odes (Sleep, Idle<span class="_ _4"></span>, </div><div class="t m0 x3 h5 y11 ff2 fs3 fc0 sc0 lse ws0">Doze)</div><div class="t m0 x1 h5 y12 ff2 fs3 fc0 sc0 lsf wsd">•<span class="_ _2"> </span>Integrate<span class="_ _4"></span>d Power-on Reset a<span class="_ _1"></span>nd Brown-o<span class="_ _1"></span>ut Reset</div><div class="t m0 x1 h5 y13 ff2 fs3 fc0 sc0 ls10 wse">•<span class="_ _2"> </span>1.35 mA/M<span class="_ _4"></span>Hz dynamic c<span class="_ _1"></span>urrent (typi<span class="_ _1"></span>cal)</div><div class="t m0 x1 h6 y14 ff2 fs3 fc0 sc0 ls11 ws0">•5<span class="_ _5"></span>5<span class="_ _5"></span> <span class="_ _5"></span><span class="ff4 ls0">μ<span class="ff2 ls12 wsf">A I<span class="fs4 ls13 ws0">PD</span><span class="ls14 ws10"> current (typical)</span></span></span></div><div class="t m0 x1 h4 y15 ff3 fs2 fc0 sc0 ls15 ws11">Advanced Analog F<span class="_ _4"></span>eatures</div><div class="t m0 x1 h5 y16 ff2 fs3 fc0 sc0 ls16 ws12">•<span class="_ _2"> </span>T<span class="_ _4"></span>wo ADC modules:</div><div class="t m0 x3 h5 y17 ff2 fs3 fc0 sc0 ls10 wse">-<span class="_ _2"> </span>Configurable<span class="_ _4"></span> as 10-bit, 1.1 M<span class="_ _4"></span>s<span class="_ _6"></span>ps wi<span class="_ _4"></span>th four </div><div class="t m0 x4 h5 y18 ff2 fs3 fc0 sc0 ls17 ws13">S&H or 12<span class="_ _1"></span>-bit, 500 k<span class="_ _4"></span>s<span class="_ _6"></span>ps <span class="_ _4"></span>w<span class="_ _6"></span>ith one<span class="_ _1"></span> S&H</div><div class="t m0 x3 h5 y19 ff2 fs3 fc0 sc0 ls9 ws14">-<span class="_ _2"> </span>18 analog <span class="_ _4"></span>inputs on 6<span class="_ _4"></span>4-pin devices<span class="_ _1"></span> and u<span class="_ _1"></span>p to </div><div class="t m0 x4 h5 y1a ff2 fs3 fc0 sc0 ls7 ws6">32 anal<span class="_ _4"></span>og inputs<span class="_ _1"></span> on 100-pi<span class="_ _4"></span>n devices</div><div class="t m0 x1 h5 y1b ff2 fs3 fc0 sc0 ls9 ws14">•<span class="_ _2"> </span>Flexibl<span class="_ _4"></span>e <span class="_ _6"></span>and indepe<span class="_ _1"></span>ndent ADC trigger sou<span class="_ _4"></span>rces</div><div class="t m0 x1 h4 y1c ff3 fs2 fc0 sc0 ls18 ws15">Timer<span class="_ _4"></span>s/Output Compare/I<span class="_ _4"></span>nput Capture</div><div class="t m0 x1 h5 y1d ff2 fs3 fc0 sc0 ls17 ws13">•<span class="_ _2"> </span>Up to n<span class="_ _1"></span>ine 16-bi<span class="_ _4"></span>t timers/counters. Ca<span class="_ _1"></span>n pair u<span class="_ _4"></span>p to </div><div class="t m0 x3 h5 y1e ff2 fs3 fc0 sc0 lsc wsb">make fo<span class="_ _1"></span>ur 32-bit ti<span class="_ _4"></span>mers.</div><div class="t m0 x1 h5 y1f ff2 fs3 fc0 sc0 ls19 ws16">•<span class="_ _2"> </span>Eight<span class="_ _4"></span> Output Comp<span class="_ _4"></span>are module<span class="_ _1"></span>s config<span class="_ _4"></span>urable as </div><div class="t m0 x3 h5 y20 ff2 fs3 fc0 sc0 ls7 ws0">timers/<span class="_ _4"></span>counters</div><div class="t m0 x1 h5 y21 ff2 fs3 fc0 sc0 ls6 ws5">•<span class="_ _2"> </span>Eight<span class="_ _1"></span> Input Ca<span class="_ _4"></span>pture modules</div><div class="t m0 x5 h4 y3 ff3 fs2 fc0 sc0 ls1a ws17">Communication Interf<span class="_ _1"></span>aces</div><div class="t m0 x5 h5 y22 ff2 fs3 fc0 sc0 ls1b ws18">•<span class="_ _2"> </span>T<span class="_ _4"></span>wo UAR<span class="_ _4"></span>T modules<span class="_ _4"></span> (10 Mbps<span class="_ _1"></span>)</div><div class="t m0 x6 h5 y23 ff2 fs3 fc0 sc0 lsb wsa">-<span class="_ _2"> </span>With suppor<span class="_ _4"></span>t for LIN 2.0 proto<span class="_ _4"></span>cols and IrDA</div><div class="t m0 x7 h7 y24 ff2 fs4 fc0 sc0 ls0 ws0">®</div><div class="t m0 x5 h5 y25 ff2 fs3 fc0 sc0 ls10 wse">•<span class="_ _2"> </span>T<span class="_ _4"></span>wo 4-wi<span class="_ _1"></span>re SPI modul<span class="_ _4"></span>es (15 Mbps<span class="_ _1"></span>)</div><div class="t m0 x5 h5 y26 ff2 fs3 fc0 sc0 ls1c ws19">•<span class="_ _2"> </span>Up to two<span class="_ _1"></span> I</div><div class="t m0 x8 h7 y6 ff2 fs4 fc0 sc0 ls0 ws0">2</div><div class="t m0 x9 h5 y26 ff2 fs3 fc0 sc0 ls10 wse">C™ modu<span class="_ _1"></span>les (up to<span class="_ _4"></span> 1 Mbaud) with </div><div class="t m0 x6 h5 y27 ff2 fs3 fc0 sc0 ls1d ws1a">SMBus supp<span class="_ _4"></span>ort</div><div class="t m0 x5 h5 y28 ff2 fs3 fc0 sc0 ls1e ws1b">•<span class="_ _2"> </span>Up to two<span class="_ _4"></span> Enhanced CAN (EC<span class="_ _4"></span>AN) modules </div><div class="t m0 x6 h5 y29 ff2 fs3 fc0 sc0 lsc wsb">(1<span class="_"> </span>Mbaud<span class="_ _4"></span>) with 2.0B supp<span class="_ _1"></span>ort</div><div class="t m0 x5 h5 y2a ff2 fs3 fc0 sc0 lsb wsa">•<span class="_ _2"> </span>Dat<span class="_ _4"></span>a Converter Inte<span class="_ _1"></span>rface (DCI) <span class="_ _1"></span>module w<span class="_ _1"></span>ith I</div><div class="t m0 xa h7 y2b ff2 fs4 fc0 sc0 ls0 ws0">2</div><div class="t m0 xb h5 y2c ff2 fs3 fc0 sc0 ls12 ws0">S </div><div class="t m0 x6 h5 y2d ff2 fs3 fc0 sc0 ls1f ws1c">codec s<span class="_ _4"></span>upport</div><div class="t m0 x5 h4 y2e ff3 fs2 fc0 sc0 ls20 ws0">Input/Output</div><div class="t m0 x5 h5 y2f ff2 fs3 fc0 sc0 ls21 ws1d">•<span class="_ _2"> </span>Sink/<span class="_ _1"></span>Source up t<span class="_ _4"></span>o 10 mA (pin spec<span class="_ _4"></span>ific) for st<span class="_ _1"></span>an-</div><div class="t m0 x6 h5 y30 ff2 fs3 fc0 sc0 lsc wsb">dard V</div><div class="t m0 xc h5 y31 ff2 fs4 fc0 sc0 ls22 ws0">OH<span class="fs3 ls23">/V<span class="_ _4"></span><span class="fs4 ls24">OL<span class="fs3 ls25 ws1e">, up to 16<span class="_ _4"></span> mA (pin specif<span class="_ _1"></span>ic) for non<span class="_ _4"></span>-</span></span></span></div><div class="t m0 x6 h5 y32 ff2 fs3 fc0 sc0 ls26 ws1f">stan<span class="_ _4"></span>dard V</div><div class="t m0 x8 h7 y33 ff2 fs4 fc0 sc0 ls24 ws0">OH<span class="fs5 ls0">1</span></div><div class="t m0 x5 h5 y34 ff2 fs3 fc0 sc0 ls26 ws1f">•<span class="_ _2"> </span>5V<span class="_ _4"></span>-toleran<span class="_ _4"></span>t pins</div><div class="t m0 x5 h5 y35 ff2 fs3 fc0 sc0 ls9 ws8">•<span class="_ _2"> </span>Selec<span class="_ _1"></span>table <span class="_ _4"></span>open drain, pu<span class="_ _4"></span>ll-ups, and <span class="_ _4"></span>pull-downs</div><div class="t m0 x5 h5 y36 ff2 fs3 fc0 sc0 ls6 ws8">•<span class="_ _2"> </span>Up to 5<span class="_ _4"></span> mA overvolt<span class="_ _4"></span>age clamp curre<span class="_ _1"></span>nt</div><div class="t m0 x5 h5 y37 ff2 fs3 fc0 sc0 ls6 ws20">•<span class="_ _2"> </span>Extern<span class="_ _1"></span>al interrupt<span class="_ _4"></span>s on all I/O <span class="_ _6"></span>pins</div><div class="t m0 x5 h4 y38 ff3 fs2 fc0 sc0 ls27 ws21">Qualificat<span class="_ _1"></span>ion and Clas<span class="_ _4"></span>s B Support</div><div class="t m0 x5 h5 y39 ff2 fs3 fc0 sc0 ls14 ws10">•<span class="_ _2"> </span>AEC-Q100 REVG<span class="_ _1"></span> (Grade 1<span class="_ _1"></span> -40ºC to +1<span class="_ _4"></span>25ºC)</div><div class="t m0 x5 h5 y3a ff2 fs3 fc0 sc0 ls14 ws10">•<span class="_ _2"> </span>AEC-Q100 REVG<span class="_ _1"></span> (Grade 0<span class="_ _1"></span> -40ºC to +1<span class="_ _4"></span>50ºC)</div><div class="t m0 x5 h5 y3b ff2 fs3 fc0 sc0 ls28 ws22">•<span class="_ _2"> </span>Class B Sa<span class="_ _4"></span>fety Library<span class="_ _3"></span>, IEC 60730</div><div class="t m0 x5 h4 y3c ff3 fs2 fc0 sc0 ls29 ws23">Debugger Development<span class="_ _4"></span> Support</div><div class="t m0 x5 h5 y3d ff2 fs3 fc0 sc0 ls6 ws20">•<span class="_ _2"> </span>In-ci<span class="_ _1"></span>rcuit and in-appl<span class="_ _4"></span>ication programmi<span class="_ _1"></span>ng</div><div class="t m0 x5 h5 y3e ff2 fs3 fc0 sc0 ls6 ws5">•<span class="_ _2"> </span>T<span class="_ _4"></span>wo program<span class="_ _4"></span> and two comple<span class="_ _4"></span>x data bre<span class="_ _1"></span>akpoint<span class="_ _4"></span>s</div><div class="t m0 x5 h5 y3f ff2 fs3 fc0 sc0 ls2a ws24">•<span class="_ _2"> </span>IEEE 1<span class="_ _3"></span>149.2-compat<span class="_ _4"></span>i<span class="_ _6"></span>ble (JT<span class="_ _3"></span>AG) boundary scan</div><div class="t m0 x5 h5 y40 ff2 fs3 fc0 sc0 ls2a ws25">•<span class="_ _2"> </span>T<span class="_ _4"></span>race and run<span class="_ _1"></span>-time watch</div><div class="t m0 x1 h4 y41 ff3 fs2 fc0 sc0 ls2b ws0">Packages</div><div class="t m0 xd h8 y42 ff3 fs5 fc0 sc0 ls2c ws0">T<span class="_ _4"></span>ype<span class="_ _7"> </span>QFN<span class="_ _8"> </span>TQFP<span class="_ _9"> </span>TQFP<span class="_ _8"> </span>TQFP</div><div class="t m0 xe h8 y43 ff3 fs5 fc0 sc0 ls2d ws26">Pin Count<span class="_ _a"> </span><span class="ff2 ls2e ws0">64<span class="_ _b"> </span>64<span class="_ _c"> </span>100<span class="_ _d"> </span>100</span></div><div class="t m0 x4 h8 y44 ff3 fs5 fc0 sc0 ls2f ws27">Contact Lead/Pit<span class="_ _6"></span>ch<span class="_ _e"> </span><span class="ff2 ls30 ws0">0.50<span class="_ _f"> </span>0.50<span class="_ _10"> </span>0.50<span class="_ _11"> </span>0.40</span></div><div class="t m0 xf h8 y45 ff3 fs5 fc0 sc0 ls2c ws0">I/O Pin<span class="_ _6"></span>s<span class="_ _12"> </span><span class="ff2 ls2e">53<span class="_ _b"> </span>53<span class="_ _d"> </span>85<span class="_ _13"> </span>85</span></div><div class="t m0 x10 h8 y46 ff3 fs5 fc0 sc0 ls31 ws0">Dimensions<span class="_ _14"> </span><span class="ff2 ls32">9x9x0.9<span class="_ _15"> </span>10x10x1<span class="_ _16"> </span>12x12x1<span class="_ _17"> </span>14x14x1</span></div><div class="t m0 x11 h8 y47 ff3 fs5 fc0 sc0 ls33 ws0">Note:<span class="_ _18"> </span><span class="ff2 ls34 ws28">All dimensions are in millimeters (mm) <span class="_ _6"></span>unless specified.</span></div><div class="t m0 x12 h9 y48 ff5 fs6 fc0 sc0 ls35 ws29">16-bit Micr<span class="_ _4"></span>ocontrollers <span class="ws2a">(up to 256 KB Flash and </span></div><div class="t m0 x13 h9 y49 ff5 fs6 fc0 sc0 ls35 ws29">16<span class="_"> </span>KB<span class="_"> </span>SRAM) <span class="_ _1"></span>with Advanced Analog</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62512b1674bc5c010595a7a0/bg2.jpg"><div class="t m1 x14 h3 y4a ff3 fs1 fc0 sc0 ls36 ws0">PIC24HJXXXGPX06A/X08A/X10A</div><div class="t m1 x14 h2 y4b ff2 fs0 fc0 sc0 ls37 ws2b">DS70592D-page 2<span class="_ _0"> </span><span class="ff1 ls0 ws0"></span><span class="ls38 ws2c"> 2009-2012 Microchip Technology Inc.</span></div><div class="t m1 x14 ha y4c ff3 fs7 fc0 sc0 ls39 ws2d">PIC24H PRODUCT FAMILIES</div><div class="t m1 x14 h5 y4d ff2 fs3 fc0 sc0 ls3a ws2e">The PIC24<span class="_ _1"></span>H Family<span class="_ _1"></span> of devices<span class="_ _1"></span> is<span class="_"> </span>i<span class="_ _4"></span>deal for a wide vari-</div><div class="t m1 x14 h5 y4e ff2 fs3 fc0 sc0 ls7 ws2f">ety of 16<span class="_ _1"></span>-bit MCU emb<span class="_ _1"></span>edded ap<span class="_ _1"></span>plication<span class="_ _4"></span>s. The device</div><div class="t m1 x14 h5 y4f ff2 fs3 fc0 sc0 ls3b ws30">names,<span class="_ _4"></span> <span class="_ _6"></span>pin count<span class="_ _4"></span>s, memory size<span class="_ _4"></span>s and peripheral<span class="_ _1"></span> avail-</div><div class="t m1 x14 h5 y50 ff2 fs3 fc0 sc0 ls3c ws31">ability<span class="_ _4"></span> of each device are<span class="_ _4"></span> <span class="_ _6"></span>listed bel<span class="_ _4"></span>ow<span class="_ _4"></span>, followed by the<span class="_ _4"></span>ir</div><div class="t m1 x14 h5 y51 ff2 fs3 fc0 sc0 ls26 ws1f">pinout d<span class="_ _4"></span>iagrams.</div><div class="t m1 x14 h4 y52 ff3 fs2 fc0 sc0 ls18 ws32">PIC24H Family <span class="_ _1"></span>Controllers</div><div class="t m1 x15 hb y53 ff3 fs0 fc0 sc0 ls3d ws0">Device<span class="_ _19"> </span>Pins</div><div class="t m1 x16 hb y54 ff3 fs0 fc0 sc0 ls3d ws0">Program </div><div class="t m1 x17 hb y53 ff3 fs0 fc0 sc0 ls3e ws0">Flash </div><div class="t m1 x18 hb y55 ff3 fs0 fc0 sc0 ls2 ws33">Memory (KB)</div><div class="t m2 x19 hb y56 ff3 fs0 fc0 sc0 ls3f ws0">RAM</div><div class="t m2 x1a hc y57 ff3 fs8 fc0 sc0 ls40 ws0">(1)<span class="_ _6"></span> </div><div class="t m2 x19 hb y58 ff3 fs0 fc0 sc0 ls3f ws0">(KB)</div><div class="t m2 x1b hb y59 ff3 fs0 fc0 sc0 ls41 ws34">DMA Channels</div><div class="t m2 x1c hb y5a ff3 fs0 fc0 sc0 ls1 ws35">Timer 16-bit</div><div class="t m2 x1d hb y5b ff3 fs0 fc0 sc0 ls42 ws36">Inpu<span class="_ _6"></span>t Ca<span class="_ _6"></span>ptur<span class="_ _6"></span>e</div><div class="t m2 x1e hb y5c ff3 fs0 fc0 sc0 ls43 ws37">Output<span class="_ _1"></span> Comp<span class="_ _1"></span>are</div><div class="t m2 x1f hb y5d ff3 fs0 fc0 sc0 ls44 ws38">Std.<span class="_ _6"></span> P<span class="_ _6"></span>WM</div><div class="t m2 x20 hb y5e ff3 fs0 fc0 sc0 ls45 ws0">Codec</div><div class="t m2 x21 hb y5f ff3 fs0 fc0 sc0 ls46 ws0">Inter<span class="_ _1"></span>face</div><div class="t m2 x8 hb y60 ff3 fs0 fc0 sc0 ls47 ws39"> ADC </div><div class="t m2 x22 hb y61 ff3 fs0 fc0 sc0 ls3f ws0">UART</div><div class="t m2 x23 hb y62 ff3 fs0 fc0 sc0 ls48 ws0">SPI</div><div class="t m2 x24 hb y60 ff3 fs0 fc0 sc0 ls0 ws0">I</div><div class="t m2 x25 hc y63 ff3 fs8 fc0 sc0 ls0 ws0">2</div><div class="t m2 x24 hb y64 ff3 fs0 fc0 sc0 ls3f ws0">C™</div><div class="t m2 x26 hb y65 ff3 fs0 fc0 sc0 ls3f ws0">CAN</div><div class="t m2 x27 hb y66 ff3 fs0 fc0 sc0 ls49 ws3a">I/O Pi<span class="_ _1"></span>ns (Max)</div><div class="t m2 x28 hc y3 ff3 fs8 fc0 sc0 ls40 ws0">(2)</div><div class="t m2 x29 hb y67 ff3 fs0 fc0 sc0 ls3e ws0">Packages</div><div class="t m0 x2a hd y68 ff2 fs0 fc0 sc0 ls1 ws3b">PIC24HJ64GP20<span class="_ _6"></span>6A<span class="_ _1a"> </span>64<span class="_ _1b"> </span>64<span class="_ _1c"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y69 ff2 fs0 fc0 sc0 ls4a ws3c">18 ch</div><div class="t m0 x2c hd y68 ff2 fs0 fc0 sc0 ls4b ws3d">221<span class="_ _21"> </span>0<span class="_ _4"></span>5<span class="_ _22"></span>3<span class="_ _23"></span>P<span class="_ _22"></span>T<span class="_ _24"></span>,<span class="_ _25"></span> M<span class="_ _25"></span>R</div><div class="t m0 x2a hd y6a ff2 fs0 fc0 sc0 ls37 ws3e">PIC24HJ64GP21<span class="_ _6"></span>0A<span class="_ _26"> </span>100<span class="_ _27"> </span>64<span class="_ _1c"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y6b ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y6a ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>0<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hd y6c ff2 fs0 fc0 sc0 ls1 ws3b">PIC24HJ64GP50<span class="_ _6"></span>6A<span class="_ _1a"> </span>64<span class="_ _1b"> </span>64<span class="_ _1c"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y6d ff2 fs0 fc0 sc0 ls4a ws3c">18 ch</div><div class="t m0 x2c hd y6c ff2 fs0 fc0 sc0 ls4b ws3d">222<span class="_ _21"> </span>1<span class="_ _4"></span>5<span class="_ _22"></span>3<span class="_ _23"></span>P<span class="_ _25"></span>T<span class="_ _28"></span>,<span class="_ _25"></span> M<span class="_ _25"></span>R</div><div class="t m0 x2a hd y6e ff2 fs0 fc0 sc0 ls37 ws3e">PIC24HJ64GP51<span class="_ _6"></span>0A<span class="_ _26"> </span>100<span class="_ _27"> </span>64<span class="_ _1c"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y6f ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y6e ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>1<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hd y70 ff2 fs0 fc0 sc0 ls4c ws40">PIC24HJ128GP2<span class="_ _6"></span>06A<span class="_ _29"> </span>64<span class="_ _27"> </span>128<span class="_ _19"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _2a"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y71 ff2 fs0 fc0 sc0 ls4a ws3c">18 ch</div><div class="t m0 x2c hd y70 ff2 fs0 fc0 sc0 ls4b ws3d">222<span class="_ _21"> </span>0<span class="_ _4"></span>5<span class="_ _22"></span>3<span class="_ _23"></span>P<span class="_ _25"></span>T<span class="_ _28"></span>,<span class="_ _25"></span> M<span class="_ _25"></span>R</div><div class="t m0 x2a hd y72 ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ128GP2<span class="_ _6"></span>10A<span class="_ _18"> </span>100<span class="_ _2b"> </span>128<span class="_ _19"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y73 ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y72 ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>0<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hd y74 ff2 fs0 fc0 sc0 ls4c ws40">PIC24HJ128GP5<span class="_ _6"></span>06A<span class="_ _29"> </span>64<span class="_ _27"> </span>128<span class="_ _19"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _2a"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y75 ff2 fs0 fc0 sc0 ls4a ws3c">18 ch</div><div class="t m0 x2c hd y74 ff2 fs0 fc0 sc0 ls4b ws3d">222<span class="_ _21"> </span>1<span class="_ _4"></span>5<span class="_ _22"></span>3<span class="_ _23"></span>P<span class="_ _25"></span>T<span class="_ _28"></span>,<span class="_ _25"></span> M<span class="_ _25"></span>R</div><div class="t m0 x2a hd y76 ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ128GP5<span class="_ _6"></span>10A<span class="_ _18"> </span>100<span class="_ _2b"> </span>128<span class="_ _19"> </span>8<span class="_ _1d"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y77 ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y76 ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>1<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hd y78 ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ128GP3<span class="_ _6"></span>06A<span class="_ _29"> </span>64<span class="_ _27"> </span>128<span class="_ _2c"> </span>16<span class="_ _20"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y79 ff2 fs0 fc0 sc0 ls4a ws3c">18 ch</div><div class="t m0 x2c hd y78 ff2 fs0 fc0 sc0 ls4b ws3d">222<span class="_ _21"> </span>0<span class="_ _4"></span>5<span class="_ _22"></span>3<span class="_ _23"></span>P<span class="_ _25"></span>T<span class="_ _28"></span>,<span class="_ _25"></span> M<span class="_ _25"></span>R</div><div class="t m0 x2a hd y7a ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ128GP3<span class="_ _6"></span>10A<span class="_ _18"> </span>100<span class="_ _2b"> </span>128<span class="_ _2c"> </span>16<span class="_ _20"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y7b ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y7a ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>0<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hd y7c ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ256GP2<span class="_ _6"></span>06A<span class="_ _29"> </span>64<span class="_ _27"> </span>256<span class="_ _2c"> </span>16<span class="_ _20"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y7d ff2 fs0 fc0 sc0 ls4a ws3c">18 ch</div><div class="t m0 x2c hd y7c ff2 fs0 fc0 sc0 ls4b ws3d">222<span class="_ _21"> </span>0<span class="_ _4"></span>5<span class="_ _22"></span>3<span class="_ _23"></span>P<span class="_ _25"></span>T<span class="_ _28"></span>,<span class="_ _25"></span> M<span class="_ _25"></span>R</div><div class="t m0 x2a hd y7e ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ256GP2<span class="_ _6"></span>10A<span class="_ _18"> </span>100<span class="_ _2b"> </span>256<span class="_ _2c"> </span>16<span class="_ _20"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>1 ADC, </div><div class="t m0 x2b hd y7f ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y7e ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>0<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hd y80 ff2 fs0 fc0 sc0 ls4d ws41">PIC24HJ256GP6<span class="_ _6"></span>10A<span class="_ _18"> </span>100<span class="_ _2b"> </span>256<span class="_ _2c"> </span>16<span class="_ _20"> </span>8<span class="_ _1d"> </span>9<span class="_ _1d"> </span>8<span class="_ _1e"> </span>8<span class="_ _1f"> </span>0<span class="_ _20"> </span>2 ADC, </div><div class="t m0 x2b hd y81 ff2 fs0 fc0 sc0 ls4a ws3c">32 ch</div><div class="t m0 x2c hd y80 ff2 fs0 fc0 sc0 ls4b ws3f">222<span class="_ _21"> </span>2<span class="_ _4"></span>8<span class="_ _22"></span>5<span class="_ _4"></span>P<span class="_ _25"></span>F<span class="_ _24"></span>,<span class="_ _22"></span> P<span class="_ _25"></span>T</div><div class="t m0 x2a hb y82 ff3 fs0 fc0 sc0 ls4e ws0">Not<span class="_ _4"></span>e<span class="_ _18"> </span>1:<span class="_ _2d"> </span><span class="ff2 ls4f ws42">RAM size is inclusive of 2 Kbytes DMA RAM.</span></div><div class="t m0 x3 hb y83 ff3 fs0 fc0 sc0 ls3e ws0">2:<span class="_ _2d"> </span><span class="ff2 ls50 ws43">Maxim<span class="_ _6"></span>um I/O pin count includes pins <span class="ls1 ws1">shared by the per<span class="ls37 ws44">ipheral f<span class="_ _1"></span>unctions.</span></span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62512b1674bc5c010595a7a0/bg3.jpg"><div class="t m0 x1 h2 y4b ff1 fs0 fc0 sc0 ls0 ws0"><span class="ff2 ls1 ws1"> 2009-2012 Microchip Technology Inc.<span class="_ _0"> </span><span class="ls2 ws2">DS70592D-page 3</span></span></div><div class="t m0 x2 h3 y4a ff3 fs1 fc0 sc0 ls3 ws0">PIC24HJXXXGPX06A/X08A/X10A</div><div class="t m0 x1 h4 y84 ff3 fs2 fc0 sc0 ls51 ws45">Pin Diagrams</div><div class="c x1 y85 w2 he"><div class="t m0 x2d hf y86 ff3 fs9 fc0 sc0 ls52 ws46">64-Pin QFN</div><div class="t m0 x2e hb y87 ff3 fs0 fc0 sc0 ls53 ws0">(1)</div><div class="t m0 x2f h10 y88 ff2 fs5 fc0 sc0 ls54 ws0">PGEC2/SO<span class="_ _1"></span>SCO/T1CK/<span class="_ _1"></span>CN0/RC14</div><div class="t m0 x2f h10 y89 ff2 fs5 fc0 sc0 ls54 ws0">PGED2/SO<span class="_ _1"></span>SCI/T4CK/<span class="_ _1"></span>CN1/RC13</div><div class="t m0 x2f h10 y8a ff2 fs5 fc0 sc0 ls55 ws0">OC1/RD0</div><div class="t m0 x2f h10 y8b ff2 fs5 fc0 sc0 ls56 ws0">IC4/INT4/RD1<span class="_ _4"></span>1</div><div class="t m0 x2f h10 y8c ff2 fs5 fc0 sc0 ls33 ws0">IC2/U1CTS</div><div class="t m0 x30 h10 y8d ff2 fs5 fc0 sc0 ls57 ws0">/INT2/RD9</div><div class="t m0 x2f h10 y8e ff2 fs5 fc0 sc0 ls56 ws0">IC1/INT1/RD8</div><div class="t m0 x2f h10 y8f ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m0 x31 h11 y90 ff2 fsa fc0 sc0 ls58 ws0">SS</div><div class="t m0 x2f h10 y91 ff2 fs5 fc0 sc0 ls59 ws0">OSC2/CLKO/RC1<span class="_ _6"></span>5</div><div class="t m0 x2f h10 y92 ff2 fs5 fc0 sc0 ls5a ws0">OSC1/CLKIN/RC12</div><div class="t m0 x2f h10 y93 ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m0 x31 h11 y94 ff2 fsa fc0 sc0 ls5b ws0">DD</div><div class="t m0 x2f h10 y95 ff2 fs5 fc0 sc0 ls5c ws0">SCL<span class="_ _6"></span>1/RG<span class="_ _6"></span>2</div><div class="t m0 x2f h10 y96 ff2 fs5 fc0 sc0 ls33 ws0">U1RTS</div><div class="t m0 x32 h10 y97 ff2 fs5 fc0 sc0 ls5d ws0">/SCK1/INT0/RF6</div><div class="t m0 x2f h10 y98 ff2 fs5 fc0 sc0 ls5e ws0">U1RX/SDI1/RF2</div><div class="t m0 x2f h10 y99 ff2 fs5 fc0 sc0 ls33 ws0">U1TX/SDO1/RF3</div><div class="t m0 x33 h10 y9a ff2 fs5 fc0 sc0 ls0 ws0">RG15</div><div class="t m0 x34 h10 y9b ff2 fs5 fc0 sc0 ls5f ws0">AN16/T2CK/T7<span class="_ _1"></span>CK/RC1</div><div class="t m0 x34 h10 y9c ff2 fs5 fc0 sc0 ls5f ws0">AN17/T3CK/T6<span class="_ _1"></span>CK/RC2</div><div class="t m0 x35 h10 y9d ff2 fs5 fc0 sc0 ls60 ws0">SCK2/CN8/RG6</div><div class="t m0 x36 h10 y9e ff2 fs5 fc0 sc0 ls55 ws0">SDI2/CN9/RG<span class="_ _6"></span>7</div><div class="t m0 x37 h10 y9f ff2 fs5 fc0 sc0 ls5e ws0">SDO2/CN10/RG8</div><div class="t m0 x38 h10 ya0 ff2 fs5 fc0 sc0 ls61 ws0">MCLR</div><div class="t m0 x39 h10 ya1 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls58">SS</span></div><div class="t m0 x39 h10 ya2 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls5b">DD</span></div><div class="t m0 x3a h10 ya3 ff2 fs5 fc0 sc0 ls62 ws0">AN3/CN5/RB3</div><div class="t m0 x3b h10 ya4 ff2 fs5 fc0 sc0 ls63 ws0">AN2/SS1</div><div class="t m0 x3c h10 ya5 ff2 fs5 fc0 sc0 ls64 ws0">/CN4/RB2</div><div class="t m0 x3d h10 ya6 ff2 fs5 fc0 sc0 ls65 ws0">PGEC3/AN1<span class="_ _4"></span>/V</div><div class="t m0 x11 h10 ya7 ff2 fsa fc0 sc0 ls66 ws0">REF<span class="fs5 ls67">-/CN3/RB1</span></div><div class="t m0 x3e h10 ya8 ff2 fs5 fc0 sc0 ls65 ws0">PGED3/AN0<span class="_ _4"></span>/V</div><div class="t m0 x1 h10 ya9 ff2 fsa fc0 sc0 ls66 ws0">REF<span class="fs5 ls68">+/CN2/RB0</span></div><div class="t m2 x3f h10 yaa ff2 fs5 fc0 sc0 ls69 ws0">OC8/CN16/RD7</div><div class="t m2 x40 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">RG13</div><div class="t m2 x41 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">RG12</div><div class="t m2 x16 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">RG14</div><div class="t m2 x19 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m2 x19 h11 yab ff2 fsa fc0 sc0 ls6a ws0">CAP</div><div class="t m2 x1a h12 yac ff3 fsa fc0 sc0 ls6b ws0">(3)</div><div class="t m2 x42 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">RG1</div><div class="t m2 x2 h10 yaa ff2 fs5 fc0 sc0 ls33 ws0">RF1</div><div class="t m2 x43 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">RG0</div><div class="t m2 x44 h10 yaa ff2 fs5 fc0 sc0 ls6c ws0">OC2/RD1</div><div class="t m2 x45 h10 yaa ff2 fs5 fc0 sc0 ls6c ws0">OC3/RD2</div><div class="t m2 x40 h10 yad ff2 fs5 fc0 sc0 ls6d ws0">PGEC1/AN6/OCF<span class="_ _4"></span>A/RB6</div><div class="t m2 x41 h10 yae ff2 fs5 fc0 sc0 ls6e ws0">PGED1/AN7/RB7</div><div class="t m2 x16 h10 yaf ff2 fs5 fc0 sc0 ls6f ws0">AV</div><div class="t m2 x16 h11 yb0 ff2 fsa fc0 sc0 ls6a ws0">DD</div><div class="t m2 x43 h10 yb1 ff2 fs5 fc0 sc0 ls70 ws0">AV<span class="_ _6"></span><span class="fsa ls58">SS</span></div><div class="t m2 x42 h10 yb2 ff2 fs5 fc0 sc0 ls33 ws0">U2CTS<span class="ls71">/AN8/RB8</span></div><div class="t m2 x2 h10 yb3 ff2 fs5 fc0 sc0 ls60 ws0">AN9/RB9</div><div class="t m2 x46 h10 yb4 ff2 fs5 fc0 sc0 ls6d ws0">TMS/AN10/RB10</div><div class="t m2 x47 h10 yb5 ff2 fs5 fc0 sc0 ls31 ws0">TDO/AN1<span class="_ _4"></span>1/RB1<span class="_ _1"></span>1</div><div class="t m2 x19 h10 yb6 ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m2 x19 h11 yb7 ff2 fsa fc0 sc0 ls58 ws0">SS</div><div class="t m2 x3f h10 yb8 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m2 x48 h10 yb9 ff2 fs5 fc0 sc0 ls72 ws0">TCK/AN12/RB12</div><div class="t m2 x49 h10 yba ff2 fs5 fc0 sc0 ls73 ws0">TDI/AN13/RB13</div><div class="t m2 x4a h10 ybb ff2 fs5 fc0 sc0 ls33 ws0">U2RTS</div><div class="t m2 x4a h10 ybc ff2 fs5 fc0 sc0 ls64 ws0">/AN14/RB14</div><div class="t m2 x4b h10 ybd ff2 fs5 fc0 sc0 ls69 ws0">AN15/OCFB/CN12/RB15</div><div class="t m2 x44 h10 ybe ff2 fs5 fc0 sc0 ls74 ws0">U2TX/SC<span class="_ _6"></span>L2/CN<span class="_ _6"></span>18/RF5</div><div class="t m2 x45 h13 ybf ff2 fs5 fc0 sc0 ls33 ws0">U2RX<span class="ff6 ls75">/SDA2/</span><span class="ls76">CN<span class="_ _6"></span>17/RF4</span></div><div class="t m0 x2f h10 yc0 ff2 fs5 fc0 sc0 ls31 ws0">SDA1/RG3</div><div class="t m0 x4c h10 yc1 ff2 fs5 fc0 sc0 ls77 ws0">SS2</div><div class="t m0 x4d h10 yc2 ff2 fs5 fc0 sc0 ls59 ws0">/CN1<span class="_ _4"></span>1/RG<span class="_ _6"></span>9</div><div class="t m0 x4e h10 yc3 ff2 fs5 fc0 sc0 ls62 ws0">AN5/IC8/CN7/RB5</div><div class="t m0 x4e h10 yc4 ff2 fs5 fc0 sc0 ls62 ws0">AN4/IC7/CN6/RB4</div><div class="t m0 x2f h10 yc5 ff2 fs5 fc0 sc0 ls71 ws0">IC3/INT3/RD10</div><div class="t m2 x47 h10 yaa ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m2 x46 h10 yaa ff2 fs5 fc0 sc0 ls33 ws0">RF0</div><div class="t m2 x4b h10 yaa ff2 fs5 fc0 sc0 ls6c ws0">OC4/RD3</div><div class="t m2 x48 h10 yaa ff2 fs5 fc0 sc0 ls69 ws0">OC7/CN15/RD6</div><div class="t m2 x49 h10 yaa ff2 fs5 fc0 sc0 ls57 ws0">OC6/IC6/CN14/RD5</div><div class="t m2 x4a h10 yaa ff2 fs5 fc0 sc0 ls57 ws0">OC5/IC5/CN13/RD4</div><div class="t m0 x16 hf yc6 ff3 fs9 fc0 sc0 ls78 ws0">PIC24HJ<span class="_ _6"></span>64GP206<span class="_ _6"></span>A</div><div class="t m0 x4f hb yc7 ff3 fs0 fc0 sc0 ls53 ws0">(2)</div><div class="t m0 x50 hf yc8 ff3 fs9 fc0 sc0 ls79 ws0">PIC24H<span class="_ _6"></span>J128GP2<span class="_ _6"></span>06A</div><div class="t m0 x50 hf yc9 ff3 fs9 fc0 sc0 ls79 ws0">PIC24H<span class="_ _6"></span>J256GP2<span class="_ _6"></span>06A</div><div class="t m0 x51 h8 yca ff3 fs5 fc0 sc0 ls33 ws0">Note<span class="_ _18"> </span>1:<span class="_ _2e"> </span><span class="ff2 ls7a ws47">The me<span class="_ _6"></span>tal plane a<span class="_ _6"></span>t the b<span class="_ _6"></span>ottom of th<span class="_ _6"></span>e device<span class="_ _6"></span> is not co<span class="_ _6"></span>nnecte<span class="_ _6"></span>d to any pi<span class="_ _6"></span>ns and sh<span class="_ _6"></span>ould be<span class="_ _6"></span> conne<span class="_ _6"></span>cted to <span class="_ _6"></span>V<span class="fsa ls58 ws0">SS</span><span class="ls7b ws48"> extern<span class="_ _6"></span>ally<span class="_ _4"></span>.</span></span></div><div class="t m0 x52 h8 ycb ff3 fs5 fc0 sc0 ls2e ws0">2:<span class="_ _2e"> </span><span class="ff2 ls7c ws49">The PIC<span class="_ _4"></span>24HJ64G<span class="_ _1"></span>P206<span class="_ _1"></span>A dev<span class="_ _1"></span>ice<span class="_ _1"></span> does n<span class="_ _4"></span>ot have th<span class="_ _4"></span>e SCL2 and S<span class="_ _1"></span>DA2<span class="_ _1"></span> pins<span class="_ _1"></span>.</span></div><div class="t m0 x52 h8 ycc ff3 fs5 fc0 sc0 ls2e ws0">3:<span class="_ _2e"> </span><span class="ff2 ls75 ws4a">Refer to <span class="_ _6"></span></span><span class="fc1 ls7d ws4b">Section<span class="_ _2f"> </span>2.3 “<span class="_ _6"></span>CPU Lo<span class="_ _6"></span>gic Filte<span class="_ _6"></span>r Capacitor<span class="_ _6"></span> Connect<span class="_ _6"></span>ion (V</span></div><div class="t m0 x53 h8 ycd ff3 fsa fc1 sc0 ls5b ws0">CAP<span class="fs5 ls7e">)”<span class="ff2 fc0 ls7f ws4c"> for<span class="_ _6"></span> prope<span class="_ _6"></span>r connecti<span class="_ _6"></span>on to thi<span class="_ _6"></span>s pin.</span></span></div><div class="t m0 x54 h5 yce ff2 fs3 fc0 sc0 lsb wsa">= Pins are up t<span class="_ _4"></span>o 5V toleran<span class="_ _1"></span>t </div><div class="t m3 x55 h14 ycf ff2 fsb fc0 sc0 ls80 ws0">64<span class="_ _30"> </span><span class="ls81">63<span class="_ _31"> </span>62<span class="_ _31"> </span></span>61<span class="_ _30"> </span><span class="ls81">60<span class="_ _31"> </span>59<span class="_ _31"> </span></span>58<span class="_ _30"> </span><span class="ls81">57<span class="_ _31"> </span>56<span class="_ _30"> </span></span>55</div><div class="t m3 x56 h14 yd0 ff2 fsb fc0 sc0 ls81 ws0">22<span class="_ _31"> </span>23<span class="_ _31"> </span><span class="ls80">24<span class="_ _30"> </span></span>25<span class="_ _31"> </span>26<span class="_ _31"> </span><span class="ls80">27<span class="_ _30"> </span></span>28<span class="_ _31"> </span>29<span class="_ _30"> </span><span class="ls80">30<span class="_ _31"> </span></span>31</div><div class="t m3 x57 h14 yd1 ff2 fsb fc0 sc0 ls0 ws0">3</div><div class="t m3 x58 h14 yd2 ff2 fsb fc0 sc0 ls81 ws0">40</div><div class="t m3 x58 h14 yd3 ff2 fsb fc0 sc0 ls81 ws0">39</div><div class="t m3 x58 h14 yd4 ff2 fsb fc0 sc0 ls81 ws0">38</div><div class="t m3 x58 h14 yd5 ff2 fsb fc0 sc0 ls81 ws0">37</div><div class="t m3 x58 h14 yd6 ff2 fsb fc0 sc0 ls81 ws0">36</div><div class="t m3 x58 h14 yd7 ff2 fsb fc0 sc0 ls81 ws0">35</div><div class="t m3 x58 h14 yd8 ff2 fsb fc0 sc0 ls81 ws0">34</div><div class="t m3 x58 h14 yd9 ff2 fsb fc0 sc0 ls81 ws0">33</div><div class="t m3 x57 h14 yda ff2 fsb fc0 sc0 ls0 ws0">4</div><div class="t m3 x57 h14 ydb ff2 fsb fc0 sc0 ls0 ws0">5</div><div class="t m3 x57 h14 ydc ff2 fsb fc0 sc0 ls0 ws0">7</div><div class="t m3 x57 h14 ydd ff2 fsb fc0 sc0 ls0 ws0">8</div><div class="t m3 x57 h14 yde ff2 fsb fc0 sc0 ls0 ws0">9</div><div class="t m3 x59 h14 ydf ff2 fsb fc0 sc0 ls81 ws0">10</div><div class="t m3 x59 h14 ye0 ff2 fsb fc0 sc0 ls82 ws0">11</div><div class="t m3 x57 h14 ye1 ff2 fsb fc0 sc0 ls0 ws0">1</div><div class="t m3 x57 h14 ye2 ff2 fsb fc0 sc0 ls0 ws0">2</div><div class="t m3 x58 h14 ye3 ff2 fsb fc0 sc0 ls81 ws0">42</div><div class="t m3 x58 h14 ye4 ff2 fsb fc0 sc0 ls81 ws0">41</div><div class="t m3 x57 h14 ye5 ff2 fsb fc0 sc0 ls0 ws0">6</div><div class="t m3 x5a h14 ye6 ff2 fsb fc0 sc0 ls81 ws0">32</div><div class="t m3 x58 h14 y8d ff2 fsb fc0 sc0 ls81 ws0">43</div><div class="t m3 x5b h14 ye7 ff2 fsb fc0 sc0 ls81 ws0">54</div><div class="t m3 x59 h14 ye8 ff2 fsb fc0 sc0 ls80 ws0">14</div><div class="t m3 x59 h14 ye9 ff2 fsb fc0 sc0 ls80 ws0">15</div><div class="t m3 x59 h14 yea ff2 fsb fc0 sc0 ls80 ws0">16</div><div class="t m3 x59 h14 yeb ff2 fsb fc0 sc0 ls80 ws0">12</div><div class="t m3 x59 h14 yec ff2 fsb fc0 sc0 ls80 ws0">13</div><div class="t m3 x55 h14 yed ff2 fsb fc0 sc0 ls81 ws0">17</div><div class="t m3 x5c h14 yd0 ff2 fsb fc0 sc0 ls80 ws0">18<span class="_ _30"> </span><span class="ls81">19<span class="_ _31"> </span>20<span class="_ _31"> </span></span>21</div><div class="t m3 x58 h14 yee ff2 fsb fc0 sc0 ls81 ws0">45</div><div class="t m3 x58 h14 yef ff2 fsb fc0 sc0 ls81 ws0">44</div><div class="t m3 x58 h14 yf0 ff2 fsb fc0 sc0 ls81 ws0">47</div><div class="t m3 x58 h14 yf1 ff2 fsb fc0 sc0 ls81 ws0">46</div><div class="t m3 x58 h14 yf2 ff2 fsb fc0 sc0 ls81 ws0">48</div><div class="t m3 x5d h14 yf3 ff2 fsb fc0 sc0 ls80 ws0">53</div><div class="t m3 x5e h14 ycf ff2 fsb fc0 sc0 ls81 ws0">52<span class="_ _31"> </span><span class="ls80">51<span class="_ _30"> </span></span>50<span class="_ _31"> </span>49</div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m4"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62512b1674bc5c010595a7a0/bg4.jpg"><div class="t m1 x14 h3 y4a ff3 fs1 fc0 sc0 ls36 ws0">PIC24HJXXXGPX06A/X08A/X10A</div><div class="t m1 x14 h2 y4b ff2 fs0 fc0 sc0 ls37 ws2b">DS70592D-page 4<span class="_ _0"> </span><span class="ff1 ls0 ws0"></span><span class="ls38 ws2c"> 2009-2012 Microchip Technology Inc.</span></div><div class="t m1 x14 h4 y84 ff3 fs2 fc0 sc0 ls15 ws11">Pin Diagrams <span class="_ _1"></span>(Continued)</div><div class="c x14 yf4 w2 h15"><div class="t m1 x2d hf yf5 ff3 fs9 fc0 sc0 ls52 ws46">64-Pin QFN</div><div class="t m1 x2e hb yf6 ff3 fs0 fc0 sc0 ls53 ws0">(1)</div><div class="t m1 x2f h10 yf7 ff2 fs5 fc0 sc0 ls83 ws0">PGEC2/SOS<span class="_ _1"></span>CO/T1CK/CN<span class="_ _4"></span>0<span class="_ _6"></span>/RC14</div><div class="t m1 x2f h10 yf8 ff2 fs5 fc0 sc0 ls84 ws0">PGED2/SOS<span class="_ _4"></span>CI/T4CK/CN1/R<span class="_ _4"></span>C1<span class="_ _6"></span>3</div><div class="t m1 x2f h10 yf9 ff2 fs5 fc0 sc0 ls33 ws0">OC1/RD0</div><div class="t m1 x2f h10 yfa ff2 fs5 fc0 sc0 ls85 ws0">IC4/INT4/<span class="_ _6"></span>RD1<span class="_ _4"></span>1</div><div class="t m1 x2f h10 yfb ff2 fs5 fc0 sc0 ls86 ws0">IC2/U1CTS</div><div class="t m1 x30 h10 yfc ff2 fs5 fc0 sc0 ls87 ws0">/INT2/RD9</div><div class="t m1 x2f h10 yfd ff2 fs5 fc0 sc0 ls85 ws0">IC1/INT1/<span class="_ _6"></span>RD8</div><div class="t m1 x2f h10 yfe ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m1 x31 h11 yff ff2 fsa fc0 sc0 ls58 ws0">SS</div><div class="t m1 x2f h10 y100 ff2 fs5 fc0 sc0 ls88 ws0">OSC2<span class="_ _4"></span>/CLKO/<span class="_ _4"></span>RC15</div><div class="t m1 x2f h10 y101 ff2 fs5 fc0 sc0 ls88 ws0">OSC1<span class="_ _4"></span>/CLKIN<span class="_ _1"></span>/RC<span class="_ _4"></span>12</div><div class="t m1 x2f h10 y102 ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m1 x31 h11 y103 ff2 fsa fc0 sc0 ls6a ws0">DD</div><div class="t m1 x2f h10 y104 ff2 fs5 fc0 sc0 ls60 ws0">SCL1/RG2</div><div class="t m1 x2f h10 y105 ff2 fs5 fc0 sc0 ls33 ws0">U1RTS</div><div class="t m1 x32 h10 y106 ff2 fs5 fc0 sc0 ls89 ws0">/SCK1/INT0<span class="_ _6"></span>/RF6</div><div class="t m1 x2f h10 y107 ff2 fs5 fc0 sc0 ls5e ws0">U1RX/SDI1/RF2</div><div class="t m1 x2f h10 y108 ff2 fs5 fc0 sc0 ls5e ws0">U1TX/SDO1/RF3</div><div class="t m1 x33 h10 y109 ff2 fs5 fc0 sc0 ls0 ws0">RG15</div><div class="t m1 x34 h10 y10a ff2 fs5 fc0 sc0 ls69 ws0">AN16/T2CK/T7CK/RC1</div><div class="t m1 x34 h10 y10b ff2 fs5 fc0 sc0 ls69 ws0">AN17/T3CK/T6CK/RC2</div><div class="t m1 x35 h10 y10c ff2 fs5 fc0 sc0 ls0 ws0">SCK2/CN8/RG6</div><div class="t m1 x36 h10 y10d ff2 fs5 fc0 sc0 ls0 ws0">SDI2/CN9/RG7</div><div class="t m1 x37 h10 y10e ff2 fs5 fc0 sc0 ls87 ws0">SDO2/CN10/RG8</div><div class="t m1 x38 h10 y10f ff2 fs5 fc0 sc0 ls61 ws0">MCLR</div><div class="t m1 x39 h10 y110 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls58">SS</span></div><div class="t m1 x39 h10 y111 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls5b">DD</span></div><div class="t m1 x3a h10 y112 ff2 fs5 fc0 sc0 ls62 ws0">AN3/CN5/RB3</div><div class="t m1 x3b h10 y113 ff2 fs5 fc0 sc0 ls8a ws0">AN2/SS1</div><div class="t m1 x3c h10 y114 ff2 fs5 fc0 sc0 ls5e ws0">/CN4/RB2</div><div class="t m1 x3d h10 y115 ff2 fs5 fc0 sc0 ls8b ws0">PGEC3/AN<span class="_ _4"></span>1<span class="_ _6"></span>/V</div><div class="t m1 x11 h10 y116 ff2 fsa fc0 sc0 ls5b ws0">REF<span class="fs5 ls8c">-/CN3/RB1</span></div><div class="t m1 x5f h10 y117 ff2 fs5 fc0 sc0 ls65 ws0">PGED3/AN0<span class="_ _4"></span>/V</div><div class="t m1 x3a h10 y118 ff2 fsa fc0 sc0 ls66 ws0">REF<span class="fs5 ls68">+/CN2/RB0</span></div><div class="t m2 x3f h10 y119 ff2 fs5 fc0 sc0 ls69 ws0">OC8/CN16/RD7</div><div class="t m2 x40 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">RG13</div><div class="t m2 x41 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">RG12</div><div class="t m2 x16 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">RG14</div><div class="t m2 x19 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m2 x19 h11 y11a ff2 fsa fc0 sc0 ls6a ws0">CAP</div><div class="t m2 x1a h12 y11b ff3 fsa fc0 sc0 ls6b ws0">(2)</div><div class="t m2 x42 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">RG1</div><div class="t m2 x2 h10 y119 ff2 fs5 fc0 sc0 ls33 ws0">RF1</div><div class="t m2 x43 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">RG0</div><div class="t m2 x44 h10 y119 ff2 fs5 fc0 sc0 ls6c ws0">OC2/RD1</div><div class="t m2 x45 h10 y119 ff2 fs5 fc0 sc0 ls6c ws0">OC3/RD2</div><div class="t m2 x40 h10 y11c ff2 fs5 fc0 sc0 ls63 ws0">PGEC1/AN6/OCF<span class="_ _4"></span>A/RB6</div><div class="t m2 x41 h10 y11d ff2 fs5 fc0 sc0 ls6e ws0">PGED1/AN7/RB7</div><div class="t m2 x16 h10 y11e ff2 fs5 fc0 sc0 ls6f ws0">AV</div><div class="t m2 x16 h11 y11f ff2 fsa fc0 sc0 ls6a ws0">DD</div><div class="t m2 x43 h10 y120 ff2 fs5 fc0 sc0 ls6f ws0">AV<span class="_ _32"></span><span class="fsa ls58">SS</span></div><div class="t m2 x42 h10 y121 ff2 fs5 fc0 sc0 ls33 ws0">U2CTS<span class="ls71">/AN8/RB8</span></div><div class="t m2 x2 h10 y122 ff2 fs5 fc0 sc0 ls60 ws0">AN9/RB9</div><div class="t m2 x46 h10 y123 ff2 fs5 fc0 sc0 ls6d ws0">TMS/AN10/RB10</div><div class="t m2 x47 h10 y124 ff2 fs5 fc0 sc0 ls31 ws0">TDO/AN11<span class="_ _1"></span>/RB1<span class="_ _4"></span>1</div><div class="t m2 x19 h10 y125 ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m2 x19 h11 y126 ff2 fsa fc0 sc0 ls58 ws0">SS</div><div class="t m2 x3f h10 y127 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m2 x48 h10 y128 ff2 fs5 fc0 sc0 ls72 ws0">TCK/AN12/RB12</div><div class="t m2 x49 h10 y129 ff2 fs5 fc0 sc0 ls73 ws0">TDI/AN13/RB13</div><div class="t m2 x4a h10 y12a ff2 fs5 fc0 sc0 ls33 ws0">U2RTS</div><div class="t m2 x4a h10 y12b ff2 fs5 fc0 sc0 ls64 ws0">/AN14/RB14</div><div class="t m2 x4b h10 y12c ff2 fs5 fc0 sc0 ls69 ws0">AN15/OCFB/CN12/RB15</div><div class="t m2 x44 h10 y12d ff2 fs5 fc0 sc0 ls33 ws0">U2TX/SCL2/CN18/RF5</div><div class="t m2 x45 h13 y12e ff2 fs5 fc0 sc0 ls33 ws0">U2RX<span class="ff6 ls0">/</span><span class="ls63">SDA2/CN17/RF4</span></div><div class="t m0 x2f h10 y12f ff2 fs5 fc0 sc0 ls63 ws0">SDA1/RG3</div><div class="t m0 x4c h10 y130 ff2 fs5 fc0 sc0 ls77 ws0">SS2</div><div class="t m0 x4d h10 y131 ff2 fs5 fc0 sc0 ls87 ws0">/CN1<span class="_ _4"></span>1/RG9</div><div class="t m0 x4e h10 y132 ff2 fs5 fc0 sc0 ls56 ws0">AN5/IC8/CN7/RB<span class="_ _6"></span>5</div><div class="t m0 x4e h10 y133 ff2 fs5 fc0 sc0 ls56 ws0">AN4/IC7/CN6/RB<span class="_ _6"></span>4</div><div class="t m0 x60 h10 y134 ff2 fs5 fc0 sc0 ls75 ws0">IC3/IN<span class="_ _6"></span>T3/RD10</div><div class="t m2 x47 h10 y119 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m2 x46 h10 y119 ff2 fs5 fc0 sc0 ls33 ws0">RF0</div><div class="t m2 x4b h10 y119 ff2 fs5 fc0 sc0 ls6c ws0">OC4/RD3</div><div class="t m2 x48 h10 y119 ff2 fs5 fc0 sc0 ls69 ws0">OC7/CN15/RD6</div><div class="t m2 x49 h10 y119 ff2 fs5 fc0 sc0 ls57 ws0">OC6/IC6/CN14/RD5</div><div class="t m2 x4a h10 y119 ff2 fs5 fc0 sc0 ls57 ws0">OC5/IC5/CN13/RD4</div><div class="t m0 x61 hf y135 ff3 fs9 fc0 sc0 ls8d ws0">PIC24HJ<span class="_ _6"></span>128GP30<span class="_ _6"></span>6A</div><div class="t m0 x62 h5 y136 ff2 fs3 fc0 sc0 ls8e ws4d">= Pins<span class="_ _6"></span> are<span class="_ _6"></span> up t<span class="_ _6"></span>o 5V to<span class="_ _6"></span>ler<span class="_ _6"></span>ant<span class="_ _6"></span> </div><div class="t m0 x63 h8 y137 ff3 fs5 fc0 sc0 ls33 ws0">Note<span class="_ _18"> </span>1:<span class="_ _2e"> </span><span class="ff2 ls32 ws4e">The me<span class="_ _6"></span>tal plane a<span class="_ _6"></span>t the b<span class="_ _6"></span>ottom of th<span class="_ _6"></span>e device<span class="_ _6"></span> is not co<span class="_ _6"></span>nnecte<span class="_ _6"></span>d to any pin<span class="_ _6"></span>s and sh<span class="_ _6"></span>ould b<span class="_ _6"></span>e conne<span class="_ _6"></span>cted to V<span class="fsa ls58 ws0">SS</span><span class="ls7b ws48"> ext<span class="_ _6"></span>ernally.</span></span></div><div class="t m0 x64 h8 y138 ff3 fs5 fc0 sc0 ls2e ws0">2:<span class="_ _2e"> </span><span class="ff2 ls71 ws4f">Refer to<span class="_ _6"></span> </span><span class="fc1 ls8f ws50">Section<span class="_"> </span>2<span class="_ _6"></span>.3 “CPU<span class="_ _6"></span> Logi<span class="_ _6"></span>c Filter<span class="_ _6"></span> Capacitor C<span class="_ _6"></span>onnec<span class="_ _6"></span>tion (<span class="_ _6"></span>V</span></div><div class="t m0 x65 h8 y139 ff3 fsa fc1 sc0 ls6a ws0">CAP<span class="fs5 ls7e">)”<span class="_ _1"></span><span class="ff2 fc0 ls90 ws51"> for prope<span class="_ _6"></span>r conn<span class="_ _6"></span>ection to th<span class="_ _6"></span>is pin.</span></span></div><div class="t m3 x55 h14 y13a ff2 fsb fc0 sc0 ls80 ws0">64<span class="_ _30"> </span><span class="ls81">63<span class="_ _31"> </span>62<span class="_ _31"> </span></span>61<span class="_ _30"> </span><span class="ls81">60<span class="_ _31"> </span>59<span class="_ _30"> </span></span>58<span class="_ _31"> </span><span class="ls81">57<span class="_ _31"> </span>56<span class="_ _30"> </span></span>55</div><div class="t m3 x56 h14 y13b ff2 fsb fc0 sc0 ls81 ws0">22<span class="_ _31"> </span>23<span class="_ _31"> </span><span class="ls80">24<span class="_ _30"> </span></span>25<span class="_ _31"> </span>26<span class="_ _31"> </span><span class="ls80">27<span class="_ _30"> </span></span>28<span class="_ _31"> </span>29<span class="_ _30"> </span><span class="ls80">30<span class="_ _31"> </span></span>31</div><div class="t m3 x57 h14 y13c ff2 fsb fc0 sc0 ls0 ws0">3</div><div class="t m3 x58 h14 y13d ff2 fsb fc0 sc0 ls81 ws0">40</div><div class="t m3 x58 h14 y13e ff2 fsb fc0 sc0 ls81 ws0">39</div><div class="t m3 x58 h14 y13f ff2 fsb fc0 sc0 ls81 ws0">38</div><div class="t m3 x58 h14 y140 ff2 fsb fc0 sc0 ls81 ws0">37</div><div class="t m3 x58 h14 y141 ff2 fsb fc0 sc0 ls81 ws0">36</div><div class="t m3 x58 h14 y142 ff2 fsb fc0 sc0 ls81 ws0">35</div><div class="t m3 x58 h14 y143 ff2 fsb fc0 sc0 ls81 ws0">34</div><div class="t m3 x58 h14 y144 ff2 fsb fc0 sc0 ls81 ws0">33</div><div class="t m3 x57 h14 y145 ff2 fsb fc0 sc0 ls0 ws0">4</div><div class="t m3 x57 h14 y146 ff2 fsb fc0 sc0 ls0 ws0">5</div><div class="t m3 x57 h14 y147 ff2 fsb fc0 sc0 ls0 ws0">7</div><div class="t m3 x57 h14 y148 ff2 fsb fc0 sc0 ls0 ws0">8</div><div class="t m3 x57 h14 y149 ff2 fsb fc0 sc0 ls0 ws0">9</div><div class="t m3 x59 h14 y14a ff2 fsb fc0 sc0 ls81 ws0">10</div><div class="t m3 x59 h14 y14b ff2 fsb fc0 sc0 ls82 ws0">11</div><div class="t m3 x57 h14 y14c ff2 fsb fc0 sc0 ls0 ws0">1</div><div class="t m3 x57 h14 y14d ff2 fsb fc0 sc0 ls0 ws0">2</div><div class="t m3 x58 h14 y14e ff2 fsb fc0 sc0 ls81 ws0">42</div><div class="t m3 x58 h14 y14f ff2 fsb fc0 sc0 ls81 ws0">41</div><div class="t m3 x57 h14 y150 ff2 fsb fc0 sc0 ls0 ws0">6</div><div class="t m3 x5a h14 y151 ff2 fsb fc0 sc0 ls81 ws0">32</div><div class="t m3 x58 h14 y152 ff2 fsb fc0 sc0 ls81 ws0">43</div><div class="t m3 x5b h14 y153 ff2 fsb fc0 sc0 ls81 ws0">54</div><div class="t m3 x59 h14 y154 ff2 fsb fc0 sc0 ls80 ws0">14</div><div class="t m3 x59 h14 y155 ff2 fsb fc0 sc0 ls80 ws0">15</div><div class="t m3 x59 h14 y156 ff2 fsb fc0 sc0 ls80 ws0">16</div><div class="t m3 x59 h14 y157 ff2 fsb fc0 sc0 ls80 ws0">12</div><div class="t m3 x59 h14 y158 ff2 fsb fc0 sc0 ls80 ws0">13</div><div class="t m3 x55 h14 y159 ff2 fsb fc0 sc0 ls81 ws0">17</div><div class="t m3 x5c h14 y13b ff2 fsb fc0 sc0 ls80 ws0">18<span class="_ _30"> </span><span class="ls81">19<span class="_ _31"> </span>20<span class="_ _31"> </span></span>21</div><div class="t m3 x58 h14 y15a ff2 fsb fc0 sc0 ls81 ws0">45</div><div class="t m3 x58 h14 y15b ff2 fsb fc0 sc0 ls81 ws0">44</div><div class="t m3 x58 h14 y15c ff2 fsb fc0 sc0 ls81 ws0">47</div><div class="t m3 x58 h14 y15d ff2 fsb fc0 sc0 ls81 ws0">46</div><div class="t m3 x58 h14 y15e ff2 fsb fc0 sc0 ls81 ws0">48</div><div class="t m3 x5d h14 y15f ff2 fsb fc0 sc0 ls80 ws0">53</div><div class="t m3 x5e h14 y13a ff2 fsb fc0 sc0 ls81 ws0">52<span class="_ _31"> </span><span class="ls80">51<span class="_ _30"> </span></span>50<span class="_ _31"> </span>49</div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m4"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62512b1674bc5c010595a7a0/bg5.jpg"><div class="t m0 x1 h2 y4b ff1 fs0 fc0 sc0 ls0 ws0"><span class="ff2 ls1 ws1"> 2009-2012 Microchip Technology Inc.<span class="_ _0"> </span><span class="ls2 ws2">DS70592D-page 5</span></span></div><div class="t m0 x2 h3 y4a ff3 fs1 fc0 sc0 ls3 ws0">PIC24HJXXXGPX06A/X08A/X10A</div><div class="t m0 x1 h4 y84 ff3 fs2 fc0 sc0 ls15 ws11">Pin Diagrams <span class="_ _1"></span>(Continued)</div><div class="c x1 y160 w2 h16"><div class="t m0 x2d hf y161 ff3 fs9 fc0 sc0 ls52 ws46">64-Pin QFN</div><div class="t m0 x2e hb y162 ff3 fs0 fc0 sc0 ls53 ws0">(1)</div><div class="t m0 x2f h10 y163 ff2 fs5 fc0 sc0 ls91 ws0">PGE<span class="_ _6"></span>C2/<span class="_ _6"></span>SOSC<span class="_ _6"></span>O/T<span class="_ _6"></span>1CK/<span class="_ _6"></span>CN0<span class="_ _6"></span>/RC<span class="_ _6"></span>14</div><div class="t m0 x2f h10 y164 ff2 fs5 fc0 sc0 ls91 ws0">PGE<span class="_ _6"></span>D2/<span class="_ _6"></span>SOSC<span class="_ _6"></span>I/T<span class="_ _6"></span>4CK/<span class="_ _6"></span>CN1<span class="_ _6"></span>/RC<span class="_ _6"></span>13</div><div class="t m0 x2f h10 y165 ff2 fs5 fc0 sc0 ls6c ws0">OC1/RD0</div><div class="t m0 x2f h10 y166 ff2 fs5 fc0 sc0 ls92 ws0">IC4/INT4/RD1<span class="_ _4"></span>1</div><div class="t m0 x2f h10 y167 ff2 fs5 fc0 sc0 ls93 ws0">IC2/U1CTS</div><div class="t m0 x66 h10 y168 ff2 fs5 fc0 sc0 ls5d ws0">/INT2/RD9</div><div class="t m0 x2f h10 y169 ff2 fs5 fc0 sc0 ls92 ws0">IC1/INT1/RD8</div><div class="t m0 x2f h10 y16a ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m0 x31 h11 y91 ff2 fsa fc0 sc0 ls58 ws0">SS</div><div class="t m0 x2f h10 y16b ff2 fs5 fc0 sc0 ls31 ws0">OSC2/CLKO/<span class="_ _6"></span>RC15</div><div class="t m0 x2f h10 y16c ff2 fs5 fc0 sc0 ls5a ws0">OSC1/CLKIN/<span class="_ _6"></span>RC12</div><div class="t m0 x2f h10 y16d ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m0 x31 h11 y95 ff2 fsa fc0 sc0 ls6a ws0">DD</div><div class="t m0 x2f h10 yc0 ff2 fs5 fc0 sc0 ls94 ws0">SCL1/RG2</div><div class="t m0 x2f h10 y16e ff2 fs5 fc0 sc0 ls33 ws0">U1RTS</div><div class="t m0 x32 h10 y16f ff2 fs5 fc0 sc0 ls95 ws0">/SCK1/INT0<span class="_ _6"></span>/RF6</div><div class="t m0 x2f h10 y170 ff2 fs5 fc0 sc0 ls33 ws0">U1RX/SDI1/RF2</div><div class="t m0 x2f h10 y171 ff2 fs5 fc0 sc0 ls96 ws0">U1TX/SDO1/RF3</div><div class="t m0 x33 h10 y172 ff2 fs5 fc0 sc0 ls33 ws0">RG15</div><div class="t m0 x34 h10 y173 ff2 fs5 fc0 sc0 ls69 ws0">AN16/T2CK/T7CK/RC1</div><div class="t m0 x34 h10 y174 ff2 fs5 fc0 sc0 ls69 ws0">AN17/T3CK/T6CK/RC2</div><div class="t m0 x67 h10 y175 ff2 fs5 fc0 sc0 ls0 ws0">SCK2/CN8/RG6</div><div class="t m0 x1 h10 y176 ff2 fs5 fc0 sc0 ls59 ws0">SDI2/CN9/RG7</div><div class="t m0 x68 h10 y177 ff2 fs5 fc0 sc0 ls97 ws0">SDO2/CN10/RG8</div><div class="t m0 x69 h10 y178 ff2 fs5 fc0 sc0 ls7e ws0">MCLR</div><div class="t m0 x6a h10 ya2 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls98">SS</span></div><div class="t m0 x39 h10 y179 ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m0 x3a h10 ya5 ff2 fs5 fc0 sc0 ls7f ws0">AN3/C<span class="_ _6"></span>N5/RB3</div><div class="t m0 x2e h10 ya6 ff2 fs5 fc0 sc0 ls8a ws0">AN2/SS1</div><div class="t m0 x3c h10 ya7 ff2 fs5 fc0 sc0 ls71 ws0">/CN4/RB2</div><div class="t m0 x6b h10 ya8 ff2 fs5 fc0 sc0 ls99 ws0">PGEC3/AN1/<span class="_ _1"></span>V</div><div class="t m0 x6c h10 ya9 ff2 fsa fc0 sc0 ls66 ws0">REF<span class="fs5 ls67">-/CN3/RB1</span></div><div class="t m0 x5f h10 y17a ff2 fs5 fc0 sc0 ls99 ws0">PGED3/AN0/<span class="_ _1"></span>V</div><div class="t m0 x3a h10 y17b ff2 fsa fc0 sc0 ls66 ws0">REF<span class="fs5 ls9a">+/CN2/RB0</span></div><div class="t m2 x3f h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">OC8/CN16/RD7</div><div class="t m2 x6d h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">RG13</div><div class="t m2 x41 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">RG12</div><div class="t m2 x16 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">RG14</div><div class="t m2 x19 h10 y17c ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m2 x19 h11 y17d ff2 fsa fc0 sc0 ls6a ws0">CAP</div><div class="t m2 x6e h12 y17e ff3 fsa fc0 sc0 ls6b ws0">(2)</div><div class="t m2 x6f h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">RG1</div><div class="t m2 x70 h10 y17c ff2 fs5 fc0 sc0 ls97 ws0">C1TX/RF1</div><div class="t m2 x43 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">RG0</div><div class="t m2 x44 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">OC2/RD1</div><div class="t m2 x71 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">OC3/RD2</div><div class="t m2 x6d h10 y17f ff2 fs5 fc0 sc0 ls6d ws0">PGEC1/AN6/OCF<span class="_ _4"></span>A/RB6</div><div class="t m2 x13 h10 y180 ff2 fs5 fc0 sc0 ls6e ws0">PGED1/AN7/RB7</div><div class="t m2 x16 h10 y181 ff2 fs5 fc0 sc0 ls70 ws0">AV</div><div class="t m2 x16 h11 y182 ff2 fsa fc0 sc0 ls6a ws0">DD</div><div class="t m2 x72 h10 y183 ff2 fs5 fc0 sc0 ls70 ws0">AV<span class="_ _6"></span><span class="fsa ls98">SS</span></div><div class="t m2 x6f h10 y184 ff2 fs5 fc0 sc0 ls33 ws0">U2CTS<span class="ls71">/AN8/RB8</span></div><div class="t m2 x70 h10 y185 ff2 fs5 fc0 sc0 ls60 ws0">AN9/RB9</div><div class="t m2 x46 h10 y186 ff2 fs5 fc0 sc0 ls9b ws0">TMS/AN10/RB1<span class="_ _4"></span>0</div><div class="t m2 x47 h10 y187 ff2 fs5 fc0 sc0 ls63 ws0">TDO/AN1<span class="_ _4"></span>1/RB1<span class="_ _3"></span>1</div><div class="t m2 x19 h10 y188 ff2 fs5 fc0 sc0 ls0 ws0">V</div><div class="t m2 x19 h11 y189 ff2 fsa fc0 sc0 ls98 ws0">SS</div><div class="t m2 x3f h10 y18a ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m2 x48 h10 y18b ff2 fs5 fc0 sc0 ls72 ws0">TCK/AN12/RB12</div><div class="t m2 x49 h10 y18c ff2 fs5 fc0 sc0 ls73 ws0">TDI/AN13/RB13</div><div class="t m2 x73 h10 y18d ff2 fs5 fc0 sc0 ls33 ws0">U2RTS</div><div class="t m2 x73 h10 y18e ff2 fs5 fc0 sc0 ls64 ws0">/AN14/RB14</div><div class="t m2 x74 h10 y18f ff2 fs5 fc0 sc0 ls69 ws0">AN15/OCFB/CN12/RB15</div><div class="t m2 x44 h10 y190 ff2 fs5 fc0 sc0 ls5e ws0">U2TX/SCL2/CN18/RF5</div><div class="t m2 x71 h13 y191 ff2 fs5 fc0 sc0 ls33 ws0">U2RX<span class="ff6 ls0">/</span><span class="ls9c">SDA2/CN17/RF4</span></div><div class="t m0 x2f h10 y97 ff2 fs5 fc0 sc0 ls63 ws0">SDA1/RG3</div><div class="t m0 x36 h10 y192 ff2 fs5 fc0 sc0 ls77 ws0">SS2</div><div class="t m0 x75 h10 ya1 ff2 fs5 fc0 sc0 ls87 ws0">/CN1<span class="_ _4"></span>1/RG9</div><div class="t m0 x4e h10 y193 ff2 fs5 fc0 sc0 ls7f ws0">AN5/IC<span class="_ _6"></span>8/CN7/RB<span class="_ _6"></span>5</div><div class="t m0 x4e h10 y194 ff2 fs5 fc0 sc0 ls7f ws0">AN4/IC<span class="_ _6"></span>7/CN6/RB<span class="_ _6"></span>4</div><div class="t m0 x60 h10 y195 ff2 fs5 fc0 sc0 ls89 ws0">IC3/INT3/R<span class="_ _6"></span>D10</div><div class="t m2 x47 h10 y17c ff2 fs5 fc0 sc0 ls0 ws0">V<span class="fsa ls6a">DD</span></div><div class="t m2 x46 h10 y17c ff2 fs5 fc0 sc0 ls5e ws0">C1RX/RF0</div><div class="t m2 x74 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">OC4/RD3</div><div class="t m2 x48 h10 y17c ff2 fs5 fc0 sc0 ls33 ws0">OC7/CN15/RD6</div><div class="t m2 x76 h10 y17c ff2 fs5 fc0 sc0 ls34 ws0">OC6/IC6/CN14/RD5</div><div class="t m2 x73 h10 y17c ff2 fs5 fc0 sc0 ls34 ws0">OC5/IC5/CN13/RD4</div><div class="t m0 x17 hf y196 ff3 fs9 fc0 sc0 ls9d ws0">PIC24H<span class="_ _6"></span>J64GP50<span class="_ _6"></span>6A</div><div class="t m0 x77 hf y197 ff3 fs9 fc0 sc0 ls9d ws0">PIC24HJ<span class="_ _6"></span>128GP50<span class="_ _6"></span>6A</div><div class="t m0 x78 h5 y198 ff2 fs3 fc0 sc0 lsf wsd">= Pins a<span class="_ _4"></span>re up to 5V tolerant </div><div class="t m0 x63 h8 y199 ff3 fs5 fc0 sc0 ls33 ws0">Note<span class="_ _18"> </span>1:<span class="_ _2e"> </span><span class="ff2 ls32 ws4e">The me<span class="_ _6"></span>tal plane a<span class="_ _6"></span>t the b<span class="_ _6"></span>ottom of th<span class="_ _6"></span>e device<span class="_ _6"></span> is not co<span class="_ _6"></span>nnecte<span class="_ _6"></span>d to any pin<span class="_ _6"></span>s and sh<span class="_ _6"></span>ould b<span class="_ _6"></span>e conne<span class="_ _6"></span>cted to V<span class="fsa ls58 ws0">SS</span><span class="ls7b ws48"> ext<span class="_ _6"></span>ernally.</span></span></div><div class="t m0 x64 h8 y19a ff3 fs5 fc0 sc0 ls2e ws0">2:<span class="_ _2e"> </span><span class="ff2 ls71 ws4f">Refer to<span class="_ _6"></span> </span><span class="fc1 ls8f ws50">Section<span class="_"> </span>2<span class="_ _6"></span>.3 “CPU<span class="_ _6"></span> Logi<span class="_ _6"></span>c Filter<span class="_ _6"></span> Capacitor C<span class="_ _6"></span>onnec<span class="_ _6"></span>tion (<span class="_ _6"></span>V</span></div><div class="t m0 x65 h8 y19b ff3 fsa fc1 sc0 ls6a ws0">CAP<span class="fs5 ls7e">)”<span class="_ _1"></span><span class="ff2 fc0 ls90 ws51"> for prope<span class="_ _6"></span>r conn<span class="_ _6"></span>ection to th<span class="_ _6"></span>is pin.</span></span></div><div class="t m3 x79 h14 y19c ff2 fsb fc0 sc0 ls81 ws0">64<span class="_ _31"> </span><span class="ls80">63<span class="_ _30"> </span></span>62<span class="_ _31"> </span>61<span class="_ _31"> </span><span class="ls80">60<span class="_ _30"> </span></span>59<span class="_ _31"> </span>58<span class="_ _30"> </span><span class="ls80">57<span class="_ _31"> </span></span>56<span class="_ _31"> </span>55</div><div class="t m3 x7a h14 y19d ff2 fsb fc0 sc0 ls80 ws0">22<span class="_ _30"> </span><span class="ls81">23<span class="_ _31"> </span>24<span class="_ _31"> </span></span>25<span class="_ _30"> </span><span class="ls81">26<span class="_ _31"> </span>27<span class="_ _31"> </span></span>28<span class="_ _30"> </span><span class="ls81">29<span class="_ _31"> </span>30<span class="_ _30"> </span></span>31</div><div class="t m3 x7b h14 y19e ff2 fsb fc0 sc0 ls0 ws0">3</div><div class="t m3 x7c h14 y19f ff2 fsb fc0 sc0 ls80 ws0">40</div><div class="t m3 x7c h14 y1a0 ff2 fsb fc0 sc0 ls80 ws0">39</div><div class="t m3 x7c h14 y1a1 ff2 fsb fc0 sc0 ls80 ws0">38</div><div class="t m3 x7c h14 y1a2 ff2 fsb fc0 sc0 ls80 ws0">37</div><div class="t m3 x7c h14 y1a3 ff2 fsb fc0 sc0 ls80 ws0">36</div><div class="t m3 x7c h14 y1a4 ff2 fsb fc0 sc0 ls80 ws0">35</div><div class="t m3 x7c h14 y1a5 ff2 fsb fc0 sc0 ls80 ws0">34</div><div class="t m3 x7c h14 y1a6 ff2 fsb fc0 sc0 ls80 ws0">33</div><div class="t m3 x7b h14 y1a7 ff2 fsb fc0 sc0 ls0 ws0">4</div><div class="t m3 x7b h14 y1a8 ff2 fsb fc0 sc0 ls0 ws0">5</div><div class="t m3 x7b h14 y1a9 ff2 fsb fc0 sc0 ls0 ws0">7</div><div class="t m3 x7b h14 y1aa ff2 fsb fc0 sc0 ls0 ws0">8</div><div class="t m3 x7b h14 y1ab ff2 fsb fc0 sc0 ls0 ws0">9</div><div class="t m3 x7d h14 y1ac ff2 fsb fc0 sc0 ls80 ws0">10</div><div class="t m3 x7d h14 y1ad ff2 fsb fc0 sc0 ls82 ws0">11</div><div class="t m3 x7b h14 y1ae ff2 fsb fc0 sc0 ls0 ws0">1</div><div class="t m3 x7b h14 y1af ff2 fsb fc0 sc0 ls0 ws0">2</div><div class="t m3 x7c h14 y1b0 ff2 fsb fc0 sc0 ls80 ws0">42</div><div class="t m3 x7c h14 y1b1 ff2 fsb fc0 sc0 ls80 ws0">41</div><div class="t m3 x7b h14 y1b2 ff2 fsb fc0 sc0 ls0 ws0">6</div><div class="t m3 x7e h14 y1b3 ff2 fsb fc0 sc0 ls81 ws0">32</div><div class="t m3 x7c h14 y1b4 ff2 fsb fc0 sc0 ls80 ws0">43</div><div class="t m3 x7f h14 y1b5 ff2 fsb fc0 sc0 ls80 ws0">54</div><div class="t m3 x7d h14 y1b6 ff2 fsb fc0 sc0 ls81 ws0">14</div><div class="t m3 x7d h14 y1b7 ff2 fsb fc0 sc0 ls81 ws0">15</div><div class="t m3 x7d h14 y1b8 ff2 fsb fc0 sc0 ls81 ws0">16</div><div class="t m3 x7d h14 y1b9 ff2 fsb fc0 sc0 ls81 ws0">12</div><div class="t m3 x7d h14 y1ba ff2 fsb fc0 sc0 ls81 ws0">13</div><div class="t m3 x55 h14 y1bb ff2 fsb fc0 sc0 ls81 ws0">17</div><div class="t m3 x80 h14 y19d ff2 fsb fc0 sc0 ls81 ws0">18<span class="_ _30"> </span><span class="ls80">19<span class="_ _31"> </span></span>20<span class="_ _31"> </span>21</div><div class="t m3 x7c h14 y1bc ff2 fsb fc0 sc0 ls80 ws0">45</div><div class="t m3 x7c h14 y1bd ff2 fsb fc0 sc0 ls80 ws0">44</div><div class="t m3 x7c h14 y1be ff2 fsb fc0 sc0 ls80 ws0">47</div><div class="t m3 x7c h14 y1bf ff2 fsb fc0 sc0 ls80 ws0">46</div><div class="t m3 x7c h14 y1c0 ff2 fsb fc0 sc0 ls80 ws0">48</div><div class="t m3 x81 h14 y1c1 ff2 fsb fc0 sc0 ls81 ws0">53</div><div class="t m3 x4f h14 y19c ff2 fsb fc0 sc0 ls80 ws0">52<span class="_ _30"> </span><span class="ls81">51<span class="_ _31"> </span></span>50<span class="_ _30"> </span><span class="ls81">49</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m4"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>