posix_types_32.rar

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  • 2015-04-01 19:48
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This file is generally used by user-level software, so you need to be a little careful about namespace pollution etc. Also, we cannot assume GCC is being used.
posix_types_32.rar
  • posix_types_32.c
    702B
  • atl1c_main.c
    77.4KB
内容介绍
/* * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. * * Derived from Intel e1000 driver * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free * Software Foundation; either version 2 of the License, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program; if not, write to the Free Software Foundation, Inc., 59 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "atl1c.h" #define ATL1C_DRV_VERSION "1.0.1.1-NAPI" char atl1c_driver_name[] = "atl1c"; char atl1c_driver_version[] = ATL1C_DRV_VERSION; /* * atl1c_pci_tbl - PCI Device ID Table * * Wildcard entries (PCI_ANY_ID) should come last * Last entry must be all 0s * * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, * Class, Class Mask, private data (not used) } */ static const struct pci_device_id atl1c_pci_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)}, {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)}, {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)}, {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)}, {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)}, {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)}, /* required last entry */ { 0 } }; MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl); MODULE_AUTHOR("Jie Yang"); MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>"); MODULE_DESCRIPTION("Qualcomm Atheros 100/1000M Ethernet Network Driver"); MODULE_LICENSE("GPL"); MODULE_VERSION(ATL1C_DRV_VERSION); static int atl1c_stop_mac(struct atl1c_hw *hw); static void atl1c_disable_l0s_l1(struct atl1c_hw *hw); static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed); static void atl1c_start_mac(struct atl1c_adapter *adapter); static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, int *work_done, int work_to_do); static int atl1c_up(struct atl1c_adapter *adapter); static void atl1c_down(struct atl1c_adapter *adapter); static int atl1c_reset_mac(struct atl1c_hw *hw); static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter); static int atl1c_configure(struct atl1c_adapter *adapter); static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter); static const u16 atl1c_pay_load_size[] = { 128, 256, 512, 1024, 2048, 4096, }; static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; static void atl1c_pcie_patch(struct atl1c_hw *hw) { u32 mst_data, data; /* pclk sel could switch to 25M */ AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data); mst_data &= ~MASTER_CTRL_CLK_SEL_DIS; AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data); /* WoL/PCIE related settings */ if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { AT_READ_REG(hw, REG_PCIE_PHYMISC, &data); data |= PCIE_PHYMISC_FORCE_RCV_DET; AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data); } else { /* new dev set bit5 of MASTER */ if (!(mst_data & MASTER_CTRL_WAKEN_25M)) AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data | MASTER_CTRL_WAKEN_25M); } /* aspm/PCIE setting only for l2cb 1.0 */ if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) { AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data); data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW, L2CB1_PCIE_PHYMISC2_CDR_BW); data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH, L2CB1_PCIE_PHYMISC2_L0S_TH); AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data); /* extend L1 sync timer */ AT_READ_REG(hw, REG_LINK_CTRL, &data); data |= LINK_CTRL_EXT_SYNC; AT_WRITE_REG(hw, REG_LINK_CTRL, data); } /* l2cb 1.x & l1d 1.x */ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) { AT_READ_REG(hw, REG_PM_CTRL, &data); data |= PM_CTRL_L0S_BUFSRX_EN; AT_WRITE_REG(hw, REG_PM_CTRL, data); /* clear vendor msg */ AT_READ_REG(hw, REG_DMA_DBG, &data); AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG); } } /* FIXME: no need any more ? */ /* * atl1c_init_pcie - init PCIE module */ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag) { u32 data; u32 pci_cmd; struct pci_dev *pdev = hw->adapter->pdev; int pos; AT_READ_REG(hw, PCI_COMMAND, &pci_cmd); pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_IO); AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd); /* * Clear any PowerSaveing Settings */ pci_enable_wake(pdev, PCI_D3hot, 0); pci_enable_wake(pdev, PCI_D3cold, 0); /* wol sts read-clear */ AT_READ_REG(hw, REG_WOL_CTRL, &data); AT_WRITE_REG(hw, REG_WOL_CTRL, 0); /* * Mask some pcie error bits */ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); if (pos) { pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data); data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP); pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data); } /* clear error status */ pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_NFED | PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_URD); AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data); data &= ~LTSSM_ID_EN_WRO; AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data); atl1c_pcie_patch(hw); if (flag & ATL1C_PCIE_L0S_L1_DISABLE) atl1c_disable_l0s_l1(hw); msleep(5); } /** * atl1c_irq_enable - Enable default interrupt generation settings * @adapter: board private structure */ static inline void atl1c_irq_enable(struct atl1c_adapter *adapter) { if (likely(atomic_dec_and_test(&adapter->irq_sem))) { AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF); AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask); AT_WRITE_FLUSH(&adapter->hw); } } /** * atl1c_irq_disable - Mask off interrupt generation on the NIC * @adapter: board private structure */ static inline void atl1c_irq_disable(struct atl1c_adapter *adapter) { atomic_inc(&adapter->irq_sem); AT_WRITE_REG(&adapter->hw, REG_IMR, 0); AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT); AT_WRITE_FLUSH(&adapter->hw); synchronize_irq(adapter->pdev->irq); } /** * atl1c_irq_reset - reset interrupt confiure on the NIC * @adapter: board private structure */ static inline void atl1c_irq_reset(struct atl1c_adapter *adapter) { atomic_set(&adapter->irq_sem, 1); atl1c_irq_enable(adapter); } /* * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads * of the idle status register until the device is actually idle */ static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl) { int timeout; u32 data; for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { AT_READ_REG(hw, REG_IDLE_STATUS, &data); if ((data & modu_ctrl) == 0) return 0; msleep(1); } return data; } /** * atl1c_phy_config - Timer Call-back * @data: pointer to netdev cast into an unsigned long */ static void atl1c_phy_config(unsigned long data) { struct atl1c_adapter *adapter = (struct atl1c_adapter *) data; struct atl1c_hw *hw = &adapter->hw; unsigned long flags; spin_lock_irqsave(&adapter->mdio_lock, flags); atl1c_restart_autoneg(hw); spin_unlock_irqrestore(&adapter->mdio_lock, flags); } void atl1c_reinit_locked(struct atl1c_adapter *adapter) { WARN_ON(in_interrupt()); atl1c_down(adapter); atl1c_up(adapter); clear_bit(__AT_RESETTING, &adapter->flags); } static void atl1c_check_link_status(struct atl1c_adapter *adapter) { struct atl1c_hw *hw = &adapter->hw; struct net_device *netdev = adapter->netdev; struct pci_dev *pdev = adapter->pdev; int err; unsigned long flags; u16 speed, duplex, phy_data; spin_lock
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