SST39VF160-Nor-Flash-Data-Sheet.zip_nor flash_单片机开发_嵌入式/单片机/硬件编程下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Data S<span class="_ _0"></span>heet</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">©<span class="_ _0"></span>2001 S<span class="_ _0"></span>ilicon Storage Technology, Inc.</div><div class="t m0 x2 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">S71145-0<span class="_ _1"></span>2-000<span class="_ _2"> </span>6/01<span class="_ _3"> </span>399</div><div class="t m0 x2 h3 y4 ff2 fs1 fc1 sc0 ls3 ws2">1</div><div class="t m0 x3 h3 y2 ff2 fs1 fc0 sc0 ls4 ws3">The SST logo an<span class="_ _1"></span>d SuperFlash are r<span class="_ _1"></span>egistered tra<span class="_ _1"></span>demarks of Silicon Storage T<span class="_ _4"></span>echnology<span class="_ _4"></span>, Inc.</div><div class="t m0 x4 h3 y3 ff2 fs1 fc0 sc0 ls5 ws4">MPF is a trademark of Silicon Storage T<span class="_ _4"></span>echnology<span class="_ _5"></span>, Inc.</div><div class="t m0 x5 h3 y4 ff2 fs1 fc0 sc0 ls6 ws5">These specif<span class="_ _1"></span>ications are sub<span class="_ _1"></span>ject to change with<span class="_ _1"></span>out notice.</div><div class="t m0 x6 h4 y5 ff3 fs2 fc0 sc0 ls7 ws2">16 Mbit<span class="_ _6"> </span>(x16)<span class="_ _6"> </span>Multi-Purpose Flash</div><div class="t m0 x7 h5 y6 ff3 fs3 fc0 sc0 ls3 ws6">SST39LF160 / SST39VF160</div><div class="t m0 x2 h5 y7 ff3 fs3 fc0 sc0 ls8 ws2">FEATURES:</div><div class="t m0 x2 h6 y8 ff3 fs0 fc0 sc0 ls9 ws7">•<span class="_ _7"> </span>Organized<span class="_ _0"></span> as 1M x1<span class="_ _0"></span>6</div><div class="t m0 x2 h6 y9 ff3 fs0 fc0 sc0 lsa ws8">•<span class="_ _7"> </span>Single V<span class="_ _5"></span>oltag<span class="_ _0"></span>e Read and W<span class="_ _0"></span>rite Oper<span class="_ _0"></span>ations</div><div class="t m0 x8 h7 ya ff2 fs0 fc0 sc0 lsb ws9">–<span class="_ _8"> </span>3.0-3.6V<span class="_ _0"></span> f<span class="_ _1"></span>or SST<span class="_ _0"></span>39LF160</div><div class="t m0 x8 h7 yb ff2 fs0 fc0 sc0 lsb ws9">–<span class="_ _8"> </span>2.7-3.6V<span class="_ _0"></span> f<span class="_ _1"></span>or SST<span class="_ _0"></span>39VF160</div><div class="t m0 x2 h6 yc ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 lsc wsa">Superior Rel<span class="_ _0"></span>iability</span></div><div class="t m0 x8 h7 yd ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsb ws9">Endurance<span class="_ _0"></span>: 100,000 Cy<span class="_ _0"></span>cles (ty<span class="_ _0"></span>pical)</span></div><div class="t m0 x8 h7 ye ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsd wsb">Greater th<span class="_ _0"></span>an 100 years Data<span class="_ _0"></span> Retention</span></div><div class="t m0 x2 h6 yf ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 lse wsc">Low P<span class="_ _5"></span>ower Consump<span class="_ _1"></span>tion</span></div><div class="t m0 x8 h7 y10 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsf wsd">Active Current: 15 mA (typical)</span></div><div class="t m0 x8 h7 y11 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls9 ws7">Standby Current<span class="_ _0"></span>: 4 µA (typi<span class="_ _0"></span>cal)</span></div><div class="t m0 x8 h7 y12 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls10 wse">A<span class="_ _1"></span>uto Low P<span class="_ _1"></span>ow<span class="_ _1"></span>er Mode<span class="_ _0"></span>: 4 µA (typi<span class="_ _0"></span>cal)</span></div><div class="t m0 x2 h6 y13 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls11 wsf">Sector<span class="_ _1"></span>-Erase Capability</span></div><div class="t m0 x8 h7 y14 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls12 ws10">Unif<span class="_ _5"></span>orm 2 KW<span class="_ _5"></span>ord sect<span class="_ _1"></span>ors</span></div><div class="t m0 x2 h6 y15 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls13 ws11">Fast Read Access<span class="_ _0"></span> Time</span></div><div class="t m0 x8 h7 y16 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls14 ws12">55 ns f<span class="_ _5"></span>o<span class="_ _0"></span>r SST39LF1<span class="_ _0"></span>60</span></div><div class="t m0 x8 h7 y17 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls15 ws13">70 and 90 ns f<span class="_ _5"></span>or<span class="_ _0"></span> SST39VF1<span class="_ _0"></span>60</span></div><div class="t m0 x2 h6 y18 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls16">Latched Address <span class="_ _0"></span>and Data</span></div><div class="t m0 x9 h6 y19 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls17 ws14">Fast Erase and<span class="_ _0"></span> W<span class="_ _5"></span>ord-Program</span></div><div class="t m0 xa h7 y1a ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls18 ws15">Sec<span class="_ _1"></span>tor-<span class="_ _1"></span>Erase<span class="_ _1"></span> Time<span class="_ _1"></span>: 18 ms<span class="_ _1"></span> (typ<span class="_ _1"></span>ical<span class="_ _1"></span>)</span></div><div class="t m0 xa h7 y1b ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls19 ws16">Block-Erase Ti<span class="_ _0"></span>me: 18 ms<span class="_ _0"></span> (typic<span class="_ _0"></span>al)</span></div><div class="t m0 xa h7 y1c ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsb ws9">Chip-Erase <span class="_ _0"></span>Time: 70<span class="_ _0"></span> ms (typic<span class="_ _0"></span>al)</span></div><div class="t m0 xa h7 y1d ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls1a ws17">W<span class="_ _1"></span>ord-Pr<span class="_ _1"></span>ogra<span class="_ _1"></span>m Time: 14 µs (typ<span class="_ _1"></span>ical)</span></div><div class="t m0 xa h7 y1e ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsf ws18">Chip Rewrite T<span class="_ _0"></span>ime: 15 s<span class="_ _0"></span>econds<span class="_ _0"></span> (typical)<span class="_ _0"></span> for </span></div><div class="t m0 xb h7 y1f ff5 fs0 fc0 sc0 ls1b ws2">SST39LF/VF160</div><div class="t m0 x9 h6 y20 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls1c ws19">A<span class="_ _1"></span>utomatic Wri<span class="_ _1"></span>te Timing</span></div><div class="t m0 xa h7 y21 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsa ws8">Inter<span class="_ _0"></span>nal V</span></div><div class="t m0 xc h8 y22 ff5 fs4 fc0 sc0 ls1d ws2">PP</div><div class="t m0 xd h7 y23 ff5 fs0 fc0 sc0 ls14 ws1a"> Generatio<span class="_ _0"></span>n</div><div class="t m0 x9 h6 y24 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls1e ws1b">End-of-Wri<span class="_ _1"></span>te Detection</span></div><div class="t m0 xa h7 y25 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls1f ws1c">T<span class="_ _4"></span>oggle Bit</span></div><div class="t m0 xa h7 y26 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls20 ws1d">Data# Polling</span></div><div class="t m0 x9 h6 y27 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls21 ws1e">CMOS I/O Compat<span class="_ _0"></span>ibility </span></div><div class="t m0 x9 h6 y28 ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls22 ws1f">JEDEC Standard</span></div><div class="t m0 xa h7 y29 ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 lsb ws9">Flash EE<span class="_ _0"></span>PROM Pinouts<span class="_ _0"></span> and comm<span class="_ _0"></span>and sets</span></div><div class="t m0 x9 h6 y2a ff3 fs0 fc0 sc0 ls3 ws2">•<span class="_ _7"> </span><span class="ff4 ls9 ws7">P<span class="_ _1"></span>ackages A<span class="_ _1"></span>vailable</span></div><div class="t m0 xa h7 y2b ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls17 ws14">48-lead T<span class="_ _0"></span>SOP (12mm<span class="_ _0"></span> x 20mm)</span></div><div class="t m0 xa h7 y2c ff2 fs0 fc0 sc0 ls3 ws2">–<span class="_ _8"> </span><span class="ff5 ls23 ws20">48-ball<span class="_ _0"></span> TFBGA<span class="_ _0"></span> (6mm x 8<span class="_ _0"></span>mm)</span></div><div class="t m0 x2 h5 y2d ff4 fs3 fc0 sc0 ls24 ws21">PRODUCT DESCRIPTION</div><div class="t m0 x2 h7 y2e ff5 fs0 fc0 sc0 ls25 ws22">The SS<span class="_ _0"></span>T39L<span class="_ _0"></span>F/VF16<span class="_ _0"></span>0 devices <span class="_ _0"></span>are 1M x<span class="_ _0"></span>16 CMOS<span class="_ _0"></span> Mult<span class="_ _0"></span>i-</div><div class="t m0 x2 h7 y2f ff5 fs0 fc0 sc0 ls26 ws23">Pur<span class="_ _0"></span>p<span class="_ _0"></span>ose Flash (MP<span class="_ _0"></span>F) manufactured<span class="_ _0"></span> with SST<span class="ff2 ls3 ws2">’<span class="_ _5"></span><span class="ff5 ls27 ws24">s propr<span class="_ _0"></span>ietar<span class="_ _9"></span>y<span class="_ _4"></span>,</span></span></div><div class="t m0 x2 h7 y30 ff5 fs0 fc0 sc0 ls28 ws25">high pe<span class="_ _0"></span>rf<span class="_ _1"></span>or<span class="_ _0"></span>man<span class="_ _0"></span>ce CMO<span class="_ _0"></span>S Supe<span class="_ _0"></span>rFlash <span class="_ _0"></span>technol<span class="_ _0"></span>og<span class="_ _1"></span>y<span class="_ _4"></span>. T<span class="_ _0"></span>he</div><div class="t m0 x2 h7 y31 ff5 fs0 fc0 sc0 ls29 ws26">split-<span class="_ _0"></span>gate<span class="_ _0"></span> cell <span class="_ _0"></span>design<span class="_ _0"></span> and<span class="_ _0"></span> thick <span class="_ _0"></span>oxide tunn<span class="_ _0"></span>elin<span class="_ _0"></span>g inje<span class="_ _0"></span>ctor</div><div class="t m0 x2 h7 y32 ff5 fs0 fc0 sc0 ls2a ws27">attain be<span class="_ _0"></span>tter rel<span class="_ _0"></span>iability<span class="_ _0"></span> and manufacturabili<span class="_ _0"></span>ty comp<span class="_ _0"></span>ared wit<span class="_ _0"></span>h</div><div class="t m0 x2 h7 y33 ff5 fs0 fc0 sc0 ls28 ws28">alter<span class="_ _0"></span>nate<span class="_ _0"></span> approac<span class="_ _0"></span>hes. The SS<span class="_ _0"></span>T39LF<span class="_ _0"></span>160 wr<span class="_ _0"></span>ite (Pr<span class="_ _0"></span>ogram or</div><div class="t m0 x2 h7 y34 ff5 fs0 fc0 sc0 ls2b ws29">Erase) wit<span class="_ _0"></span>h a 3.0-<span class="_ _0"></span>3.6V power su<span class="_ _0"></span>pply<span class="_ _4"></span>.<span class="_ _0"></span> The SST3<span class="_ _0"></span>9VF16<span class="_ _0"></span>0</div><div class="t m0 x2 h7 y35 ff5 fs0 fc0 sc0 ls28 ws2a">wri<span class="_ _0"></span>te (Program or<span class="_ _0"></span> Erase) with<span class="_ _0"></span> a 2.7-3.<span class="_ _0"></span>6V power supply<span class="_ _5"></span>.</div><div class="t m0 x2 h7 y36 ff5 fs0 fc0 sc0 ls28 ws0">These devices c<span class="_ _0"></span>onform <span class="_ _0"></span>to JEDE<span class="_ _0"></span>C standa<span class="_ _0"></span>rd pino<span class="_ _0"></span>uts for x16</div><div class="t m0 x2 h7 y37 ff5 fs0 fc0 sc0 ls28 ws2">memor<span class="_ _0"></span>ies.</div><div class="t m0 x2 h7 y38 ff5 fs0 fc0 sc0 ls2c ws2b">F<span class="_ _1"></span>eatu<span class="_ _0"></span>rin<span class="_ _0"></span>g high perfor<span class="_ _0"></span>mance<span class="_ _0"></span> Word-Program, the S<span class="_ _0"></span>ST39L<span class="_ _0"></span>F/</div><div class="t m0 x2 h7 y39 ff5 fs0 fc0 sc0 ls2d ws2c">VF16<span class="_ _1"></span>0 de<span class="_ _5"></span>vices pro<span class="_ _1"></span>vide a ty<span class="_ _1"></span>pical W<span class="_ _5"></span>ord-Pr<span class="_ _1"></span>ogr<span class="_ _1"></span>am time<span class="_ _1"></span> of 14</div><div class="t m0 x2 h7 y3a ff5 fs0 fc0 sc0 ls2b ws2d">µsec.Th<span class="_ _0"></span>ese d<span class="_ _0"></span>evices use T<span class="_ _4"></span>ogg<span class="_ _0"></span>le Bit <span class="_ _0"></span>or Data#<span class="_ _0"></span> P<span class="_ _5"></span>o<span class="_ _0"></span>lling t<span class="_ _0"></span>o ind<span class="_ _0"></span>i-</div><div class="t m0 x2 h7 y3b ff5 fs0 fc0 sc0 ls2e ws2e">cate<span class="_ _0"></span> the comp<span class="_ _0"></span>letio<span class="_ _0"></span>n of Pro<span class="_ _0"></span>gram operatio<span class="_ _0"></span>n. T<span class="_ _4"></span>o prot<span class="_ _0"></span>ect</div><div class="t m0 x2 h7 y3c ff5 fs0 fc0 sc0 ls28 ws2f">agains<span class="_ _0"></span>t inadver<span class="_ _0"></span>ten<span class="_ _0"></span>t wri<span class="_ _0"></span>te, they hav<span class="_ _5"></span>e<span class="_ _0"></span> on-chi<span class="_ _0"></span>p hardware an<span class="_ _0"></span>d</div><div class="t m0 x2 h7 y3d ff5 fs0 fc0 sc0 ls28 ws30">Software Dat<span class="_ _0"></span>a Prote<span class="_ _0"></span>ction sch<span class="_ _0"></span>emes. Desi<span class="_ _0"></span>gned, manufac-</div><div class="t m0 x2 h7 y3e ff5 fs0 fc0 sc0 ls27 ws31">tured, a<span class="_ _0"></span>nd tested<span class="_ _0"></span> f<span class="_ _1"></span>or a wi<span class="_ _0"></span>de spect<span class="_ _0"></span>rum<span class="_ _0"></span> of applic<span class="_ _0"></span>ations, the<span class="_ _0"></span>se</div><div class="t m0 x2 h7 y3f ff5 fs0 fc0 sc0 ls2f ws32">devices are offered wi<span class="_ _0"></span>th a gua<span class="_ _0"></span>ranteed en<span class="_ _0"></span>durance<span class="_ _0"></span> of 10,00<span class="_ _0"></span>0</div><div class="t m0 x2 h7 y40 ff5 fs0 fc0 sc0 ls30 ws33">cycl<span class="_ _0"></span>es. Data re<span class="_ _0"></span>tention i<span class="_ _0"></span>s rated <span class="_ _0"></span>at greater<span class="_ _0"></span> than 10<span class="_ _0"></span>0 years.</div><div class="t m0 x2 h7 y41 ff5 fs0 fc0 sc0 ls31 ws34">The SS<span class="_ _0"></span>T39LF<span class="_ _0"></span>/VF16<span class="_ _0"></span>0 devices ar<span class="_ _0"></span>e suit<span class="_ _0"></span>ed for applic<span class="_ _0"></span>atio<span class="_ _0"></span>ns</div><div class="t m0 x2 h7 y42 ff5 fs0 fc0 sc0 ls32 ws35">that req<span class="_ _0"></span>uire convenient an<span class="_ _0"></span>d econo<span class="_ _0"></span>mical upd<span class="_ _0"></span>ating of <span class="_ _0"></span>pro-</div><div class="t m0 x2 h7 y43 ff5 fs0 fc0 sc0 ls33 ws36">gr<span class="_ _1"></span>am,<span class="_ _1"></span> configur<span class="_ _1"></span>at<span class="_ _1"></span>ion, or<span class="_ _1"></span> data me<span class="_ _1"></span>mory<span class="_ _4"></span>. Fo<span class="_ _1"></span>r all syst<span class="_ _1"></span>em app<span class="_ _1"></span>li-</div><div class="t m0 x2 h7 y44 ff5 fs0 fc0 sc0 ls34 ws37">cations, th<span class="_ _0"></span>ey signif<span class="_ _0"></span>icantly<span class="_ _0"></span> improve performa<span class="_ _0"></span>nce an<span class="_ _0"></span>d</div><div class="t m0 x2 h7 y45 ff5 fs0 fc0 sc0 ls34 ws38">relia<span class="_ _0"></span>bility<span class="_ _5"></span>, while<span class="_ _0"></span> lowering p<span class="_ _0"></span>ower consum<span class="_ _0"></span>ption<span class="_ _0"></span>. They inher-</div><div class="t m0 x2 h7 y46 ff5 fs0 fc0 sc0 ls27 ws39">ently <span class="_ _0"></span>use les<span class="_ _0"></span>s energy dur<span class="_ _0"></span>ing<span class="_ _0"></span> Erase and<span class="_ _0"></span> Program <span class="_ _0"></span>than al<span class="_ _0"></span>ter-</div><div class="t m0 x2 h7 y47 ff5 fs0 fc0 sc0 ls2c ws3a">native flash te<span class="_ _0"></span>chnolo<span class="_ _0"></span>gies. The to<span class="_ _0"></span>tal energy consu<span class="_ _0"></span>med is a</div><div class="t m0 x2 h7 y48 ff5 fs0 fc0 sc0 ls2c ws9">functio<span class="_ _0"></span>n of th<span class="_ _0"></span>e appli<span class="_ _0"></span>ed voltage, cur<span class="_ _0"></span>rent, an<span class="_ _0"></span>d time of<span class="_ _0"></span> applic<span class="_ _0"></span>a-</div><div class="t m0 x2 h7 y49 ff5 fs0 fc0 sc0 ls2c ws3b">tion. Si<span class="_ _0"></span>nce for any given voltage range, the S<span class="_ _0"></span>uperF<span class="_ _0"></span>lash</div><div class="t m0 x9 h7 y4a ff5 fs0 fc0 sc0 ls2c ws3c">technol<span class="_ _0"></span>ogy uses less cur<span class="_ _0"></span>rent to p<span class="_ _0"></span>rogram and h<span class="_ _0"></span>as a shor<span class="_ _9"></span>ter</div><div class="t m0 x9 h7 y4b ff5 fs0 fc0 sc0 ls27 ws3d">erase time, the tot<span class="_ _0"></span>al ene<span class="_ _0"></span>rg<span class="_ _1"></span>y consu<span class="_ _0"></span>med dur<span class="_ _0"></span>ing<span class="_ _0"></span> any Erase or</div><div class="t m0 x9 h7 y4c ff5 fs0 fc0 sc0 ls35 ws3e">Program o<span class="_ _0"></span>peration is<span class="_ _0"></span> less<span class="_ _0"></span> than al<span class="_ _0"></span>ter<span class="_ _0"></span>native flash <span class="_ _0"></span>techn<span class="_ _0"></span>olo-</div><div class="t m0 x9 h7 y4d ff5 fs0 fc0 sc0 ls36 ws3f">gies. These<span class="_ _0"></span> devices also<span class="_ _0"></span> improve flexibility wh<span class="_ _0"></span>ile lower<span class="_ _0"></span>ing</div><div class="t m0 x9 h7 y4e ff5 fs0 fc0 sc0 ls26 ws40">the cos<span class="_ _0"></span>t for program, data<span class="_ _0"></span>, and con<span class="_ _0"></span>figurat<span class="_ _0"></span>ion sto<span class="_ _0"></span>rage appl<span class="_ _0"></span>i-</div><div class="t m0 x9 h7 y4f ff5 fs0 fc0 sc0 ls37 ws2">cations.</div><div class="t m0 x9 h7 y50 ff5 fs0 fc0 sc0 ls2b ws41">The S<span class="_ _0"></span>uperFlas<span class="_ _0"></span>h te<span class="_ _0"></span>chnology pr<span class="_ _0"></span>ovides fi<span class="_ _0"></span>x<span class="_ _1"></span>ed Eras<span class="_ _0"></span>e and P<span class="_ _0"></span>ro-</div><div class="t m0 x9 h7 y51 ff5 fs0 fc0 sc0 ls2c ws42">gram times, in<span class="_ _0"></span>depende<span class="_ _0"></span>nt of th<span class="_ _0"></span>e numbe<span class="_ _0"></span>r of Erase/<span class="_ _0"></span>Program</div><div class="t m0 x9 h7 y52 ff5 fs0 fc0 sc0 ls38 ws43">cycle<span class="_ _1"></span>s that<span class="_ _1"></span> ha<span class="_ _1"></span>v<span class="_ _1"></span>e occ<span class="_ _1"></span>urred<span class="_ _1"></span>. Ther<span class="_ _1"></span>ef<span class="_ _5"></span>ore the sys<span class="_ _1"></span>tem sof<span class="_ _1"></span>tw<span class="_ _1"></span>are</div><div class="t m0 x9 h7 y53 ff5 fs0 fc0 sc0 ls2a ws13">or hardwa<span class="_ _0"></span>re doe<span class="_ _0"></span>s not h<span class="_ _0"></span>av<span class="_ _1"></span>e to be<span class="_ _0"></span> modifi<span class="_ _0"></span>ed or <span class="_ _0"></span>de-rated<span class="_ _0"></span> as is</div><div class="t m0 x9 h7 y54 ff5 fs0 fc0 sc0 ls39 ws44">nece<span class="_ _0"></span>ssar<span class="_ _0"></span>y<span class="_ _0"></span> with a<span class="_ _0"></span>lter<span class="_ _0"></span>nat<span class="_ _0"></span>ive flash te<span class="_ _0"></span>chnolog<span class="_ _0"></span>ies, who<span class="_ _0"></span>se Eras<span class="_ _0"></span>e</div><div class="t m0 x9 h7 y55 ff5 fs0 fc0 sc0 ls2f ws45">and Pr<span class="_ _0"></span>ogram times<span class="_ _0"></span> increas<span class="_ _0"></span>e with<span class="_ _0"></span> accumul<span class="_ _0"></span>ated E<span class="_ _0"></span>rase/Pro-</div><div class="t m0 x9 h7 y56 ff5 fs0 fc0 sc0 ls33 ws46">gr<span class="_ _1"></span>am cycl<span class="_ _1"></span>es.</div><div class="t m0 x9 h7 y57 ff5 fs0 fc0 sc0 ls3a ws47">T<span class="_ _4"></span>o<span class="_ _1"></span> meet<span class="_ _1"></span> high<span class="_ _1"></span> densi<span class="_ _1"></span>ty<span class="_ _4"></span>, su<span class="_ _1"></span>rf<span class="_ _1"></span>ace<span class="_ _1"></span> mount<span class="_ _1"></span> requ<span class="_ _1"></span>irem<span class="_ _1"></span>ents<span class="_ _1"></span>, the</div><div class="t m0 x9 h7 y58 ff5 fs0 fc0 sc0 ls2b ws48">SST39<span class="_ _0"></span>LF/VF16<span class="_ _0"></span>0 are offered in 48-<span class="_ _0"></span>lead TS<span class="_ _0"></span>OP and 48-b<span class="_ _0"></span>all</div><div class="t m0 x9 h7 y59 ff5 fs0 fc0 sc0 ls35 ws9">TFBGA<span class="_ _0"></span> packages. See F<span class="_ _0"></span>igure 1<span class="_ _0"></span> for pinout<span class="_ _0"></span>s.</div><div class="t m0 x9 h5 y5a ff4 fs3 fc0 sc0 ls3b ws49">Device Operation</div><div class="t m0 x9 h7 y5b ff5 fs0 fc0 sc0 ls2c ws4a">Comma<span class="_ _0"></span>nds are us<span class="_ _0"></span>ed to<span class="_ _0"></span> initiat<span class="_ _0"></span>e the m<span class="_ _0"></span>emor<span class="_ _0"></span>y o<span class="_ _0"></span>peration f<span class="_ _0"></span>unc-</div><div class="t m0 x9 h7 y5c ff5 fs0 fc0 sc0 ls2c ws4b">tions of<span class="_ _0"></span> the device. Comman<span class="_ _0"></span>ds are w<span class="_ _0"></span>rit<span class="_ _0"></span>ten to th<span class="_ _0"></span>e device</div><div class="t m0 x9 h7 y5d ff5 fs0 fc0 sc0 ls39 ws4c">using s<span class="_ _0"></span>tanda<span class="_ _0"></span>rd micr<span class="_ _0"></span>oproc<span class="_ _0"></span>essor wr<span class="_ _0"></span>it<span class="_ _0"></span>e sequen<span class="_ _0"></span>ces. A co<span class="_ _0"></span>m-</div><div class="t m0 x9 h7 y5e ff5 fs0 fc0 sc0 ls2f ws4d">mand is<span class="_ _0"></span> written<span class="_ _0"></span> by asser<span class="_ _9"></span>ting WE<span class="_ _0"></span># low while keeping<span class="_ _0"></span> CE#</div><div class="t m0 x9 h7 y5f ff5 fs0 fc0 sc0 ls26 ws4e">low<span class="_ _5"></span>. Th<span class="_ _0"></span>e addr<span class="_ _0"></span>ess bus is <span class="_ _0"></span>latche<span class="_ _0"></span>d on <span class="_ _0"></span>the falling e<span class="_ _0"></span>dge o<span class="_ _0"></span>f WE#</div><div class="t m0 x9 h7 y60 ff5 fs0 fc0 sc0 ls2a ws4f">or CE#, <span class="_ _0"></span>whichev<span class="_ _1"></span>er occu<span class="_ _0"></span>rs last.<span class="_ _0"></span> The data<span class="_ _0"></span> bus is latc<span class="_ _0"></span>hed on</div><div class="t m0 x9 h7 y61 ff5 fs0 fc0 sc0 ls28 ws14">the r<span class="_ _0"></span>ising<span class="_ _0"></span> edge of <span class="_ _0"></span>WE# <span class="_ _0"></span>or CE#,<span class="_ _0"></span> whichev<span class="_ _1"></span>er occ<span class="_ _0"></span>urs firs<span class="_ _0"></span>t.</div><div class="t m0 xe h3 y62 ff5 fs1 fc1 sc0 ls3c ws50">SST39LF/<span class="_ _1"></span>VF1603<span class="_ _1"></span>.0 & 2.7V 16<span class="_ _1"></span>Mb (x16) MP<span class="_ _1"></span>F memories</div><div class="d m1"></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/bg2.jpg"><div class="t m2 xf h9 y63 ff5 fs5 fc0 sc0 ls3 ws2">2</div><div class="t m2 x10 h7 y1 ff5 fs0 fc0 sc0 ls16 ws2">Data Shee<span class="_ _0"></span>t</div><div class="t m2 x11 ha y64 ff4 fs6 fc0 sc0 ls3d ws51">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m2 x12 ha y65 ff4 fs6 fc0 sc0 ls3e ws2">SST39LF160 / SST39VF1<span class="_ _0"></span>60</div><div class="t m2 x2 h3 y2 ff5 fs1 fc0 sc0 ls3f ws52">©<span class="_ _0"></span>2001 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>6/01<span class="_ _a"> </span>399</span></div><div class="t m2 x2 h6 y66 ff5 fs0 fc0 sc0 ls26 ws53">The SS<span class="_ _0"></span>T39LF/V<span class="_ _0"></span>F160 al<span class="_ _0"></span>so hav<span class="_ _1"></span>e the<span class="_ _0"></span> <span class="ff4 ls40 ws54">A<span class="_ _1"></span>uto Low P<span class="_ _5"></span>ower</span></div><div class="t m2 x2 h7 y67 ff5 fs0 fc0 sc0 ls35 ws55">mode whic<span class="_ _0"></span>h puts the device<span class="_ _0"></span> in a near stand<span class="_ _0"></span>by mode after</div><div class="t m2 x2 h7 y68 ff5 fs0 fc0 sc0 ls41 ws56">data<span class="_ _1"></span> has be<span class="_ _1"></span>en acce<span class="_ _1"></span>ssed w<span class="_ _1"></span>ith a <span class="_ _1"></span>va<span class="_ _1"></span>lid Re<span class="_ _1"></span>ad ope<span class="_ _1"></span>rati<span class="_ _1"></span>on. T<span class="_ _1"></span>his</div><div class="t m2 x2 h7 y69 ff5 fs0 fc0 sc0 ls42 ws57">reduce<span class="_ _0"></span>s the <span class="_ _0"></span>I</div><div class="t m2 x13 h8 y6a ff5 fs4 fc0 sc0 ls43 ws2">DD</div><div class="t m2 x14 h7 y6b ff5 fs0 fc0 sc0 ls2f ws58"> active read current fr<span class="_ _0"></span>om typical<span class="_ _0"></span>ly 15 mA to</div><div class="t m2 x2 h7 y6c ff5 fs0 fc0 sc0 ls2b ws59">typica<span class="_ _0"></span>lly 4 µA<span class="_ _0"></span>. The Auto Low P<span class="_ _5"></span>ower mode<span class="_ _0"></span> reduce<span class="_ _0"></span>s the ty<span class="_ _0"></span>pi-</div><div class="t m2 x2 h7 y6d ff5 fs0 fc0 sc0 ls44 ws5a">cal I</div><div class="t m2 x15 h8 y6e ff5 fs4 fc0 sc0 ls43 ws2">DD</div><div class="t m2 x16 h7 y6f ff5 fs0 fc0 sc0 ls2f ws5b"> active read cur<span class="_ _0"></span>rent to t<span class="_ _0"></span>he range o<span class="_ _0"></span>f 1 mA/MHz<span class="_ _0"></span> of</div><div class="t m2 x2 h7 y70 ff5 fs0 fc0 sc0 ls45 ws5c">read cyc<span class="_ _1"></span>le time<span class="_ _1"></span>. The de<span class="_ _1"></span>vice<span class="_ _1"></span> e<span class="_ _1"></span>xits the A<span class="_ _5"></span>uto Low P<span class="_ _5"></span>ow<span class="_ _1"></span>er</div><div class="t m2 x2 h7 y71 ff5 fs0 fc0 sc0 ls30 ws5d">mode wit<span class="_ _0"></span>h any add<span class="_ _0"></span>ress <span class="_ _0"></span>transition<span class="_ _0"></span> or con<span class="_ _0"></span>trol s<span class="_ _0"></span>ignal tra<span class="_ _0"></span>nsition</div><div class="t m2 x2 h7 y72 ff5 fs0 fc0 sc0 ls30 ws5e">used to i<span class="_ _0"></span>nitiate a<span class="_ _0"></span>nothe<span class="_ _0"></span>r Read<span class="_ _0"></span> cycle, with no<span class="_ _0"></span> acces<span class="_ _0"></span>s time</div><div class="t m2 x2 h7 y73 ff5 fs0 fc0 sc0 ls46 ws5f">penalty<span class="_ _5"></span>. Note that <span class="_ _0"></span>the device does n<span class="_ _0"></span>ot enter<span class="_ _0"></span> A<span class="_ _1"></span>uto L<span class="_ _0"></span>ow</div><div class="t m2 x2 h7 y74 ff5 fs0 fc0 sc0 ls47 ws60">P<span class="_ _5"></span>ow<span class="_ _1"></span>er mo<span class="_ _1"></span>de a<span class="_ _1"></span>fter <span class="_ _1"></span>pow<span class="_ _5"></span>er-up wi<span class="_ _1"></span>th CE<span class="_ _1"></span># he<span class="_ _1"></span>ld ste<span class="_ _1"></span>adi<span class="_ _1"></span>ly lo<span class="_ _1"></span>w unt<span class="_ _1"></span>il</div><div class="t m2 x2 h7 y75 ff5 fs0 fc0 sc0 ls38 ws44">the f<span class="_ _1"></span>irst a<span class="_ _1"></span>ddre<span class="_ _1"></span>ss tran<span class="_ _1"></span>siti<span class="_ _1"></span>on or<span class="_ _1"></span> CE# is driv<span class="_ _5"></span>en high.</div><div class="t m2 x2 h5 y76 ff4 fs3 fc0 sc0 ls48 ws2">Read</div><div class="t m2 x2 h7 y77 ff5 fs0 fc0 sc0 ls3a ws3f">The R<span class="_ _1"></span>ead op<span class="_ _1"></span>erat<span class="_ _1"></span>ion o<span class="_ _1"></span>f the S<span class="_ _1"></span>ST39L<span class="_ _1"></span>F/VF16<span class="_ _1"></span>0 is co<span class="_ _1"></span>ntroll<span class="_ _1"></span>ed</div><div class="t m2 x2 h7 y78 ff5 fs0 fc0 sc0 ls49 ws61">by CE# and OE<span class="_ _0"></span>#, bot<span class="_ _0"></span>h hav<span class="_ _1"></span>e to be l<span class="_ _0"></span>ow f<span class="_ _1"></span>or the s<span class="_ _0"></span>ystem t<span class="_ _0"></span>o</div><div class="t m2 x2 h7 y79 ff5 fs0 fc0 sc0 ls27 ws62">obtain da<span class="_ _0"></span>ta from th<span class="_ _0"></span>e outpu<span class="_ _0"></span>ts. CE# is us<span class="_ _0"></span>ed for de<span class="_ _1"></span>vice sel<span class="_ _0"></span>ec-</div><div class="t m2 x2 h7 y7a ff5 fs0 fc0 sc0 ls4a ws63">tion. Wh<span class="_ _0"></span>en CE#<span class="_ _0"></span> is h<span class="_ _0"></span>igh, the c<span class="_ _0"></span>hip<span class="_ _0"></span> is dese<span class="_ _0"></span>lec<span class="_ _0"></span>ted and<span class="_ _0"></span> only</div><div class="t m2 x2 h7 y7b ff5 fs0 fc0 sc0 ls2b ws64">stan<span class="_ _0"></span>dby po<span class="_ _1"></span>wer is consum<span class="_ _0"></span>ed. OE# is<span class="_ _0"></span> the output<span class="_ _0"></span> control an<span class="_ _0"></span>d</div><div class="t m2 x2 h7 y7c ff5 fs0 fc0 sc0 ls4b ws65">is us<span class="_ _0"></span>ed to g<span class="_ _0"></span>ate data<span class="_ _0"></span> from <span class="_ _0"></span>the o<span class="_ _0"></span>utput pi<span class="_ _0"></span>ns. The da<span class="_ _0"></span>ta bus is i<span class="_ _0"></span>n</div><div class="t m2 x2 h7 y7d ff5 fs0 fc0 sc0 ls32 ws30">high imp<span class="_ _0"></span>edance s<span class="_ _0"></span>tate when eit<span class="_ _0"></span>her CE# or OE<span class="_ _0"></span># is high.</div><div class="t m2 x2 h7 y7e ff5 fs0 fc0 sc0 ls32 ws66">Refer to the Read cycl<span class="_ _0"></span>e timing dia<span class="_ _0"></span>gram f<span class="_ _1"></span>or fur<span class="_ _0"></span>th<span class="_ _0"></span>er detai<span class="_ _0"></span>ls</div><div class="t m2 x2 h7 y7f ff5 fs0 fc0 sc0 ls39 ws67">(Fig<span class="_ _0"></span>ure 2).</div><div class="t m2 x2 h5 y80 ff4 fs3 fc0 sc0 ls4c ws68">Word-Program<span class="_ _1"></span> Operation</div><div class="t m2 x2 h7 y81 ff5 fs0 fc0 sc0 ls2c ws2b">The SS<span class="_ _0"></span>T39LF/V<span class="_ _0"></span>F160 <span class="_ _0"></span>are pr<span class="_ _0"></span>ogrammed on<span class="_ _0"></span> a word-<span class="_ _0"></span>by-word</div><div class="t m2 x2 h7 y82 ff5 fs0 fc0 sc0 ls2c ws69">basis. Be<span class="_ _0"></span>f<span class="_ _1"></span>ore program<span class="_ _0"></span>ming, on<span class="_ _0"></span>e must en<span class="_ _0"></span>sure that t<span class="_ _0"></span>he sec-</div><div class="t m2 x2 h7 y83 ff5 fs0 fc0 sc0 ls2c ws6a">tor<span class="_ _5"></span>, <span class="_ _0"></span>in wh<span class="_ _0"></span>ich the<span class="_ _0"></span> word whi<span class="_ _0"></span>ch is<span class="_ _0"></span> being <span class="_ _0"></span>programme<span class="_ _0"></span>d exists, is</div><div class="t m2 x2 h7 y84 ff5 fs0 fc0 sc0 ls2c ws6b">fully eras<span class="_ _0"></span>ed. The P<span class="_ _0"></span>rogram operatio<span class="_ _0"></span>n consi<span class="_ _0"></span>sts of thr<span class="_ _0"></span>ee</div><div class="t m2 x2 h7 y85 ff5 fs0 fc0 sc0 ls2a ws6c">steps. The<span class="_ _0"></span> first step<span class="_ _0"></span> is the three-<span class="_ _0"></span>byte load se<span class="_ _0"></span>quence for</div><div class="t m2 x2 h7 y86 ff5 fs0 fc0 sc0 ls38 ws6d">Soft<span class="_ _1"></span>war<span class="_ _1"></span>e Da<span class="_ _1"></span>ta Pr<span class="_ _1"></span>otec<span class="_ _1"></span>tion.<span class="_ _1"></span> The<span class="_ _1"></span> second<span class="_ _1"></span> step<span class="_ _1"></span> is t<span class="_ _1"></span>o l<span class="_ _1"></span>oad w<span class="_ _1"></span>ord</div><div class="t m2 x2 h7 y87 ff5 fs0 fc0 sc0 ls46 ws6e">address<span class="_ _0"></span> and word d<span class="_ _0"></span>ata. Dur<span class="_ _0"></span>ing t<span class="_ _0"></span>he Word-Program ope<span class="_ _0"></span>ra-</div><div class="t m2 x2 h7 y88 ff5 fs0 fc0 sc0 ls2c ws2b">tion, the ad<span class="_ _0"></span>dress<span class="_ _0"></span>es are la<span class="_ _0"></span>tched on the<span class="_ _0"></span> f<span class="_ _1"></span>allin<span class="_ _0"></span>g edge of<span class="_ _0"></span> either</div><div class="t m2 x2 h7 y89 ff5 fs0 fc0 sc0 ls27 ws31">CE# or <span class="_ _0"></span>WE#, wh<span class="_ _0"></span>ichev<span class="_ _1"></span>er occur<span class="_ _0"></span>s last. <span class="_ _0"></span>The dat<span class="_ _0"></span>a is la<span class="_ _0"></span>tche<span class="_ _0"></span>d on</div><div class="t m2 x2 h7 y8a ff5 fs0 fc0 sc0 ls27 ws6f">the r<span class="_ _0"></span>ising<span class="_ _0"></span> edge of ei<span class="_ _0"></span>ther CE#<span class="_ _0"></span> or WE#<span class="_ _0"></span>, whichever occurs</div><div class="t m2 x2 h7 y8b ff5 fs0 fc0 sc0 ls2c ws69">first. Th<span class="_ _0"></span>e third st<span class="_ _0"></span>ep is the int<span class="_ _0"></span>er<span class="_ _0"></span>nal Pro<span class="_ _0"></span>gram operatio<span class="_ _0"></span>n which</div><div class="t m2 x2 h7 y8c ff5 fs0 fc0 sc0 ls28 ws70">is init<span class="_ _0"></span>iated a<span class="_ _0"></span>fter the<span class="_ _0"></span> ri<span class="_ _0"></span>sing edge<span class="_ _0"></span> of th<span class="_ _0"></span>e four<span class="_ _0"></span>th WE#<span class="_ _0"></span> or CE#<span class="_ _0"></span>,</div><div class="t m2 x2 h7 y8d ff5 fs0 fc0 sc0 ls26 ws71">whichever occurs fi<span class="_ _0"></span>rst. Th<span class="_ _0"></span>e Program op<span class="_ _0"></span>eratio<span class="_ _0"></span>n, once <span class="_ _0"></span>init<span class="_ _0"></span>i-</div><div class="t m2 x2 h7 y8e ff5 fs0 fc0 sc0 ls30 ws72">ated, wil<span class="_ _0"></span>l be comp<span class="_ _0"></span>leted<span class="_ _0"></span> within<span class="_ _0"></span> 20 µs. See Figu<span class="_ _0"></span>res 3 and<span class="_ _0"></span> 4</div><div class="t m2 x2 h7 y8f ff5 fs0 fc0 sc0 ls2a ws73">for WE# and C<span class="_ _0"></span>E# cont<span class="_ _0"></span>rolled<span class="_ _0"></span> Program ope<span class="_ _0"></span>ration ti<span class="_ _0"></span>ming di<span class="_ _0"></span>a-</div><div class="t m2 x2 h7 y90 ff5 fs0 fc0 sc0 ls4d ws74">gr<span class="_ _1"></span>ams a<span class="_ _1"></span>nd Fi<span class="_ _1"></span>gure 15<span class="_ _1"></span> f<span class="_ _1"></span>or f<span class="_ _1"></span>lo<span class="_ _1"></span>wcharts. D<span class="_ _1"></span>uring th<span class="_ _1"></span>e Prog<span class="_ _5"></span>ram</div><div class="t m2 x2 h7 y91 ff5 fs0 fc0 sc0 ls26 ws75">operatio<span class="_ _0"></span>n, the onl<span class="_ _0"></span>y valid reads are Data<span class="_ _0"></span># P<span class="_ _5"></span>o<span class="_ _0"></span>lling and<span class="_ _0"></span> T<span class="_ _4"></span>og-</div><div class="t m2 x2 h7 y92 ff5 fs0 fc0 sc0 ls30 ws76">gle Bit. Dur<span class="_ _0"></span>ing<span class="_ _0"></span> the inter<span class="_ _0"></span>n<span class="_ _0"></span>al Program operat<span class="_ _0"></span>ion, the hos<span class="_ _0"></span>t is</div><div class="t m2 x2 h7 y93 ff5 fs0 fc0 sc0 ls42 ws77">free to pe<span class="_ _0"></span>rform ad<span class="_ _0"></span>ditio<span class="_ _0"></span>nal task<span class="_ _0"></span>s. Any comman<span class="_ _0"></span>ds iss<span class="_ _0"></span>ued</div><div class="t m2 x2 h7 y94 ff5 fs0 fc0 sc0 ls2c ws1a">dur<span class="_ _0"></span>ing the i<span class="_ _0"></span>nter<span class="_ _0"></span>na<span class="_ _0"></span>l Program op<span class="_ _0"></span>eratio<span class="_ _0"></span>n are ign<span class="_ _0"></span>ored<span class="_ _0"></span>.</div><div class="t m2 x2 h5 y95 ff4 fs3 fc0 sc0 ls4e ws78">Sector/Block-Erase<span class="_ _1"></span> Operation</div><div class="t m2 x2 h7 y96 ff5 fs0 fc0 sc0 ls4f ws79">The <span class="_ _1"></span>Sector-<span class="_ _1"></span> (or Bl<span class="_ _1"></span>oc<span class="_ _1"></span>k-) Er<span class="_ _1"></span>ase<span class="_ _1"></span> oper<span class="_ _1"></span>ation<span class="_ _1"></span> allo<span class="_ _1"></span>ws th<span class="_ _1"></span>e syste<span class="_ _1"></span>m</div><div class="t m2 x2 h7 y97 ff5 fs0 fc0 sc0 ls2c ws7a">to erase <span class="_ _0"></span>the device on a s<span class="_ _0"></span>ector<span class="_ _0"></span>-by-sector<span class="_ _0"></span> (or block-by-</div><div class="t m2 x2 h7 y98 ff5 fs0 fc0 sc0 ls34 ws6d">block) basis. The<span class="_ _0"></span> SST3<span class="_ _0"></span>9LF/VF<span class="_ _0"></span>160 offer both<span class="_ _0"></span> Sec<span class="_ _0"></span>tor-Eras<span class="_ _0"></span>e</div><div class="t m2 x2 h7 y99 ff5 fs0 fc0 sc0 ls26 ws7b">and Block-E<span class="_ _0"></span>rase mode. The se<span class="_ _0"></span>ctor ar<span class="_ _0"></span>chitec<span class="_ _0"></span>ture is<span class="_ _0"></span> based</div><div class="t m2 x9 h7 y9a ff5 fs0 fc0 sc0 ls50 ws7c">on uni<span class="_ _1"></span>f<span class="_ _1"></span>orm sector si<span class="_ _1"></span>ze<span class="_ _1"></span> of 2 KW<span class="_ _5"></span>ord. The Blo<span class="_ _1"></span>c<span class="_ _1"></span>k-Er<span class="_ _1"></span>ase mode</div><div class="t m2 x9 h7 y9b ff5 fs0 fc0 sc0 ls39 ws7d">is base<span class="_ _0"></span>d on uni<span class="_ _0"></span>f<span class="_ _1"></span>or<span class="_ _0"></span>m block size of 32 K<span class="_ _0"></span>Word. The Sec<span class="_ _0"></span>tor-</div><div class="t m2 x9 h7 y9c ff5 fs0 fc0 sc0 ls39 ws7e">Erase ope<span class="_ _0"></span>ration is<span class="_ _0"></span> init<span class="_ _0"></span>iated<span class="_ _0"></span> b<span class="_ _1"></span>y ex<span class="_ _1"></span>ecuting<span class="_ _0"></span> a six-byte co<span class="_ _0"></span>m-</div><div class="t m2 x9 h7 y9d ff5 fs0 fc0 sc0 ls26 ws7f">mand se<span class="_ _0"></span>quence wi<span class="_ _0"></span>th Se<span class="_ _0"></span>ctor-<span class="_ _0"></span>Erase comm<span class="_ _0"></span>and (<span class="_ _0"></span>30H) an<span class="_ _0"></span>d</div><div class="t m2 x9 h7 y9e ff5 fs0 fc0 sc0 ls51 ws80">secto<span class="_ _1"></span>r addres<span class="_ _1"></span>s (SA) in th<span class="_ _1"></span>e last b<span class="_ _1"></span>us cycle<span class="_ _5"></span>. <span class="_ _0"></span>The Blo<span class="_ _1"></span>ck-E<span class="_ _1"></span>rase</div><div class="t m2 x9 h7 y9f ff5 fs0 fc0 sc0 ls36 ws81">operatio<span class="_ _0"></span>n is ini<span class="_ _0"></span>tiate<span class="_ _0"></span>d by e<span class="_ _1"></span>x<span class="_ _1"></span>ecut<span class="_ _0"></span>ing a si<span class="_ _0"></span>x-byte co<span class="_ _0"></span>mman<span class="_ _0"></span>d</div><div class="t m2 x9 h7 ya0 ff5 fs0 fc0 sc0 ls35 ws82">sequenc<span class="_ _0"></span>e with <span class="_ _0"></span>Block-Eras<span class="_ _0"></span>e comma<span class="_ _0"></span>nd (50<span class="_ _0"></span>H) and block</div><div class="t m2 x9 h7 ya1 ff5 fs0 fc0 sc0 ls52 ws83">address <span class="_ _1"></span>(BA) in<span class="_ _1"></span> the last b<span class="_ _5"></span>us cycle<span class="_ _1"></span>. The sect<span class="_ _1"></span>or or b<span class="_ _5"></span>lock</div><div class="t m2 x9 h7 ya2 ff5 fs0 fc0 sc0 ls30 ws84">addres<span class="_ _0"></span>s is latc<span class="_ _0"></span>hed o<span class="_ _0"></span>n the falling ed<span class="_ _0"></span>ge of the s<span class="_ _0"></span>ixt<span class="_ _0"></span>h WE#</div><div class="t m2 x9 h7 ya3 ff5 fs0 fc0 sc0 ls26 ws75">pulse, whil<span class="_ _0"></span>e the co<span class="_ _0"></span>mmand (3<span class="_ _0"></span>0H or 50H)<span class="_ _0"></span> is latc<span class="_ _0"></span>hed on the</div><div class="t m2 x9 h7 ya4 ff5 fs0 fc0 sc0 ls42 ws77">risi<span class="_ _0"></span>ng edg<span class="_ _0"></span>e of th<span class="_ _0"></span>e sixt<span class="_ _0"></span>h WE# p<span class="_ _0"></span>ulse. The<span class="_ _0"></span> inter<span class="_ _0"></span>n<span class="_ _0"></span>al Erase</div><div class="t m2 x9 h7 ya5 ff5 fs0 fc0 sc0 ls30 ws85">operatio<span class="_ _0"></span>n begins<span class="_ _0"></span> after <span class="_ _0"></span>the si<span class="_ _0"></span>xth WE<span class="_ _0"></span># puls<span class="_ _0"></span>e. The End<span class="_ _0"></span>-of-</div><div class="t m2 x9 h7 ya6 ff5 fs0 fc0 sc0 ls26 ws86">Erase op<span class="_ _0"></span>eration c<span class="_ _0"></span>an be deter<span class="_ _0"></span>m<span class="_ _0"></span>ined u<span class="_ _0"></span>sing ei<span class="_ _0"></span>ther Data<span class="_ _0"></span>#</div><div class="t m2 x9 h7 ya7 ff5 fs0 fc0 sc0 ls26 ws87">P<span class="_ _5"></span>o<span class="_ _0"></span>lling or<span class="_ _0"></span> T<span class="_ _4"></span>oggle Bit method<span class="_ _0"></span>s. See Figures<span class="_ _0"></span> 8 and 9 f<span class="_ _1"></span>or tim-</div><div class="t m2 x9 h7 ya8 ff5 fs0 fc0 sc0 ls26 ws88">ing wavef<span class="_ _5"></span>or<span class="_ _0"></span>ms. A<span class="_ _0"></span>ny comman<span class="_ _0"></span>ds iss<span class="_ _0"></span>ued d<span class="_ _0"></span>uring<span class="_ _0"></span> the S<span class="_ _0"></span>ector-</div><div class="t m2 x9 h7 ya9 ff5 fs0 fc0 sc0 ls2c ws1a">or Blo<span class="_ _0"></span>ck-Erase operat<span class="_ _0"></span>ion are<span class="_ _0"></span> ignor<span class="_ _0"></span>ed.</div><div class="t m2 x9 h5 yaa ff4 fs3 fc0 sc0 ls53 ws89">Chip-Erase Oper<span class="_ _1"></span>ation</div><div class="t m2 x9 h7 yab ff5 fs0 fc0 sc0 ls54 ws8a">The S<span class="_ _1"></span>ST39L<span class="_ _1"></span>F/VF1<span class="_ _1"></span>60 pro<span class="_ _1"></span>vid<span class="_ _1"></span>e a Chip<span class="_ _1"></span>-Era<span class="_ _1"></span>se oper<span class="_ _1"></span>atio<span class="_ _1"></span>n,</div><div class="t m2 x9 h7 yac ff5 fs0 fc0 sc0 ls27 ws8b">which al<span class="_ _0"></span>lows the user to era<span class="_ _0"></span>se the enti<span class="_ _0"></span>re memor<span class="_ _0"></span>y ar<span class="_ _0"></span>ra<span class="_ _1"></span>y to</div><div class="t m2 x9 h7 yad ff5 fs0 fc0 sc0 ls46 ws2">the <span class="_ _0"></span><span class="ff2 ls3">“<span class="ff5">1<span class="_ _5"></span><span class="ff2">”<span class="ff5 ls41 ws8c"> <span class="_ _1"></span>state<span class="_ _1"></span>. Th<span class="_ _1"></span>is is us<span class="_ _1"></span>efu<span class="_ _1"></span>l when<span class="_ _1"></span> the en<span class="_ _1"></span>tire<span class="_ _1"></span> de<span class="_ _5"></span>vice must<span class="_ _1"></span> be</span></span></span></span></div><div class="t m2 x9 h7 yae ff5 fs0 fc0 sc0 ls2e ws20">quickly e<span class="_ _0"></span>rased.</div><div class="t m2 x9 h7 yaf ff5 fs0 fc0 sc0 ls4f ws8d">The Chi<span class="_ _1"></span>p-Er<span class="_ _1"></span>ase ope<span class="_ _1"></span>rat<span class="_ _1"></span>ion is ini<span class="_ _1"></span>tiate<span class="_ _1"></span>d by e<span class="_ _5"></span>x<span class="_ _1"></span>ecutin<span class="_ _1"></span>g a six-</div><div class="t m2 x9 h7 yb0 ff5 fs0 fc0 sc0 ls35 ws8e">byte comma<span class="_ _0"></span>nd seq<span class="_ _0"></span>uence w<span class="_ _0"></span>ith C<span class="_ _0"></span>hip-Eras<span class="_ _0"></span>e co<span class="_ _0"></span>mmand (<span class="_ _0"></span>10H)</div><div class="t m2 x9 h7 yb1 ff5 fs0 fc0 sc0 ls2b ws8f">at addr<span class="_ _0"></span>ess 55<span class="_ _0"></span>55H in<span class="_ _0"></span> the las<span class="_ _0"></span>t byte se<span class="_ _0"></span>quence. T<span class="_ _0"></span>he Erase</div><div class="t m2 x9 h7 yb2 ff5 fs0 fc0 sc0 ls35 ws90">operatio<span class="_ _0"></span>n begins wi<span class="_ _0"></span>th the ri<span class="_ _0"></span>sing edg<span class="_ _0"></span>e of the sixt<span class="_ _0"></span>h WE# or</div><div class="t m2 x9 h7 yb3 ff5 fs0 fc0 sc0 ls46 ws91">CE#, whic<span class="_ _0"></span>he<span class="_ _1"></span>ver occurs firs<span class="_ _0"></span>t. Dur<span class="_ _0"></span>ing the Era<span class="_ _0"></span>se operation<span class="_ _0"></span>,</div><div class="t m2 x9 h7 yb4 ff5 fs0 fc0 sc0 ls35 wsd">the only<span class="_ _0"></span> v<span class="_ _1"></span>alid r<span class="_ _0"></span>ead is T<span class="_ _4"></span>oggl<span class="_ _0"></span>e Bit or<span class="_ _0"></span> Data# P<span class="_ _1"></span>olling.<span class="_ _0"></span> See T<span class="_ _4"></span>able</div><div class="t m2 x9 h7 yb5 ff5 fs0 fc0 sc0 ls28 ws92">4 for the com<span class="_ _0"></span>mand s<span class="_ _0"></span>equence, Fi<span class="_ _0"></span>gure 7 <span class="_ _0"></span>f<span class="_ _1"></span>or ti<span class="_ _0"></span>ming di<span class="_ _0"></span>agram,</div><div class="t m2 x9 h7 yb6 ff5 fs0 fc0 sc0 ls26 ws93">and Fi<span class="_ _0"></span>gure 1<span class="_ _0"></span>8 for the flowcha<span class="_ _0"></span>r<span class="_ _0"></span>t. <span class="_ _0"></span>Any comm<span class="_ _0"></span>ands<span class="_ _0"></span> issued <span class="_ _0"></span>dur-</div><div class="t m2 x9 h7 yb7 ff5 fs0 fc0 sc0 ls30 ws33">ing t<span class="_ _0"></span>he Chip-E<span class="_ _0"></span>rase ope<span class="_ _0"></span>ration ar<span class="_ _0"></span>e ignor<span class="_ _0"></span>ed.</div><div class="t m2 x9 h5 yb8 ff4 fs3 fc0 sc0 ls55 ws94">Write Opera<span class="_ _1"></span>tion Status Dete<span class="_ _1"></span>ction</div><div class="t m2 x9 h7 yb9 ff5 fs0 fc0 sc0 ls38 ws95">The SST<span class="_ _1"></span>39LF/<span class="_ _1"></span>VF16<span class="_ _1"></span>0 prov<span class="_ _1"></span>ide tw<span class="_ _1"></span>o soft<span class="_ _1"></span>wa<span class="_ _1"></span>re means to</div><div class="t m2 x9 h7 yba ff5 fs0 fc0 sc0 ls27 ws96">detect <span class="_ _0"></span>the com<span class="_ _0"></span>pletion<span class="_ _0"></span> of a <span class="_ _0"></span>Wr<span class="_ _0"></span>ite (P<span class="_ _0"></span>rogram or E<span class="_ _0"></span>rase) cyc<span class="_ _0"></span>le,</div><div class="t m2 x9 h7 ybb ff5 fs0 fc0 sc0 ls42 ws97">in o<span class="_ _0"></span>rder to<span class="_ _0"></span> optim<span class="_ _0"></span>ize the <span class="_ _0"></span>syste<span class="_ _0"></span>m wr<span class="_ _0"></span>ite cy<span class="_ _0"></span>cle ti<span class="_ _0"></span>me. The <span class="_ _0"></span>soft-</div><div class="t m2 x9 h7 ybc ff5 fs0 fc0 sc0 ls27 ws98">ware detect<span class="_ _0"></span>ion inc<span class="_ _0"></span>ludes two s<span class="_ _0"></span>tatus bi<span class="_ _0"></span>ts: Data#<span class="_ _0"></span> P<span class="_ _5"></span>oll<span class="_ _0"></span>ing</div><div class="t m2 x9 h7 ybd ff5 fs0 fc0 sc0 ls56 ws2">(DQ</div><div class="t m2 x17 h8 ybe ff5 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m2 x18 h7 ybf ff5 fs0 fc0 sc0 ls27 ws99">) and T<span class="_ _4"></span>oggl<span class="_ _0"></span>e Bit (D<span class="_ _0"></span>Q</div><div class="t m2 x19 h8 ybe ff5 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m2 x1a h7 ybf ff5 fs0 fc0 sc0 ls4a ws9a">). The<span class="_ _0"></span> End-of-<span class="_ _0"></span>Wr<span class="_ _0"></span>ite dete<span class="_ _0"></span>ctio<span class="_ _0"></span>n</div><div class="t m2 x9 h7 yc0 ff5 fs0 fc0 sc0 ls26 ws9b">mode is en<span class="_ _0"></span>abled after the<span class="_ _0"></span> ris<span class="_ _0"></span>ing edge of W<span class="_ _0"></span>E#, whic<span class="_ _0"></span>h ini-</div><div class="t m2 x9 h7 yc1 ff5 fs0 fc0 sc0 ls27 ws31">tiates <span class="_ _0"></span>the inter<span class="_ _0"></span>n<span class="_ _0"></span>al Pro<span class="_ _0"></span>gram or Erase o<span class="_ _0"></span>peration.</div><div class="t m2 x9 h7 yc2 ff5 fs0 fc0 sc0 ls2b ws9c">The act<span class="_ _0"></span>ual comp<span class="_ _0"></span>leti<span class="_ _0"></span>on of the no<span class="_ _0"></span>nv<span class="_ _5"></span>o<span class="_ _0"></span>lati<span class="_ _0"></span>le write<span class="_ _0"></span> is asyn<span class="_ _0"></span>chro-</div><div class="t m2 x9 h7 yc3 ff5 fs0 fc0 sc0 ls2f ws9d">nous wi<span class="_ _0"></span>th the sy<span class="_ _0"></span>stem; th<span class="_ _0"></span>erefore, either a D<span class="_ _0"></span>ata# P<span class="_ _1"></span>olling<span class="_ _0"></span> or</div><div class="t m2 x9 h7 yc4 ff5 fs0 fc0 sc0 ls35 ws9e">T<span class="_ _4"></span>oggle B<span class="_ _0"></span>it read may be si<span class="_ _0"></span>multaneou<span class="_ _0"></span>s with th<span class="_ _0"></span>e compl<span class="_ _0"></span>etio<span class="_ _0"></span>n</div><div class="t m2 x9 h7 yc5 ff5 fs0 fc0 sc0 ls57 ws9f">of the w<span class="_ _1"></span>rite cycle.<span class="_ _1"></span> If this o<span class="_ _1"></span>ccurs<span class="_ _1"></span>, the system m<span class="_ _1"></span>a<span class="_ _1"></span>y possib<span class="_ _1"></span>ly</div><div class="t m2 x9 h7 yc6 ff5 fs0 fc0 sc0 ls42 ws57">get a<span class="_ _0"></span>n erron<span class="_ _0"></span>eous <span class="_ _0"></span>resul<span class="_ _0"></span>t, i.e., valid<span class="_ _0"></span> data<span class="_ _0"></span> may appear<span class="_ _0"></span> to <span class="_ _0"></span>con-</div><div class="t m2 x9 h7 yc7 ff5 fs0 fc0 sc0 ls4b wsa0">flict with e<span class="_ _0"></span>ither DQ</div><div class="t m2 xd h8 yc8 ff5 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m2 x1b h7 yc9 ff5 fs0 fc0 sc0 ls58 wsa1"> or DQ</div><div class="t m2 x19 h8 yc8 ff5 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m2 x1a h7 yc9 ff5 fs0 fc0 sc0 ls27 wsa2">. In orde<span class="_ _0"></span>r to prev<span class="_ _1"></span>ent spur<span class="_ _0"></span>ious</div><div class="t m2 x9 h7 yca ff5 fs0 fc0 sc0 ls2b wsa3">rejec<span class="_ _0"></span>tion, i<span class="_ _0"></span>f an <span class="_ _0"></span>errone<span class="_ _0"></span>ous r<span class="_ _0"></span>esult o<span class="_ _0"></span>ccurs, the<span class="_ _0"></span> soft<span class="_ _0"></span>ware rout<span class="_ _0"></span>ine</div><div class="t m2 x9 h7 ycb ff5 fs0 fc0 sc0 ls25 wsa4">shou<span class="_ _0"></span>ld inc<span class="_ _0"></span>lude <span class="_ _0"></span>a loop to<span class="_ _0"></span> rea<span class="_ _0"></span>d the <span class="_ _0"></span>access<span class="_ _0"></span>ed l<span class="_ _0"></span>ocatio<span class="_ _0"></span>n an</div><div class="t m2 x9 h7 ycc ff5 fs0 fc0 sc0 ls32 wsa5">additio<span class="_ _0"></span>nal two (2) tim<span class="_ _0"></span>es. If both rea<span class="_ _0"></span>ds are valid, the<span class="_ _0"></span>n the</div><div class="t m2 x9 h7 ycd ff5 fs0 fc0 sc0 ls2a ws27">device has co<span class="_ _0"></span>mpleted <span class="_ _0"></span>the W<span class="_ _0"></span>rit<span class="_ _0"></span>e cycle, oth<span class="_ _0"></span>erwise<span class="_ _0"></span> the rejec<span class="_ _0"></span>-</div><div class="t m2 x9 h7 yce ff5 fs0 fc0 sc0 ls26 ws4e">tion is valid.</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><div class="d m1"></div><div class="d m1"></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><div class="d m1"></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/bg3.jpg"><div class="t m0 x2 h7 y1 ff5 fs0 fc0 sc0 ls15 ws31">Data Sheet</div><div class="t m0 x2 ha y64 ff4 fs6 fc0 sc0 ls3d ws51">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m0 x2 ha y65 ff4 fs6 fc0 sc0 ls59 wsa6">SST39LF160 / SST39V<span class="_ _0"></span>F160</div><div class="t m0 xf h9 y63 ff5 fs5 fc0 sc0 ls3 ws2">3</div><div class="t m0 x2 h3 y2 ff5 fs1 fc0 sc0 ls3f ws52">©<span class="_ _0"></span>2001 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>6/01<span class="_ _a"> </span>399</span></div><div class="t m0 x2 h5 ycf ff4 fs3 fc0 sc0 ls5a wsa7">Data# Polling (DQ</div><div class="t m0 x1c hb yd0 ff4 fs5 fc0 sc0 ls3 ws2">7</div><div class="t m0 xe h5 ycf ff4 fs3 fc0 sc0 ls3 ws2">)</div><div class="t m0 x2 h7 yd1 ff5 fs0 fc0 sc0 ls36 wsa8">When<span class="_ _0"></span> the S<span class="_ _0"></span>ST39L<span class="_ _0"></span>F/VF1<span class="_ _0"></span>60 a<span class="_ _0"></span>re in<span class="_ _0"></span> the i<span class="_ _0"></span>nter<span class="_ _0"></span>nal<span class="_ _0"></span> Pro<span class="_ _0"></span>gram</div><div class="t m0 x2 h7 yd2 ff5 fs0 fc0 sc0 ls30 wsa9">operatio<span class="_ _0"></span>n, any atte<span class="_ _0"></span>mpt to re<span class="_ _0"></span>ad DQ</div><div class="t m0 x1d h8 yd3 ff5 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x1e h7 yd4 ff5 fs0 fc0 sc0 ls2b wsaa"> will pr<span class="_ _0"></span>oduce<span class="_ _0"></span> the com-</div><div class="t m0 x2 h7 yd5 ff5 fs0 fc0 sc0 ls2c wsab">plement<span class="_ _0"></span> of the tr<span class="_ _0"></span>ue data. O<span class="_ _0"></span>nce the Pr<span class="_ _0"></span>ogram operation is</div><div class="t m0 x2 h7 yd6 ff5 fs0 fc0 sc0 ls5b wsac">comp<span class="_ _0"></span>leted<span class="_ _0"></span>, DQ</div><div class="t m0 x1f h8 yd7 ff5 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x20 h7 yd8 ff5 fs0 fc0 sc0 ls2a ws4f"> will prod<span class="_ _0"></span>uce tr<span class="_ _0"></span>ue data<span class="_ _0"></span>. The device is then</div><div class="t m0 x2 h7 yd9 ff5 fs0 fc0 sc0 ls26 wsad">ready <span class="_ _0"></span>f<span class="_ _1"></span>or the<span class="_ _0"></span> next operation. D<span class="_ _0"></span>uri<span class="_ _0"></span>ng int<span class="_ _0"></span>er<span class="_ _0"></span>nal Erase<span class="_ _0"></span> opera-</div><div class="t m0 x2 h7 yda ff5 fs0 fc0 sc0 ls4b wsae">tion, any a<span class="_ _0"></span>ttempt to<span class="_ _0"></span> read DQ</div><div class="t m0 x21 h8 ydb ff5 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x22 h7 ydc ff5 fs0 fc0 sc0 ls2a wsaf"> will pro<span class="_ _0"></span>duce <span class="_ _0"></span>a <span class="ff2 ls3 ws2">‘<span class="_ _1"></span><span class="ff5">0<span class="_ _1"></span><span class="ff2">’<span class="_ _1"></span><span class="ff5 ls5c wsb0">. Once th<span class="_ _0"></span>e</span></span></span></span></div><div class="t m0 x2 h7 ydd ff5 fs0 fc0 sc0 ls28 wsb1">inter<span class="_ _0"></span>nal<span class="_ _0"></span> Erase operati<span class="_ _0"></span>on is compl<span class="_ _0"></span>eted, DQ</div><div class="t m0 x23 h8 yde ff5 fs4 fc0 sc0 ls3 ws2">7</div><div class="t m0 x24 h7 ydf ff5 fs0 fc0 sc0 ls47 wsb2"> will <span class="_ _1"></span>prod<span class="_ _1"></span>uce a</div><div class="t m0 x2 h7 ye0 ff2 fs0 fc0 sc0 ls3 ws2">‘<span class="_ _5"></span><span class="ff5">1<span class="ff2">’<span class="_ _5"></span><span class="ff5 ls35 wsb3">.<span class="_ _0"></span> The D<span class="_ _0"></span>ata# P<span class="_ _1"></span>olling i<span class="_ _0"></span>s valid after<span class="_ _0"></span> the r<span class="_ _0"></span>ising e<span class="_ _0"></span>dge of four<span class="_ _0"></span>t<span class="_ _0"></span>h</span></span></span></div><div class="t m0 x2 h7 ye1 ff5 fs0 fc0 sc0 ls4a wsb4">WE# (or<span class="_ _0"></span> CE#) puls<span class="_ _0"></span>e f<span class="_ _1"></span>or Pr<span class="_ _0"></span>ogram operatio<span class="_ _0"></span>n. F<span class="_ _1"></span>or Sect<span class="_ _0"></span>or-,</div><div class="t m0 x2 h7 ye2 ff5 fs0 fc0 sc0 ls2c ws1a">Block- or C<span class="_ _0"></span>hip-Eras<span class="_ _0"></span>e, the Data# P<span class="_ _1"></span>oll<span class="_ _0"></span>ing is<span class="_ _0"></span> v<span class="_ _1"></span>alid a<span class="_ _0"></span>fter the<span class="_ _0"></span> ris<span class="_ _0"></span>-</div><div class="t m0 x2 h7 ye3 ff5 fs0 fc0 sc0 ls42 wsb5">ing ed<span class="_ _0"></span>ge of sixt<span class="_ _0"></span>h WE# (or CE<span class="_ _0"></span>#) puls<span class="_ _0"></span>e. See Figur<span class="_ _0"></span>e 5 for</div><div class="t m0 x2 h7 ye4 ff5 fs0 fc0 sc0 ls35 ws9">Data# P<span class="_ _1"></span>oll<span class="_ _0"></span>ing tim<span class="_ _0"></span>ing dia<span class="_ _0"></span>gram and F<span class="_ _0"></span>igure 1<span class="_ _0"></span>6 f<span class="_ _1"></span>or a fl<span class="_ _0"></span>owchar<span class="_ _9"></span>t.</div><div class="t m0 x2 h5 ye5 ff4 fs3 fc0 sc0 ls5d wsb6">Toggle Bit (DQ</div><div class="t m0 x25 hb ye6 ff4 fs5 fc0 sc0 ls3 ws2">6</div><div class="t m0 x26 h5 ye5 ff4 fs3 fc0 sc0 ls3 ws2">)</div><div class="t m0 x2 h7 ye7 ff5 fs0 fc0 sc0 ls2c wsb7">Duri<span class="_ _0"></span>ng the inte<span class="_ _0"></span>r<span class="_ _0"></span>nal Pro<span class="_ _0"></span>gram or Erase ope<span class="_ _0"></span>ration, any co<span class="_ _0"></span>n-</div><div class="t m0 x2 h7 ye8 ff5 fs0 fc0 sc0 ls5e wsb8">secutive attemp<span class="_ _0"></span>ts to r<span class="_ _0"></span>ead DQ</div><div class="t m0 x22 h8 ye9 ff5 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m0 x27 h7 yea ff5 fs0 fc0 sc0 ls42 wsb9"> will<span class="_ _0"></span> produ<span class="_ _0"></span>ce a<span class="_ _0"></span>lter<span class="_ _0"></span>na<span class="_ _0"></span>ting 1s</div><div class="t m0 x2 h7 yeb ff5 fs0 fc0 sc0 ls27 wsba">and 0s, i.e., toggli<span class="_ _0"></span>ng between 1 an<span class="_ _0"></span>d 0. When<span class="_ _0"></span> the inter<span class="_ _0"></span>nal</div><div class="t m0 x2 h7 yec ff5 fs0 fc0 sc0 ls27 wsaf">Program or<span class="_ _0"></span> Erase op<span class="_ _0"></span>eratio<span class="_ _0"></span>n is com<span class="_ _0"></span>plete<span class="_ _0"></span>d, the DQ</div><div class="t m0 x28 h8 yed ff5 fs4 fc0 sc0 ls3 ws2">6</div><div class="t m0 x29 h7 yee ff5 fs0 fc0 sc0 ls5f ws45"> bit w<span class="_ _1"></span>ill</div><div class="t m0 x2 h7 yef ff5 fs0 fc0 sc0 ls30 wsbb">stop<span class="_ _0"></span> togglin<span class="_ _0"></span>g. The<span class="_ _0"></span> device is the<span class="_ _0"></span>n ready<span class="_ _0"></span> for the next opera-</div><div class="t m0 x2 h7 yf0 ff5 fs0 fc0 sc0 ls27 wsba">tion. T<span class="_ _0"></span>he T<span class="_ _4"></span>oggle <span class="_ _0"></span>Bit is<span class="_ _0"></span> valid after t<span class="_ _0"></span>he r<span class="_ _0"></span>ising <span class="_ _0"></span>edge of <span class="_ _0"></span>f<span class="_ _1"></span>our<span class="_ _9"></span>th</div><div class="t m0 x2 h7 yf1 ff5 fs0 fc0 sc0 ls4a wsb4">WE# (or<span class="_ _0"></span> CE#) puls<span class="_ _0"></span>e f<span class="_ _1"></span>or Pr<span class="_ _0"></span>ogram operatio<span class="_ _0"></span>n. F<span class="_ _1"></span>or Sect<span class="_ _0"></span>or-,</div><div class="t m0 x2 h7 yf2 ff5 fs0 fc0 sc0 ls35 wsbc">Block- or C<span class="_ _0"></span>hip-Eras<span class="_ _0"></span>e, the T<span class="_ _4"></span>oggle Bi<span class="_ _0"></span>t is valid after<span class="_ _0"></span> the r<span class="_ _0"></span>isin<span class="_ _0"></span>g</div><div class="t m0 x2 h7 yf3 ff5 fs0 fc0 sc0 ls35 ws69">edge of six<span class="_ _0"></span>th WE# (or CE#)<span class="_ _0"></span> pulse. See Figure<span class="_ _0"></span> 6 f<span class="_ _1"></span>or T<span class="_ _4"></span>oggle</div><div class="t m0 x2 h7 yf4 ff5 fs0 fc0 sc0 ls60 wsbd">Bit<span class="_ _1"></span> timi<span class="_ _1"></span>ng di<span class="_ _1"></span>agr<span class="_ _1"></span>am an<span class="_ _1"></span>d Figu<span class="_ _1"></span>re 16<span class="_ _1"></span> f<span class="_ _1"></span>or a<span class="_ _1"></span> flo<span class="_ _1"></span>wcha<span class="_ _1"></span>r<span class="_ _0"></span>t.</div><div class="t m0 x2 h5 yf5 ff4 fs3 fc0 sc0 ls5a wsa7">Data Protection</div><div class="t m0 x2 h7 yf6 ff5 fs0 fc0 sc0 ls30 wsbe">The SS<span class="_ _0"></span>T39LF/V<span class="_ _0"></span>F160 pr<span class="_ _0"></span>ovide bot<span class="_ _0"></span>h hardware<span class="_ _0"></span> and so<span class="_ _0"></span>ftware</div><div class="t m0 x2 h7 yf7 ff5 fs0 fc0 sc0 ls32 ws0">features to pro<span class="_ _0"></span>tect nonvolatile da<span class="_ _0"></span>ta from<span class="_ _0"></span> inad<span class="_ _0"></span>v<span class="_ _1"></span>er<span class="_ _0"></span>ten<span class="_ _0"></span>t wr<span class="_ _0"></span>ites.</div><div class="t m0 x9 h5 ycf ff4 fs3 fc0 sc0 ls61 wsbf">Hardware Data <span class="_ _1"></span>Protection</div><div class="t m0 x9 h7 yd1 ff5 fs0 fc0 sc0 ls39 ws44">Noise/G<span class="_ _0"></span>litch<span class="_ _0"></span> Prote<span class="_ _0"></span>ctio<span class="_ _0"></span>n:<span class="ls4d"> A WE# or <span class="_ _1"></span>CE# <span class="_ _1"></span>pulse <span class="_ _1"></span>of l<span class="_ _1"></span>ess th<span class="_ _1"></span>an 5</span></div><div class="t m0 x9 h7 yd2 ff5 fs0 fc0 sc0 ls34 ws16">ns will<span class="_ _0"></span> not <span class="_ _0"></span>initiat<span class="_ _0"></span>e a wr<span class="_ _0"></span>it<span class="_ _0"></span>e cyc<span class="_ _0"></span>le.</div><div class="t m0 x9 h7 yf8 ff5 fs0 fc0 sc0 ls3 ws2">V</div><div class="t m0 x2a h8 yf9 ff5 fs4 fc0 sc0 ls43 ws2">DD</div><div class="t m0 x2b h7 yfa ff5 fs0 fc0 sc0 ls62 wsc0"> P<span class="_ _5"></span>ower Up/Down D<span class="_ _0"></span>etection:<span class="ls4a wsc1"> T<span class="_ _0"></span>he Wri<span class="_ _0"></span>te operatio<span class="_ _0"></span>n is</span></div><div class="t m0 x9 h7 yfb ff5 fs0 fc0 sc0 ls27 ws31">inhibi<span class="_ _0"></span>ted when <span class="_ _0"></span>V</div><div class="t m0 xc h8 y6e ff5 fs4 fc0 sc0 ls43 ws2">DD</div><div class="t m0 xd h7 y6f ff5 fs0 fc0 sc0 ls36 wsc2"> is le<span class="_ _0"></span>ss than<span class="_ _0"></span> 1.5V<span class="_ _4"></span>.</div><div class="t m0 x9 h7 yfc ff5 fs0 fc0 sc0 ls2b wsc3">Wr<span class="_ _0"></span>ite In<span class="_ _0"></span>hibit Mo<span class="_ _0"></span>de:</div><div class="t m0 x2c h7 ydc ff5 fs0 fc0 sc0 ls32 wsa5"> F<span class="_ _1"></span>orcing<span class="_ _0"></span> OE# low<span class="_ _1"></span>, CE# high,<span class="_ _0"></span> or WE<span class="_ _0"></span>#</div><div class="t m0 x9 h7 ydd ff5 fs0 fc0 sc0 ls30 wsc4">high will<span class="_ _0"></span> inhibi<span class="_ _0"></span>t the Wr<span class="_ _0"></span>ite ope<span class="_ _0"></span>ration. Thi<span class="_ _0"></span>s prev<span class="_ _1"></span>ents inad<span class="_ _0"></span>v<span class="_ _1"></span>er<span class="_ _9"></span>t-</div><div class="t m0 x9 h7 yfd ff5 fs0 fc0 sc0 ls63 wsc5">ent w<span class="_ _1"></span>rites du<span class="_ _1"></span>ring po<span class="_ _1"></span>we<span class="_ _1"></span>r-up o<span class="_ _1"></span>r po<span class="_ _1"></span>wer-<span class="_ _1"></span>do<span class="_ _1"></span>wn.</div><div class="t m0 x9 h5 yfe ff4 fs3 fc0 sc0 ls64 wsc6">Software Data Protection (SDP)</div><div class="t m0 x9 h7 yff ff5 fs0 fc0 sc0 ls65 wsc7">The SS<span class="_ _1"></span>T39LF/<span class="_ _1"></span>VF16<span class="_ _1"></span>0 pro<span class="_ _1"></span>vid<span class="_ _1"></span>e the JEDE<span class="_ _1"></span>C appr<span class="_ _1"></span>ov<span class="_ _5"></span>ed Soft-</div><div class="t m0 x9 h7 y100 ff5 fs0 fc0 sc0 ls28 ws2f">ware Data P<span class="_ _0"></span>rotect<span class="_ _0"></span>ion sche<span class="_ _0"></span>me for all da<span class="_ _0"></span>ta alteratio<span class="_ _0"></span>n ope<span class="_ _0"></span>ra-</div><div class="t m0 x9 h7 y101 ff5 fs0 fc0 sc0 ls42 wsc8">tions, i.e., Pr<span class="_ _0"></span>ogram and E<span class="_ _0"></span>rase. Any Pr<span class="_ _0"></span>ogram operat<span class="_ _0"></span>ion</div><div class="t m0 x9 h7 y102 ff5 fs0 fc0 sc0 ls26 wsc9">requir<span class="_ _0"></span>es the incl<span class="_ _0"></span>usion of the<span class="_ _0"></span> three-byte s<span class="_ _0"></span>equence. Th<span class="_ _0"></span>e</div><div class="t m0 x9 h7 y103 ff5 fs0 fc0 sc0 ls26 ws7b">three-<span class="_ _0"></span>byte load se<span class="_ _0"></span>quence i<span class="_ _0"></span>s used<span class="_ _0"></span> to initi<span class="_ _0"></span>ate the<span class="_ _0"></span> Program</div><div class="t m0 x9 h7 y104 ff5 fs0 fc0 sc0 ls35 wsca">operatio<span class="_ _0"></span>n, providing op<span class="_ _0"></span>timal pr<span class="_ _0"></span>otecti<span class="_ _0"></span>on from in<span class="_ _0"></span>adver<span class="_ _0"></span>tent</div><div class="t m0 x9 h7 y105 ff5 fs0 fc0 sc0 ls30 wscb">Wr<span class="_ _0"></span>ite op<span class="_ _0"></span>erations, e.g., d<span class="_ _0"></span>uri<span class="_ _0"></span>ng the sy<span class="_ _0"></span>stem power-<span class="_ _0"></span>up or</div><div class="t m0 x9 h7 y106 ff5 fs0 fc0 sc0 ls2d wscc">po<span class="_ _1"></span>wer-<span class="_ _1"></span>do<span class="_ _1"></span>wn. An<span class="_ _5"></span>y Erase ope<span class="_ _1"></span>rati<span class="_ _1"></span>on req<span class="_ _1"></span>uires<span class="_ _1"></span> the incl<span class="_ _1"></span>usion of</div><div class="t m0 x9 h7 y107 ff5 fs0 fc0 sc0 ls31 wscd">six-<span class="_ _0"></span>b<span class="_ _1"></span>yte<span class="_ _0"></span> sequenc<span class="_ _0"></span>e. These device<span class="_ _0"></span>s are sh<span class="_ _0"></span>ipped<span class="_ _0"></span> with th<span class="_ _0"></span>e</div><div class="t m0 x9 h7 y108 ff5 fs0 fc0 sc0 ls2c wsce">Software Da<span class="_ _0"></span>ta Protec<span class="_ _0"></span>tion pe<span class="_ _0"></span>rm<span class="_ _0"></span>anently<span class="_ _0"></span> enabled. Se<span class="_ _0"></span>e T<span class="_ _4"></span>able</div><div class="t m0 x9 h7 y109 ff5 fs0 fc0 sc0 ls2c wscf">4 for the specifi<span class="_ _0"></span>c software<span class="_ _0"></span> command<span class="_ _0"></span> codes. Du<span class="_ _0"></span>ring S<span class="_ _0"></span>DP</div><div class="t m0 x9 h7 y10a ff5 fs0 fc0 sc0 ls27 wsd0">comman<span class="_ _0"></span>d seq<span class="_ _0"></span>uence, inv<span class="_ _1"></span>alid c<span class="_ _0"></span>ommands<span class="_ _0"></span> will a<span class="_ _0"></span>bor<span class="_ _0"></span>t th<span class="_ _0"></span>e</div><div class="t m0 x9 h7 y10b ff5 fs0 fc0 sc0 ls4b ws65">device to read mode withi<span class="_ _0"></span>n T</div><div class="t m0 x1a h8 y10c ff5 fs4 fc0 sc0 ls43 ws2">RC</div><div class="t m0 x2d h7 y10d ff5 fs0 fc0 sc0 ls66 wsd1">. The co<span class="_ _1"></span>ntent<span class="_ _1"></span>s of DQ</div><div class="t m0 x2e h8 y10c ff5 fs4 fc0 sc0 ls67 ws2">15</div><div class="t m0 x2f h7 y10d ff5 fs0 fc0 sc0 ls68 ws2">-DQ</div><div class="t m0 x30 h8 y10c ff5 fs4 fc0 sc0 ls3 ws2">8</div><div class="t m0 x9 h7 y10e ff5 fs0 fc0 sc0 ls4a wsd2">can be V</div><div class="t m0 x31 h8 y10f ff5 fs4 fc0 sc0 ls69 ws2">IL</div><div class="t m0 x32 h7 y10e ff5 fs0 fc0 sc0 ls6a wsd3"> or V</div><div class="t m0 x33 h8 y10f ff5 fs4 fc0 sc0 ls6b ws2">IH</div><div class="t m0 xc h7 y10e ff5 fs0 fc0 sc0 ls34 ws16">, but no o<span class="_ _0"></span>ther value, du<span class="_ _0"></span>ri<span class="_ _0"></span>ng any SD<span class="_ _0"></span>P co<span class="_ _0"></span>m-</div><div class="t m0 x9 h7 y110 ff5 fs0 fc0 sc0 ls42 wsd4">mand se<span class="_ _0"></span>quence.</div><div class="d m1"></div><div class="d m1"></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/bg4.jpg"><div class="t m2 xf h9 y63 ff5 fs5 fc0 sc0 ls3 ws2">4</div><div class="t m2 x10 h7 y1 ff5 fs0 fc0 sc0 ls16 ws2">Data Shee<span class="_ _0"></span>t</div><div class="t m2 x11 ha y64 ff4 fs6 fc0 sc0 ls3d ws51">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m2 x12 ha y65 ff4 fs6 fc0 sc0 ls3e ws2">SST39LF160 / SST39VF1<span class="_ _0"></span>60</div><div class="t m2 x2 h3 y2 ff5 fs1 fc0 sc0 ls3f ws52">©<span class="_ _0"></span>2001 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>6/01<span class="_ _a"> </span>399</span></div><div class="t m2 x2 h5 ycf ff4 fs3 fc0 sc0 ls3b wsd5">Common Flash Memory Interface (CFI)</div><div class="t m2 x2 h7 yd1 ff5 fs0 fc0 sc0 ls6c ws18">The SST39LF<span class="_ _0"></span>160 and SST39V<span class="_ _0"></span>F160 also c<span class="_ _0"></span>ontain the CFI</div><div class="t m2 x2 h7 yd2 ff5 fs0 fc0 sc0 ls6d wsd6">informat<span class="_ _0"></span>ion to descr<span class="_ _0"></span>ibe the ch<span class="_ _0"></span>aracter<span class="_ _0"></span>istics of the<span class="_ _0"></span> de<span class="_ _1"></span>vice.</div><div class="t m2 x2 h7 y111 ff5 fs0 fc0 sc0 ls6e wsba">In order to enter the CFI Q<span class="_ _0"></span>uer<span class="_ _0"></span>y mode, the syste<span class="_ _0"></span>m must</div><div class="t m2 x2 h7 y112 ff5 fs0 fc0 sc0 ls6e wsd7">write three-<span class="_ _0"></span>byte sequence, same as product ID entr<span class="_ _0"></span>y</div><div class="t m2 x2 h7 y113 ff5 fs0 fc0 sc0 ls6f wsd8">command with<span class="_ _0"></span> 98H (CFI Q<span class="_ _0"></span>uer<span class="_ _0"></span>y comma<span class="_ _0"></span>nd) to addr<span class="_ _0"></span>ess</div><div class="t m2 x2 h7 y114 ff5 fs0 fc0 sc0 ls65 ws87">5555H in the l<span class="_ _0"></span>ast byte sequence. On<span class="_ _0"></span>ce the device enters</div><div class="t m2 x2 h7 y115 ff5 fs0 fc0 sc0 ls6f ws4a">the CFI Quer<span class="_ _9"></span>y mode, the syste<span class="_ _0"></span>m can read CF<span class="_ _0"></span>I data at the</div><div class="t m2 x2 h7 y116 ff5 fs0 fc0 sc0 ls63 ws41">addresse<span class="_ _0"></span>s given in T<span class="_ _4"></span>ab<span class="_ _1"></span>les 5 throu<span class="_ _0"></span>gh 7. The system<span class="_ _0"></span> must</div><div class="t m2 x2 h7 y117 ff5 fs0 fc0 sc0 ls70 wsd9">write th<span class="_ _0"></span>e CFI Exit command to retur<span class="_ _0"></span>n to Read mod<span class="_ _0"></span>e from</div><div class="t m2 x2 h7 y118 ff5 fs0 fc0 sc0 ls6a ws31">the CFI Quer<span class="_ _9"></span>y mode.</div><div class="t m2 x2 h5 y119 ff4 fs3 fc0 sc0 ls5a wsa7">Product Identifica<span class="_ _0"></span>tion</div><div class="t m2 x2 h7 y11a ff5 fs0 fc0 sc0 ls2e wsda">The P<span class="_ _0"></span>roduct<span class="_ _0"></span> Ident<span class="_ _0"></span>ificati<span class="_ _0"></span>on m<span class="_ _0"></span>ode id<span class="_ _0"></span>entifi<span class="_ _0"></span>es the <span class="_ _0"></span>devices as</div><div class="t m2 x2 h7 y11b ff5 fs0 fc0 sc0 ls27 ws31">the SST<span class="_ _0"></span>39LF/VF<span class="_ _0"></span>160 and <span class="_ _0"></span>manufacturer as S<span class="_ _0"></span>ST<span class="_ _4"></span>. This m<span class="_ _0"></span>ode</div><div class="t m2 x2 h7 y11c ff5 fs0 fc0 sc0 ls36 wsdb">may be acces<span class="_ _0"></span>sed by software<span class="_ _0"></span> operation<span class="_ _0"></span>s. Users m<span class="_ _0"></span>ay use</div><div class="t m2 x2 h7 y11d ff5 fs0 fc0 sc0 ls2c wsce">the Software Pr<span class="_ _0"></span>oduct Id<span class="_ _0"></span>entific<span class="_ _0"></span>ation o<span class="_ _0"></span>peration to iden<span class="_ _0"></span>tify th<span class="_ _0"></span>e</div><div class="t m2 x2 h7 y11e ff5 fs0 fc0 sc0 ls32 wsdc">par<span class="_ _0"></span>t (<span class="_ _0"></span>i.e., using<span class="_ _0"></span> the device ID) whe<span class="_ _0"></span>n using<span class="_ _0"></span> multiple manu-</div><div class="t m2 x2 h7 y11f ff5 fs0 fc0 sc0 ls26 wsdd">facturers in the s<span class="_ _0"></span>ame so<span class="_ _0"></span>ck<span class="_ _1"></span>et. For details, see T<span class="_ _4"></span>able 4 for</div><div class="t m2 x2 h7 y120 ff5 fs0 fc0 sc0 ls32 ws0">software ope<span class="_ _0"></span>ration, Figur<span class="_ _0"></span>e 10 for the Software ID Entr<span class="_ _9"></span>y and</div><div class="t m2 x2 h7 y121 ff5 fs0 fc0 sc0 ls6c wsde">Read<span class="_ _1"></span> timi<span class="_ _1"></span>ng di<span class="_ _1"></span>agr<span class="_ _1"></span>am,<span class="_ _1"></span> and Fi<span class="_ _1"></span>gure<span class="_ _1"></span> 17 f<span class="_ _5"></span>or the Sof<span class="_ _1"></span>twa<span class="_ _1"></span>re ID</div><div class="t m2 x2 h7 y122 ff5 fs0 fc0 sc0 ls4f wsdf">Entry comman<span class="_ _1"></span>d seque<span class="_ _1"></span>nce flo<span class="_ _1"></span>wch<span class="_ _1"></span>ar<span class="_ _0"></span>t.</div><div class="t m2 x9 h5 y123 ff4 fs3 fc0 sc0 ls71 wse0">Product Identification Mode Exit/</div><div class="t m2 x9 h5 y124 ff4 fs3 fc0 sc0 ls72 wse1">CFI Mode Exit</div><div class="t m2 x9 h7 y125 ff5 fs0 fc0 sc0 ls2f ws7">In ord<span class="_ _0"></span>er to re<span class="_ _0"></span>tur<span class="_ _0"></span>n to<span class="_ _0"></span> the s<span class="_ _0"></span>tandard<span class="_ _0"></span> Read<span class="_ _0"></span> mode, the <span class="_ _0"></span>Software</div><div class="t m2 x9 h7 y126 ff5 fs0 fc0 sc0 ls26 wse2">Produc<span class="_ _0"></span>t Identifi<span class="_ _0"></span>cation<span class="_ _0"></span> mode must be<span class="_ _0"></span> e<span class="_ _1"></span>xited. Exi<span class="_ _0"></span>t is acco<span class="_ _0"></span>m-</div><div class="t m2 x9 h7 y127 ff5 fs0 fc0 sc0 ls2e wse3">plishe<span class="_ _0"></span>d by issui<span class="_ _0"></span>ng the So<span class="_ _0"></span>ftware ID E<span class="_ _0"></span>xit co<span class="_ _0"></span>mman<span class="_ _0"></span>d</div><div class="t m2 x9 h7 y128 ff5 fs0 fc0 sc0 ls35 ws3c">sequenc<span class="_ _0"></span>e, which r<span class="_ _0"></span>etur<span class="_ _0"></span>ns t<span class="_ _0"></span>he device to <span class="_ _0"></span>the Rea<span class="_ _0"></span>d operati<span class="_ _0"></span>on.</div><div class="t m2 x9 h7 y129 ff5 fs0 fc0 sc0 ls42 wsd4">This co<span class="_ _0"></span>mman<span class="_ _0"></span>d may also<span class="_ _0"></span> be used<span class="_ _0"></span> to res<span class="_ _0"></span>et the<span class="_ _0"></span> device to th<span class="_ _0"></span>e</div><div class="t m2 x9 h7 y12a ff5 fs0 fc0 sc0 ls47 wsda">Read<span class="_ _1"></span> mode a<span class="_ _1"></span>fter<span class="_ _1"></span> any i<span class="_ _1"></span>nadv<span class="_ _5"></span>er<span class="_ _0"></span>tent tr<span class="_ _5"></span>ansient con<span class="_ _1"></span>dit<span class="_ _1"></span>ion th<span class="_ _1"></span>at</div><div class="t m2 x9 h7 y12b ff5 fs0 fc0 sc0 ls2a wse4">appare<span class="_ _0"></span>ntly c<span class="_ _0"></span>auses <span class="_ _0"></span>the device to be<span class="_ _0"></span>hav<span class="_ _1"></span>e abno<span class="_ _0"></span>r<span class="_ _0"></span>mally<span class="_ _5"></span>, e.g.,</div><div class="t m2 x9 h7 y12c ff5 fs0 fc0 sc0 ls26 wsdd">not read<span class="_ _0"></span> corre<span class="_ _0"></span>ctly<span class="_ _4"></span>.<span class="_ _0"></span> Pleas<span class="_ _0"></span>e note that t<span class="_ _0"></span>he Soft<span class="_ _0"></span>ware ID Exit<span class="_ _0"></span>/</div><div class="t m2 x9 h7 y12d ff5 fs0 fc0 sc0 ls35 wse5">CFI Exit c<span class="_ _0"></span>omma<span class="_ _0"></span>nd is i<span class="_ _0"></span>gnored d<span class="_ _0"></span>uring<span class="_ _0"></span> an int<span class="_ _0"></span>er<span class="_ _0"></span>nal Pr<span class="_ _0"></span>ogram or</div><div class="t m2 x9 h7 y12e ff5 fs0 fc0 sc0 ls2b wse6">Erase op<span class="_ _0"></span>eration. S<span class="_ _0"></span>ee T<span class="_ _4"></span>able 4 for software co<span class="_ _0"></span>mman<span class="_ _0"></span>d</div><div class="t m2 x9 h7 y12f ff5 fs0 fc0 sc0 ls2c wse7">codes, Figu<span class="_ _0"></span>re 12<span class="_ _0"></span> f<span class="_ _1"></span>or timi<span class="_ _0"></span>ng wav<span class="_ _1"></span>ef<span class="_ _1"></span>or<span class="_ _0"></span>m an<span class="_ _0"></span>d Figure<span class="_ _0"></span> 17 for a</div><div class="t m2 x9 h7 y130 ff5 fs0 fc0 sc0 ls49 ws2">flowchar<span class="_ _9"></span>t.</div><div class="t m2 x9 h6 y131 ff4 fs0 fc0 sc0 ls73 ws2">T<span class="_ _4"></span>ABLE<span class="_ _7"> </span>1:<span class="_ _c"> </span>P</div><div class="t m2 x33 h6 y66 ff4 fs7 fc0 sc0 ls74 ws2">RODUCT<span class="fs0 ls75"> I</span><span class="ls76">DENT<span class="_ _1"></span>IFIC<span class="_ _1"></span>ATION</span></div><div class="t m2 x34 hb y132 ff4 fs5 fc0 sc0 ls77 ws2">Address<span class="_ _d"> </span>Data</div><div class="t m2 x35 h9 y133 ff5 fs5 fc0 sc0 ls78 ws2">Manufactur<span class="_ _0"></span>er<span class="ff2 ls3">’<span class="_ _1"></span><span class="ff5 ls79 wse8">s ID<span class="_ _e"> </span>0000H<span class="_ _d"> </span>00BFH</span></span></div><div class="t m2 x35 h9 y134 ff5 fs5 fc0 sc0 ls7a wse9">Device ID</div><div class="t m2 x36 h9 y135 ff5 fs5 fc0 sc0 ls7b ws2">SST39LF/VF16<span class="_ _1"></span>0<span class="_ _f"> </span>0001H<span class="_ _10"> </span>2782H</div><div class="t m2 x37 h3 y136 ff5 fs1 fc0 sc0 ls7c ws2">T1.2<span class="_ _11"> </span>399</div><div class="d m1"></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><div class="d m1"></div><div class="d m1"></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/bg5.jpg"><div class="t m0 x2 h7 y1 ff5 fs0 fc0 sc0 ls15 ws31">Data Sheet</div><div class="t m0 x2 ha y64 ff4 fs6 fc0 sc0 ls3d ws51">16 Mbit<span class="_ _a"> </span>Multi-Purpose Flash</div><div class="t m0 x2 ha y65 ff4 fs6 fc0 sc0 ls59 wsa6">SST39LF160 / SST39V<span class="_ _0"></span>F160</div><div class="t m0 xf h9 y63 ff5 fs5 fc0 sc0 ls3 ws2">5</div><div class="t m0 x2 h3 y2 ff5 fs1 fc0 sc0 ls3f ws52">©<span class="_ _0"></span>2001 Silicon<span class="_ _0"></span> Storage Technology, Inc.<span class="_ _b"> </span><span class="ls2 ws2">S71145-02<span class="_ _1"></span>-000<span class="_ _2"> </span>6/01<span class="_ _a"> </span>399</span></div><div class="t m0 x38 h6 y137 ff4 fs0 fc0 sc0 ls7d ws2">FIGURE<span class="_ _6"> </span>1:<span class="_ _c"> </span>P<span class="fs7 ls7e">IN</span><span class="ls75"> A<span class="fs7 ls7f">SSIGNME<span class="_ _0"></span>NTS</span><span class="ls3"> <span class="fs7 ls80">FO<span class="_ _0"></span>R<span class="_ _0"></span></span><span class="ls81 ws0"> 48-</span><span class="fs7 ls82">LEA<span class="_ _0"></span>D</span><span class="ls83 wsf"> TSOP </span><span class="fs7 ls74">AND</span><span class="ls84 ws7"> 48-</span><span class="fs7 ls85">BALL</span><span class="ls73 wsea"> TFBG<span class="_ _1"></span>A</span></span></span></div><div class="t m3 x39 hc y138 ff5 fs8 fc0 sc0 ls3 ws2">Y<span class="_ _4"></span>-Decoder</div><div class="t m3 x3a hc y139 ff5 fs8 fc0 sc0 ls3 ws2">I/O Buff<span class="_ _1"></span>ers and Data Latches</div><div class="t m4 x34 hd y13a ff5 fs9 fc0 sc0 ls3 ws2">399 ILL B1.1</div><div class="t m3 x1e hc y13b ff5 fs8 fc0 sc0 ls3 ws2">Address Buff<span class="_ _1"></span>er & Latches</div><div class="t m3 x3b hc y13c ff5 fs8 fc0 sc0 ls3 ws2">X-Decoder</div><div class="t m3 x1b hc y13d ff5 fs8 fc0 sc0 ls3 ws2">DQ</div><div class="t m3 x3c hc y13e ff5 fs8 fc0 sc0 ls3 ws2">15</div><div class="t m3 x3d hc y13d ff5 fs8 fc0 sc0 ls3 ws2"> - DQ</div><div class="t m3 x3e hc y13e ff5 fs8 fc0 sc0 ls3 ws2">0</div><div class="t m3 x3f hc y13f ff5 fs8 fc0 sc0 ls3 ws2">Memor<span class="_ _0"></span>y Address</div><div class="t m3 x21 hc y140 ff5 fs8 fc0 sc0 ls3 ws2">OE#</div><div class="t m3 x21 hc y141 ff5 fs8 fc0 sc0 ls3 ws2">CE#</div><div class="t m3 x40 hc y142 ff5 fs8 fc0 sc0 ls86 ws2">WE#</div><div class="t m3 x41 hc y143 ff5 fs8 fc0 sc0 ls3 ws2">SuperFlash</div><div class="t m3 x42 hc y144 ff5 fs8 fc0 sc0 ls3 ws2">Memor<span class="_ _0"></span>y</div><div class="t m3 x43 hc y145 ff5 fs8 fc0 sc0 ls3 ws2">Control Logic</div><div class="t m0 x44 h6 y146 ff4 fs0 fc0 sc0 ls3 ws2">F<span class="fs7 ls87">UNCTIONAL</span><span class="ls75"> B<span class="fs7 ls82">LOCK</span> D<span class="fs7 ls88">IAGRAM</span></span></div><div class="t m5 x45 he y147 ff5 fsa fc0 sc0 ls3 ws2">A13</div><div class="t m5 x46 he y148 ff5 fsa fc0 sc0 ls3 ws2">A9</div><div class="t m5 x47 he y149 ff5 fsa fc0 sc0 ls3 ws2">WE#</div><div class="t m5 x48 he y14a ff5 fsa fc0 sc0 ls3 ws2">NC</div><div class="t m5 x46 he y14b ff5 fsa fc0 sc0 ls3 ws2">A7</div><div class="t m5 x46 he y14c ff5 fsa fc0 sc0 ls3 ws2">A3</div><div class="t m5 x49 he y147 ff5 fsa fc0 sc0 ls3 ws2">A12</div><div class="t m5 x4a he y148 ff5 fsa fc0 sc0 ls3 ws2">A8</div><div class="t m5 x4b he y149 ff5 fsa fc0 sc0 ls3 ws2">NC</div><div class="t m5 x4b he y14a ff5 fsa fc0 sc0 ls3 ws2">NC</div><div class="t m5 x49 he y14b ff5 fsa fc0 sc0 ls3 ws2">A17</div><div class="t m5 x4a he y14c ff5 fsa fc0 sc0 ls3 ws2">A4</div><div class="t m5 x4c he y147 ff5 fsa fc0 sc0 ls3 ws2">A14</div><div class="t m5 x4c he y148 ff5 fsa fc0 sc0 ls3 ws2">A10</div><div class="t m5 x4d he y149 ff5 fsa fc0 sc0 ls3 ws2">NC</div><div class="t m5 x4c he y14a ff5 fsa fc0 sc0 ls3 ws2">A18</div><div class="t m5 x4e he y14b ff5 fsa fc0 sc0 ls3 ws2">A6</div><div class="t m5 x4e he y14c ff5 fsa fc0 sc0 ls3 ws2">A2</div><div class="t m5 x4f he y147 ff5 fsa fc0 sc0 ls3 ws2">A15</div><div class="t m5 x4f he y148 ff5 fsa fc0 sc0 ls3 ws2">A11</div><div class="t m5 x4f he y149 ff5 fsa fc0 sc0 ls3 ws2">A19</div><div class="t m5 x50 he y14a ff5 fsa fc0 sc0 ls3 ws2">NC</div><div class="t m5 x51 he y14b ff5 fsa fc0 sc0 ls3 ws2">A5</div><div class="t m5 x51 he y14c ff5 fsa fc0 sc0 ls3 ws2">A1</div><div class="t m5 x52 he y147 ff5 fsa fc0 sc0 ls3 ws2">A16</div><div class="t m5 x53 he y148 ff5 fsa fc0 sc0 ls3 ws2">DQ7</div><div class="t m5 x53 he y149 ff5 fsa fc0 sc0 ls3 ws2">DQ5</div><div class="t m5 x53 he y14a ff5 fsa fc0 sc0 ls3 ws2">DQ2</div><div class="t m5 x53 he y14b ff5 fsa fc0 sc0 ls3 ws2">DQ0</div><div class="t m5 x54 he y14c ff5 fsa fc0 sc0 ls3 ws2">A0</div><div class="t m5 x55 he y147 ff5 fsa fc0 sc0 ls3 ws2">NC</div><div class="t m5 x2a he y148 ff5 fsa fc0 sc0 ls3 ws2">DQ14</div><div class="t m5 x2a he y149 ff5 fsa fc0 sc0 ls3 ws2">DQ12</div><div class="t m5 x2a he y14a ff5 fsa fc0 sc0 ls3 ws2">DQ10</div><div class="t m5 x56 he y14b ff5 fsa fc0 sc0 ls3 ws2">DQ8</div><div class="t m5 x56 he y14c ff5 fsa fc0 sc0 ls3 ws2">CE#</div><div class="t m5 xb he y147 ff5 fsa fc0 sc0 ls3 ws2">DQ15</div><div class="t m5 xb he y148 ff5 fsa fc0 sc0 ls3 ws2">DQ13</div><div class="t m5 x57 he y149 ff5 fsa fc0 sc0 ls3 ws2">V</div><div class="t m5 x58 he y14d ff5 fsa fc0 sc0 ls3 ws2">DD</div><div class="t m5 xb he y14a ff5 fsa fc0 sc0 ls3 ws2">DQ11</div><div class="t m5 x57 he y14b ff5 fsa fc0 sc0 ls3 ws2">DQ9</div><div class="t m5 x57 he y14c ff5 fsa fc0 sc0 ls3 ws2">OE#</div><div class="t m5 x32 he y147 ff5 fsa fc0 sc0 ls3 ws2">V</div><div class="t m5 x59 he y14e ff5 fsa fc0 sc0 ls3 ws2">SS</div><div class="t m5 x32 he y148 ff5 fsa fc0 sc0 ls3 ws2">DQ6</div><div class="t m5 x32 he y149 ff5 fsa fc0 sc0 ls3 ws2">DQ4</div><div class="t m5 x32 he y14a ff5 fsa fc0 sc0 ls3 ws2">DQ3</div><div class="t m5 x32 he y14b ff5 fsa fc0 sc0 ls3 ws2">DQ1</div><div class="t m5 x32 he y14c ff5 fsa fc0 sc0 ls3 ws2">V</div><div class="t m5 x59 he y14f ff5 fsa fc0 sc0 ls3 ws2">SS</div><div class="t m6 x1b hf y150 ff5 fsb fc0 sc0 ls3 ws2">399 ILL F02a.1</div><div class="t m0 x29 h10 y151 ff5 fsc fc0 sc0 ls89 ws2">SST39LF/VF160</div><div class="t m0 x5a h11 y152 ff5 fsd fc0 sc0 ls3 ws2">T<span class="_ _1"></span>OP <span class="_ _5"></span>VIEW (balls facing down)</div><div class="t m0 x5b h12 y153 ff5 fse fc0 sc0 ls3 ws2">6</div><div class="t m0 x5b h12 y154 ff5 fse fc0 sc0 ls3 ws2">5</div><div class="t m0 x5b h12 y155 ff5 fse fc0 sc0 ls3 ws2">4</div><div class="t m0 x5b h12 y156 ff5 fse fc0 sc0 ls3 ws2">3</div><div class="t m0 x5b h12 y157 ff5 fse fc0 sc0 ls3 ws2">2</div><div class="t m0 x5b h12 y158 ff5 fse fc0 sc0 ls3 ws2">1</div><div class="t m7 x46 h10 y159 ff5 fsc fc0 sc0 ls8a ws2">A B C D E F G H</div><div class="t m4 x5c hd y15a ff5 fs9 fc0 sc0 ls3 ws2">A15</div><div class="t m4 x5c hd y15b ff5 fs9 fc0 sc0 ls3 ws2">A14</div><div class="t m4 x5c hd y15c ff5 fs9 fc0 sc0 ls3 ws2">A13</div><div class="t m4 x5c hd y15d ff5 fs9 fc0 sc0 ls3 ws2">A12</div><div class="t m4 x5c hd y15e ff5 fs9 fc0 sc0 ls3 ws2">A11</div><div class="t m4 x5c hd y15f ff5 fs9 fc0 sc0 ls3 ws2">A10</div><div class="t m4 x21 hd y160 ff5 fs9 fc0 sc0 ls3 ws2">A9</div><div class="t m4 x21 hd y161 ff5 fs9 fc0 sc0 ls3 ws2">A8</div><div class="t m4 x5c hd y162 ff5 fs9 fc0 sc0 ls3 ws2">A19</div><div class="t m4 x40 hd y163 ff5 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x5d hd y164 ff5 fs9 fc0 sc0 ls3 ws2">WE#</div><div class="t m4 x40 hd y165 ff5 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x40 hd y166 ff5 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x40 hd y167 ff5 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x40 hd y168 ff5 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x5c hd y169 ff5 fs9 fc0 sc0 ls3 ws2">A18</div><div class="t m4 x5c hd y16a ff5 fs9 fc0 sc0 ls3 ws2">A17</div><div class="t m4 x21 hd y16b ff5 fs9 fc0 sc0 ls3 ws2">A7</div><div class="t m4 x21 hd y16c ff5 fs9 fc0 sc0 ls3 ws2">A6</div><div class="t m4 x21 hd y16d ff5 fs9 fc0 sc0 ls3 ws2">A5</div><div class="t m4 x21 hd y16e ff5 fs9 fc0 sc0 ls3 ws2">A4</div><div class="t m4 x21 hd y16f ff5 fs9 fc0 sc0 ls3 ws2">A3</div><div class="t m4 x21 hd y170 ff5 fs9 fc0 sc0 ls3 ws2">A2</div><div class="t m4 x21 hd y171 ff5 fs9 fc0 sc0 ls3 ws2">A1</div><div class="t m4 x5e hd y172 ff5 fs9 fc0 sc0 ls3 ws2">1</div><div class="t m4 x5e hd y173 ff5 fs9 fc0 sc0 ls3 ws2">2</div><div class="t m4 x5e hd y174 ff5 fs9 fc0 sc0 ls3 ws2">3</div><div class="t m4 x5e hd y175 ff5 fs9 fc0 sc0 ls3 ws2">4</div><div class="t m4 x5e hd y176 ff5 fs9 fc0 sc0 ls3 ws2">5</div><div class="t m4 x5e hd y177 ff5 fs9 fc0 sc0 ls3 ws2">6</div><div class="t m4 x5e hd y178 ff5 fs9 fc0 sc0 ls3 ws2">7</div><div class="t m4 x5e hd y179 ff5 fs9 fc0 sc0 ls3 ws2">8</div><div class="t m4 x5e hd y17a ff5 fs9 fc0 sc0 ls3 ws2">9</div><div class="t m4 x5e hd y17b ff5 fs9 fc0 sc0 ls3 ws2">10</div><div class="t m4 x5e hd y17c ff5 fs9 fc0 sc0 ls3 ws2">11</div><div class="t m4 x5e hd y17d ff5 fs9 fc0 sc0 ls3 ws2">12</div><div class="t m4 x5e hd y17e ff5 fs9 fc0 sc0 ls3 ws2">13</div><div class="t m4 x5e hd y17f ff5 fs9 fc0 sc0 ls3 ws2">14</div><div class="t m4 x5e hd y180 ff5 fs9 fc0 sc0 ls3 ws2">15</div><div class="t m4 x5e hd y181 ff5 fs9 fc0 sc0 ls3 ws2">16</div><div class="t m4 x5e hd y182 ff5 fs9 fc0 sc0 ls3 ws2">17</div><div class="t m4 x5e hd y183 ff5 fs9 fc0 sc0 ls3 ws2">18</div><div class="t m4 x5e hd y184 ff5 fs9 fc0 sc0 ls3 ws2">19</div><div class="t m4 x5e hd y185 ff5 fs9 fc0 sc0 ls3 ws2">20</div><div class="t m4 x5e hd y186 ff5 fs9 fc0 sc0 ls3 ws2">21</div><div class="t m4 x5e hd y187 ff5 fs9 fc0 sc0 ls3 ws2">22</div><div class="t m4 x5e hd y188 ff5 fs9 fc0 sc0 ls3 ws2">23</div><div class="t m4 x5e hd y189 ff5 fs9 fc0 sc0 ls3 ws2">24</div><div class="t m4 x5f hd y15a ff5 fs9 fc0 sc0 ls3 ws2">A16</div><div class="t m4 x5f hd y15b ff5 fs9 fc0 sc0 ls3 ws2">NC</div><div class="t m4 x5f hd y15c ff5 fs9 fc0 sc0 ls3 ws2">V</div><div class="t m4 x19 hd y18a ff5 fs9 fc0 sc0 ls3 ws2">SS</div><div class="t m4 x5f hd y15d ff5 fs9 fc0 sc0 ls3 ws2">DQ15</div><div class="t m4 x5f hd y15e ff5 fs9 fc0 sc0 ls3 ws2">DQ7</div><div class="t m4 x5f hd y15f ff5 fs9 fc0 sc0 ls3 ws2">DQ14</div><div class="t m4 x5f hd y160 ff5 fs9 fc0 sc0 ls3 ws2">DQ6</div><div class="t m4 x5f hd y161 ff5 fs9 fc0 sc0 ls3 ws2">DQ13</div><div class="t m4 x5f hd y162 ff5 fs9 fc0 sc0 ls3 ws2">DQ5</div><div class="t m4 x5f hd y163 ff5 fs9 fc0 sc0 ls3 ws2">DQ12</div><div class="t m4 x5f hd y164 ff5 fs9 fc0 sc0 ls3 ws2">DQ4</div><div class="t m4 x5f hd y165 ff5 fs9 fc0 sc0 ls3 ws2">V</div><div class="t m4 x19 hd y18b ff5 fs9 fc0 sc0 ls3 ws2">DD</div><div class="t m4 x5f hd y166 ff5 fs9 fc0 sc0 ls3 ws2">DQ11</div><div class="t m4 x5f hd y167 ff5 fs9 fc0 sc0 ls3 ws2">DQ3</div><div class="t m4 x5f hd y168 ff5 fs9 fc0 sc0 ls3 ws2">DQ10</div><div class="t m4 x5f hd y169 ff5 fs9 fc0 sc0 ls3 ws2">DQ2</div><div class="t m4 x5f hd y16a ff5 fs9 fc0 sc0 ls3 ws2">DQ9</div><div class="t m4 x5f hd y16b ff5 fs9 fc0 sc0 ls3 ws2">DQ1</div><div class="t m4 x5f hd y16c ff5 fs9 fc0 sc0 ls3 ws2">DQ8</div><div class="t m4 x5f hd y16d ff5 fs9 fc0 sc0 ls3 ws2">DQ0</div><div class="t m4 x5f hd y16e ff5 fs9 fc0 sc0 ls3 ws2">OE#</div><div class="t m4 x5f hd y16f ff5 fs9 fc0 sc0 ls3 ws2">V</div><div class="t m4 x19 hd y18c ff5 fs9 fc0 sc0 ls3 ws2">SS</div><div class="t m4 x5f hd y170 ff5 fs9 fc0 sc0 ls3 ws2">CE#</div><div class="t m4 x5f hd y171 ff5 fs9 fc0 sc0 ls3 ws2">A0</div><div class="t m4 x60 hd y172 ff5 fs9 fc0 sc0 ls3 ws2">48</div><div class="t m4 x60 hd y173 ff5 fs9 fc0 sc0 ls3 ws2">47</div><div class="t m4 x60 hd y174 ff5 fs9 fc0 sc0 ls3 ws2">46</div><div class="t m4 x60 hd y175 ff5 fs9 fc0 sc0 ls3 ws2">45</div><div class="t m4 x60 hd y176 ff5 fs9 fc0 sc0 ls3 ws2">44</div><div class="t m4 x60 hd y177 ff5 fs9 fc0 sc0 ls3 ws2">43</div><div class="t m4 x60 hd y178 ff5 fs9 fc0 sc0 ls3 ws2">42</div><div class="t m4 x60 hd y179 ff5 fs9 fc0 sc0 ls3 ws2">41</div><div class="t m4 x60 hd y17a ff5 fs9 fc0 sc0 ls3 ws2">40</div><div class="t m4 x60 hd y17b ff5 fs9 fc0 sc0 ls3 ws2">39</div><div class="t m4 x60 hd y17c ff5 fs9 fc0 sc0 ls3 ws2">38</div><div class="t m4 x60 hd y17d ff5 fs9 fc0 sc0 ls3 ws2">37</div><div class="t m4 x60 hd y17e ff5 fs9 fc0 sc0 ls3 ws2">36</div><div class="t m4 x60 hd y17f ff5 fs9 fc0 sc0 ls3 ws2">35</div><div class="t m4 x60 hd y180 ff5 fs9 fc0 sc0 ls3 ws2">34</div><div class="t m4 x60 hd y181 ff5 fs9 fc0 sc0 ls3 ws2">33</div><div class="t m4 x60 hd y182 ff5 fs9 fc0 sc0 ls3 ws2">32</div><div class="t m4 x60 hd y183 ff5 fs9 fc0 sc0 ls3 ws2">31</div><div class="t m4 x60 hd y184 ff5 fs9 fc0 sc0 ls3 ws2">30</div><div class="t m4 x60 hd y185 ff5 fs9 fc0 sc0 ls3 ws2">29</div><div class="t m4 x60 hd y186 ff5 fs9 fc0 sc0 ls3 ws2">28</div><div class="t m4 x60 hd y187 ff5 fs9 fc0 sc0 ls3 ws2">27</div><div class="t m4 x60 hd y188 ff5 fs9 fc0 sc0 ls3 ws2">26</div><div class="t m4 x60 hd y189 ff5 fs9 fc0 sc0 ls3 ws2">25</div><div class="t m4 x2c hd y18d ff5 fs9 fc0 sc0 ls3 ws2">399 ILL F01.2</div><div class="t m0 x61 h10 y18e ff5 fsc fc0 sc0 ls3 ws2">Standard Pinout</div><div class="t m0 x62 h10 y18f ff5 fsc fc0 sc0 ls3 wseb">T<span class="_ _4"></span>op View</div><div class="t m0 x3b h10 y190 ff5 fsc fc0 sc0 ls8b wsec">Die Up</div><div class="t m0 x63 h10 y191 ff5 fsc fc0 sc0 ls3 ws2">SST39LF160/SST39VF160</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>