SST39VF160-Nor-Flash-Data-Sheet.zip

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nor flash(SST39VF160 Nor Flash )的数据手册英文文档。对nor flash的读写很有帮助。-nor flash
SST39VF160-Nor-Flash-Data-Sheet.zip
  • SST39VF160 Nor Flash Data Sheet.pdf
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253c51b74bc5c01050d3ce4/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Data S<span class="_ _0"></span>heet</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">&#169;<span class="_ _0"></span>2001 S<span class="_ _0"></span>ilicon Storage Technology, Inc.</div><div class="t m0 x2 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">S71145-0<span class="_ _1"></span>2-000<span class="_ _2"> </span>6/01<span class="_ _3"> </span>399</div><div class="t m0 x2 h3 y4 ff2 fs1 fc1 sc0 ls3 ws2">1</div><div class="t m0 x3 h3 y2 ff2 fs1 fc0 sc0 ls4 ws3">The SST logo an<span class="_ _1"></span>d SuperFlash are r<span class="_ _1"></span>egistered tra<span class="_ _1"></span>demarks of Silicon Storage T<span class="_ _4"></span>echnology<span class="_ _4"></span>, Inc.</div><div class="t m0 x4 h3 y3 ff2 fs1 fc0 sc0 ls5 ws4">MPF is a trademark of Silicon Storage T<span class="_ _4"></span>echnology<span class="_ _5"></span>, Inc.</div><div class="t m0 x5 h3 y4 ff2 fs1 fc0 sc0 ls6 ws5">These specif<span class="_ _1"></span>ications are sub<span class="_ _1"></span>ject to change with<span class="_ _1"></span>out notice.</div><div class="t m0 x6 h4 y5 ff3 fs2 fc0 sc0 ls7 ws2">16 Mbit<span class="_ _6"> </span>(x16)<span class="_ _6"> </span>Multi-Purpose Flash</div><div class="t m0 x7 h5 y6 ff3 fs3 fc0 sc0 ls3 ws6">SST39LF160 / SST39VF160</div><div class="t m0 x2 h5 y7 ff3 fs3 fc0 sc0 ls8 ws2">FEATURES:</div><div class="t m0 x2 h6 y8 ff3 fs0 fc0 sc0 ls9 ws7">&#8226;<span class="_ _7"> </span>Organized<span class="_ _0"></span> as 1M x1<span class="_ _0"></span>6</div><div class="t m0 x2 h6 y9 ff3 fs0 fc0 sc0 lsa ws8">&#8226;<span class="_ _7"> </span>Single V<span class="_ _5"></span>oltag<span class="_ _0"></span>e Read and W<span class="_ _0"></span>rite Oper<span class="_ _0"></span>ations</div><div class="t m0 x8 h7 ya ff2 fs0 fc0 sc0 lsb ws9">&#8211;<span class="_ _8"> </span>3.0-3.6V<span class="_ _0"></span> f<span class="_ _1"></span>or SST<span class="_ _0"></span>39LF160</div><div class="t m0 x8 h7 yb ff2 fs0 fc0 sc0 lsb ws9">&#8211;<span class="_ _8"> </span>2.7-3.6V<span class="_ _0"></span> f<span class="_ _1"></span>or SST<span class="_ _0"></span>39VF160</div><div class="t m0 x2 h6 yc ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 lsc wsa">Superior Rel<span class="_ _0"></span>iability</span></div><div class="t m0 x8 h7 yd ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsb ws9">Endurance<span class="_ _0"></span>: 100,000 Cy<span class="_ _0"></span>cles (ty<span class="_ _0"></span>pical)</span></div><div class="t m0 x8 h7 ye ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsd wsb">Greater th<span class="_ _0"></span>an 100 years Data<span class="_ _0"></span> Retention</span></div><div class="t m0 x2 h6 yf ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 lse wsc">Low P<span class="_ _5"></span>ower Consump<span class="_ _1"></span>tion</span></div><div class="t m0 x8 h7 y10 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsf wsd">Active Current: 15 mA (typical)</span></div><div class="t m0 x8 h7 y11 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls9 ws7">Standby Current<span class="_ _0"></span>: 4 &#181;A (typi<span class="_ _0"></span>cal)</span></div><div class="t m0 x8 h7 y12 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls10 wse">A<span class="_ _1"></span>uto Low P<span class="_ _1"></span>ow<span class="_ _1"></span>er Mode<span class="_ _0"></span>: 4 &#181;A (typi<span class="_ _0"></span>cal)</span></div><div class="t m0 x2 h6 y13 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls11 wsf">Sector<span class="_ _1"></span>-Erase Capability</span></div><div class="t m0 x8 h7 y14 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls12 ws10">Unif<span class="_ _5"></span>orm 2 KW<span class="_ _5"></span>ord sect<span class="_ _1"></span>ors</span></div><div class="t m0 x2 h6 y15 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls13 ws11">Fast Read Access<span class="_ _0"></span> Time</span></div><div class="t m0 x8 h7 y16 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls14 ws12">55 ns f<span class="_ _5"></span>o<span class="_ _0"></span>r SST39LF1<span class="_ _0"></span>60</span></div><div class="t m0 x8 h7 y17 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls15 ws13">70 and 90 ns f<span class="_ _5"></span>or<span class="_ _0"></span> SST39VF1<span class="_ _0"></span>60</span></div><div class="t m0 x2 h6 y18 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls16">Latched Address <span class="_ _0"></span>and Data</span></div><div class="t m0 x9 h6 y19 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls17 ws14">Fast Erase and<span class="_ _0"></span> W<span class="_ _5"></span>ord-Program</span></div><div class="t m0 xa h7 y1a ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls18 ws15">Sec<span class="_ _1"></span>tor-<span class="_ _1"></span>Erase<span class="_ _1"></span> Time<span class="_ _1"></span>: 18 ms<span class="_ _1"></span> (typ<span class="_ _1"></span>ical<span class="_ _1"></span>)</span></div><div class="t m0 xa h7 y1b ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls19 ws16">Block-Erase Ti<span class="_ _0"></span>me: 18 ms<span class="_ _0"></span> (typic<span class="_ _0"></span>al)</span></div><div class="t m0 xa h7 y1c ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsb ws9">Chip-Erase <span class="_ _0"></span>Time: 70<span class="_ _0"></span> ms (typic<span class="_ _0"></span>al)</span></div><div class="t m0 xa h7 y1d ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls1a ws17">W<span class="_ _1"></span>ord-Pr<span class="_ _1"></span>ogra<span class="_ _1"></span>m Time: 14 &#181;s (typ<span class="_ _1"></span>ical)</span></div><div class="t m0 xa h7 y1e ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsf ws18">Chip Rewrite T<span class="_ _0"></span>ime: 15 s<span class="_ _0"></span>econds<span class="_ _0"></span> (typical)<span class="_ _0"></span> for </span></div><div class="t m0 xb h7 y1f ff5 fs0 fc0 sc0 ls1b ws2">SST39LF/VF160</div><div class="t m0 x9 h6 y20 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls1c ws19">A<span class="_ _1"></span>utomatic Wri<span class="_ _1"></span>te Timing</span></div><div class="t m0 xa h7 y21 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsa ws8">Inter<span class="_ _0"></span>nal V</span></div><div class="t m0 xc h8 y22 ff5 fs4 fc0 sc0 ls1d ws2">PP</div><div class="t m0 xd h7 y23 ff5 fs0 fc0 sc0 ls14 ws1a"> Generatio<span class="_ _0"></span>n</div><div class="t m0 x9 h6 y24 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls1e ws1b">End-of-Wri<span class="_ _1"></span>te Detection</span></div><div class="t m0 xa h7 y25 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls1f ws1c">T<span class="_ _4"></span>oggle Bit</span></div><div class="t m0 xa h7 y26 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls20 ws1d">Data# Polling</span></div><div class="t m0 x9 h6 y27 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls21 ws1e">CMOS I/O Compat<span class="_ _0"></span>ibility </span></div><div class="t m0 x9 h6 y28 ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls22 ws1f">JEDEC Standard</span></div><div class="t m0 xa h7 y29 ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 lsb ws9">Flash EE<span class="_ _0"></span>PROM Pinouts<span class="_ _0"></span> and comm<span class="_ _0"></span>and sets</span></div><div class="t m0 x9 h6 y2a ff3 fs0 fc0 sc0 ls3 ws2">&#8226;<span class="_ _7"> </span><span class="ff4 ls9 ws7">P<span class="_ _1"></span>ackages A<span class="_ _1"></span>vailable</span></div><div class="t m0 xa h7 y2b ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls17 ws14">48-lead T<span class="_ _0"></span>SOP (12mm<span class="_ _0"></span> x 20mm)</span></div><div class="t m0 xa h7 y2c ff2 fs0 fc0 sc0 ls3 ws2">&#8211;<span class="_ _8"> </span><span class="ff5 ls23 ws20">48-ball<span class="_ _0"></span> TFBGA<span class="_ _0"></span> (6mm x 8<span class="_ _0"></span>mm)</span></div><div class="t m0 x2 h5 y2d ff4 fs3 fc0 sc0 ls24 ws21">PRODUCT DESCRIPTION</div><div class="t m0 x2 h7 y2e ff5 fs0 fc0 sc0 ls25 ws22">The SS<span class="_ _0"></span>T39L<span class="_ _0"></span>F/VF16<span class="_ _0"></span>0 devices <span class="_ _0"></span>are 1M x<span class="_ _0"></span>16 CMOS<span class="_ _0"></span> Mult<span class="_ _0"></span>i-</div><div class="t m0 x2 h7 y2f ff5 fs0 fc0 sc0 ls26 ws23">Pur<span class="_ _0"></span>p<span class="_ _0"></span>ose Flash (MP<span class="_ _0"></span>F) manufactured<span class="_ _0"></span> with SST<span class="ff2 ls3 ws2">&#8217;<span class="_ _5"></span><span class="ff5 ls27 ws24">s propr<span class="_ _0"></span>ietar<span class="_ _9"></span>y<span class="_ _4"></span>,</span></span></div><div class="t m0 x2 h7 y30 ff5 fs0 fc0 sc0 ls28 ws25">high pe<span class="_ _0"></span>rf<span class="_ _1"></span>or<span class="_ _0"></span>man<span class="_ _0"></span>ce CMO<span class="_ _0"></span>S Supe<span class="_ _0"></span>rFlash <span class="_ _0"></span>technol<span class="_ _0"></span>og<span class="_ _1"></span>y<span class="_ _4"></span>. T<span class="_ _0"></span>he</div><div class="t m0 x2 h7 y31 ff5 fs0 fc0 sc0 ls29 ws26">split-<span class="_ _0"></span>gate<span class="_ _0"></span> cell <span class="_ _0"></span>design<span class="_ _0"></span> and<span class="_ _0"></span> thick <span class="_ _0"></span>oxide tunn<span class="_ _0"></span>elin<span class="_ _0"></span>g inje<span class="_ _0"></span>ctor</div><div class="t m0 x2 h7 y32 ff5 fs0 fc0 sc0 ls2a ws27">attain be<span class="_ _0"></span>tter rel<span class="_ _0"></span>iability<span class="_ _0"></span> and manufacturabili<span class="_ _0"></span>ty comp<span class="_ _0"></span>ared wit<span class="_ _0"></span>h</div><div class="t m0 x2 h7 y33 ff5 fs0 fc0 sc0 ls28 ws28">alter<span class="_ _0"></span>nate<span class="_ _0"></span> approac<span class="_ _0"></span>hes. The SS<span class="_ _0"></span>T39LF<span class="_ _0"></span>160 wr<span class="_ _0"></span>ite (Pr<span class="_ _0"></span>ogram or</div><div class="t m0 x2 h7 y34 ff5 fs0 fc0 sc0 ls2b ws29">Erase) wit<span class="_ _0"></span>h a 3.0-<span class="_ _0"></span>3.6V power su<span class="_ _0"></span>pply<span class="_ _4"></span>.<span class="_ _0"></span> The SST3<span class="_ _0"></span>9VF16<span class="_ _0"></span>0</div><div class="t m0 x2 h7 y35 ff5 fs0 fc0 sc0 ls28 ws2a">wri<span class="_ _0"></span>te (Program or<span class="_ _0"></span> Erase) with<span class="_ _0"></span> a 2.7-3.<span class="_ _0"></span>6V power supply<span class="_ _5"></span>.</div><div class="t m0 x2 h7 y36 ff5 fs0 fc0 sc0 ls28 ws0">These devices c<span class="_ _0"></span>onform <span class="_ _0"></span>to JEDE<span class="_ _0"></span>C standa<span class="_ _0"></span>rd pino<span class="_ _0"></span>uts for x16</div><div class="t m0 x2 h7 y37 ff5 fs0 fc0 sc0 ls28 ws2">memor<span class="_ _0"></span>ies.</div><div class="t m0 x2 h7 y38 ff5 fs0 fc0 sc0 ls2c ws2b">F<span class="_ _1"></span>eatu<span class="_ _0"></span>rin<span class="_ _0"></span>g high perfor<span class="_ _0"></span>mance<span class="_ _0"></span> Word-Program, the S<span class="_ _0"></span>ST39L<span class="_ _0"></span>F/</div><div class="t m0 x2 h7 y39 ff5 fs0 fc0 sc0 ls2d ws2c">VF16<span class="_ _1"></span>0 de<span class="_ _5"></span>vices pro<span class="_ _1"></span>vide a ty<span class="_ _1"></span>pical W<span class="_ _5"></span>ord-Pr<span class="_ _1"></span>ogr<span class="_ _1"></span>am time<span class="_ _1"></span> of 14</div><div class="t m0 x2 h7 y3a ff5 fs0 fc0 sc0 ls2b ws2d">&#181;sec.Th<span class="_ _0"></span>ese d<span class="_ _0"></span>evices use T<span class="_ _4"></span>ogg<span class="_ _0"></span>le Bit <span class="_ _0"></span>or Data#<span class="_ _0"></span> P<span class="_ _5"></span>o<span class="_ _0"></span>lling t<span class="_ _0"></span>o ind<span class="_ _0"></span>i-</div><div class="t m0 x2 h7 y3b ff5 fs0 fc0 sc0 ls2e ws2e">cate<span class="_ _0"></span> the comp<span class="_ _0"></span>letio<span class="_ _0"></span>n of Pro<span class="_ _0"></span>gram operatio<span class="_ _0"></span>n. T<span class="_ _4"></span>o prot<span class="_ _0"></span>ect</div><div class="t m0 x2 h7 y3c ff5 fs0 fc0 sc0 ls28 ws2f">agains<span class="_ _0"></span>t inadver<span class="_ _0"></span>ten<span class="_ _0"></span>t wri<span class="_ _0"></span>te, they hav<span class="_ _5"></span>e<span class="_ _0"></span> on-chi<span class="_ _0"></span>p hardware an<span class="_ _0"></span>d</div><div class="t m0 x2 h7 y3d ff5 fs0 fc0 sc0 ls28 ws30">Software Dat<span class="_ _0"></span>a Prote<span class="_ _0"></span>ction sch<span class="_ _0"></span>emes. Desi<span class="_ _0"></span>gned, manufac-</div><div class="t m0 x2 h7 y3e ff5 fs0 fc0 sc0 ls27 ws31">tured, a<span class="_ _0"></span>nd tested<span class="_ _0"></span> f<span class="_ _1"></span>or a wi<span class="_ _0"></span>de spect<span class="_ _0"></span>rum<span class="_ _0"></span> of applic<span class="_ _0"></span>ations, the<span class="_ _0"></span>se</div><div class="t m0 x2 h7 y3f ff5 fs0 fc0 sc0 ls2f ws32">devices are offered wi<span class="_ _0"></span>th a gua<span class="_ _0"></span>ranteed en<span class="_ _0"></span>durance<span class="_ _0"></span> of 10,00<span class="_ _0"></span>0</div><div class="t m0 x2 h7 y40 ff5 fs0 fc0 sc0 ls30 ws33">cycl<span class="_ _0"></span>es. Data re<span class="_ _0"></span>tention i<span class="_ _0"></span>s rated <span class="_ _0"></span>at greater<span class="_ _0"></span> than 10<span class="_ _0"></span>0 years.</div><div class="t m0 x2 h7 y41 ff5 fs0 fc0 sc0 ls31 ws34">The SS<span class="_ _0"></span>T39LF<span class="_ _0"></span>/VF16<span class="_ _0"></span>0 devices ar<span class="_ _0"></span>e suit<span class="_ _0"></span>ed for applic<span class="_ _0"></span>atio<span class="_ _0"></span>ns</div><div class="t m0 x2 h7 y42 ff5 fs0 fc0 sc0 ls32 ws35">that req<span class="_ _0"></span>uire convenient an<span class="_ _0"></span>d econo<span class="_ _0"></span>mical upd<span class="_ _0"></span>ating of <span class="_ _0"></span>pro-</div><div class="t m0 x2 h7 y43 ff5 fs0 fc0 sc0 ls33 ws36">gr<span class="_ _1"></span>am,<span class="_ _1"></span> configur<span class="_ _1"></span>at<span class="_ _1"></span>ion, or<span class="_ _1"></span> data me<span class="_ _1"></span>mory<span class="_ _4"></span>. Fo<span class="_ _1"></span>r all syst<span class="_ _1"></span>em app<span class="_ _1"></span>li-</div><div class="t m0 x2 h7 y44 ff5 fs0 fc0 sc0 ls34 ws37">cations, th<span class="_ _0"></span>ey signif<span class="_ _0"></span>icantly<span class="_ _0"></span> improve performa<span class="_ _0"></span>nce an<span class="_ _0"></span>d</div><div class="t m0 x2 h7 y45 ff5 fs0 fc0 sc0 ls34 ws38">relia<span class="_ _0"></span>bility<span class="_ _5"></span>, while<span class="_ _0"></span> lowering p<span class="_ _0"></span>ower consum<span class="_ _0"></span>ption<span class="_ _0"></span>. They inher-</div><div class="t m0 x2 h7 y46 ff5 fs0 fc0 sc0 ls27 ws39">ently <span class="_ _0"></span>use les<span class="_ _0"></span>s energy dur<span class="_ _0"></span>ing<span class="_ _0"></span> Erase and<span class="_ _0"></span> Program <span class="_ _0"></span>than al<span class="_ _0"></span>ter-</div><div class="t m0 x2 h7 y47 ff5 fs0 fc0 sc0 ls2c ws3a">native flash te<span class="_ _0"></span>chnolo<span class="_ _0"></span>gies. The to<span class="_ _0"></span>tal energy consu<span class="_ _0"></span>med is a</div><div class="t m0 x2 h7 y48 ff5 fs0 fc0 sc0 ls2c ws9">functio<span class="_ _0"></span>n of th<span class="_ _0"></span>e appli<span class="_ _0"></span>ed voltage, cur<span class="_ _0"></span>rent, an<span class="_ _0"></span>d time of<span class="_ _0"></span> applic<span class="_ _0"></span>a-</div><div class="t m0 x2 h7 y49 ff5 fs0 fc0 sc0 ls2c ws3b">tion. Si<span class="_ _0"></span>nce for any given voltage range, the S<span class="_ _0"></span>uperF<span class="_ _0"></span>lash</div><div class="t m0 x9 h7 y4a ff5 fs0 fc0 sc0 ls2c ws3c">technol<span class="_ _0"></span>ogy uses less cur<span class="_ _0"></span>rent to p<span class="_ _0"></span>rogram and h<span class="_ _0"></span>as a shor<span class="_ _9"></span>ter</div><div class="t m0 x9 h7 y4b ff5 fs0 fc0 sc0 ls27 ws3d">erase time, the tot<span class="_ _0"></span>al ene<span class="_ _0"></span>rg<span class="_ _1"></span>y consu<span class="_ _0"></span>med dur<span class="_ _0"></span>ing<span class="_ _0"></span> any Erase or</div><div class="t m0 x9 h7 y4c ff5 fs0 fc0 sc0 ls35 ws3e">Program o<span class="_ _0"></span>peration is<span class="_ _0"></span> less<span class="_ _0"></span> than al<span class="_ _0"></span>ter<span class="_ _0"></span>native flash <span class="_ _0"></span>techn<span class="_ _0"></span>olo-</div><div class="t m0 x9 h7 y4d ff5 fs0 fc0 sc0 ls36 ws3f">gies. These<span class="_ _0"></span> devices also<span class="_ _0"></span> improve flexibility wh<span class="_ _0"></span>ile lower<span class="_ _0"></span>ing</div><div class="t m0 x9 h7 y4e ff5 fs0 fc0 sc0 ls26 ws40">the cos<span class="_ _0"></span>t for program, data<span class="_ _0"></span>, and con<span class="_ _0"></span>figurat<span class="_ _0"></span>ion sto<span class="_ _0"></span>rage appl<span class="_ _0"></span>i-</div><div class="t m0 x9 h7 y4f ff5 fs0 fc0 sc0 ls37 ws2">cations.</div><div class="t m0 x9 h7 y50 ff5 fs0 fc0 sc0 ls2b ws41">The S<span class="_ _0"></span>uperFlas<span class="_ _0"></span>h te<span class="_ _0"></span>chnology pr<span class="_ _0"></span>ovides fi<span class="_ _0"></span>x<span class="_ _1"></span>ed Eras<span class="_ _0"></span>e and P<span class="_ _0"></span>ro-</div><div class="t m0 x9 h7 y51 ff5 fs0 fc0 sc0 ls2c ws42">gram times, in<span class="_ _0"></span>depende<span class="_ _0"></span>nt of th<span class="_ _0"></span>e numbe<span class="_ _0"></span>r of Erase/<span class="_ _0"></span>Program</div><div class="t m0 x9 h7 y52 ff5 fs0 fc0 sc0 ls38 ws43">cycle<span class="_ _1"></span>s that<span class="_ _1"></span> ha<span class="_ _1"></span>v<span class="_ _1"></span>e occ<span class="_ _1"></span>urred<span class="_ _1"></span>. Ther<span class="_ _1"></span>ef<span class="_ _5"></span>ore the sys<span class="_ _1"></span>tem sof<span class="_ _1"></span>tw<span class="_ _1"></span>are</div><div class="t m0 x9 h7 y53 ff5 fs0 fc0 sc0 ls2a ws13">or hardwa<span class="_ _0"></span>re doe<span class="_ _0"></span>s not h<span class="_ _0"></span>av<span class="_ _1"></span>e to be<span class="_ _0"></span> modifi<span class="_ _0"></span>ed or <span class="_ _0"></span>de-rated<span class="_ _0"></span> as is</div><div class="t m0 x9 h7 y54 ff5 fs0 fc0 sc0 ls39 ws44">nece<span class="_ _0"></span>ssar<span class="_ _0"></span>y<span class="_ _0"></span> with a<span class="_ _0"></span>lter<span class="_ _0"></span>nat<span class="_ _0"></span>ive flash te<span class="_ _0"></span>chnolog<span class="_ _0"></span>ies, who<span class="_ _0"></span>se Eras<span class="_ _0"></span>e</div><div class="t m0 x9 h7 y55 ff5 fs0 fc0 sc0 ls2f ws45">and Pr<span class="_ _0"></span>ogram times<span class="_ _0"></span> increas<span class="_ _0"></span>e with<span class="_ _0"></span> accumul<span class="_ _0"></span>ated E<span class="_ _0"></span>rase/Pro-</div><div class="t m0 x9 h7 y56 ff5 fs0 fc0 sc0 ls33 ws46">gr<span class="_ _1"></span>am cycl<span class="_ _1"></span>es.</div><div class="t m0 x9 h7 y57 ff5 fs0 fc0 sc0 ls3a ws47">T<span class="_ _4"></span>o<span class="_ _1"></span> meet<span class="_ _1"></span> high<span class="_ _1"></span> densi<span class="_ _1"></span>ty<span class="_ _4"></span>, su<span class="_ _1"></span>rf<span class="_ _1"></span>ace<span class="_ _1"></span> mount<span class="_ _1"></span> requ<span class="_ _1"></span>irem<span class="_ _1"></span>ents<span class="_ _1"></span>, the</div><div class="t m0 x9 h7 y58 ff5 fs0 fc0 sc0 ls2b ws48">SST39<span class="_ _0"></span>LF/VF16<span class="_ _0"></span>0 are offered in 48-<span class="_ _0"></span>lead TS<span class="_ _0"></span>OP and 48-b<span class="_ _0"></span>all</div><div class="t m0 x9 h7 y59 ff5 fs0 fc0 sc0 ls35 ws9">TFBGA<span class="_ _0"></span> packages. See F<span class="_ _0"></span>igure 1<span class="_ _0"></span> for pinout<span class="_ _0"></span>s.</div><div class="t m0 x9 h5 y5a ff4 fs3 fc0 sc0 ls3b ws49">Device Operation</div><div class="t m0 x9 h7 y5b ff5 fs0 fc0 sc0 ls2c ws4a">Comma<span class="_ _0"></span>nds are us<span class="_ _0"></span>ed to<span class="_ _0"></span> initiat<span class="_ _0"></span>e the m<span class="_ _0"></span>emor<span class="_ _0"></span>y o<span class="_ _0"></span>peration f<span class="_ _0"></span>unc-</div><div class="t m0 x9 h7 y5c ff5 fs0 fc0 sc0 ls2c ws4b">tions of<span class="_ _0"></span> the device. Comman<span class="_ _0"></span>ds are w<span class="_ _0"></span>rit<span class="_ _0"></span>ten to th<span class="_ _0"></span>e device</div><div class="t m0 x9 h7 y5d ff5 fs0 fc0 sc0 ls39 ws4c">using s<span class="_ _0"></span>tanda<span class="_ _0"></span>rd micr<span class="_ _0"></span>oproc<span class="_ _0"></span>essor wr<span class="_ _0"></span>it<span class="_ _0"></span>e sequen<span class="_ _0"></span>ces. A co<span class="_ _0"></span>m-</div><div class="t m0 x9 h7 y5e ff5 fs0 fc0 sc0 ls2f ws4d">mand is<span class="_ _0"></span> written<span class="_ _0"></span> by asser<span class="_ _9"></span>ting WE<span class="_ _0"></span># low while keeping<span class="_ _0"></span> CE#</div><div class="t m0 x9 h7 y5f ff5 fs0 fc0 sc0 ls26 ws4e">low<span class="_ _5"></span>. Th<span class="_ _0"></span>e addr<span class="_ _0"></span>ess bus is <span class="_ _0"></span>latche<span class="_ _0"></span>d on <span class="_ _0"></span>the falling e<span class="_ _0"></span>dge o<span class="_ _0"></span>f WE#</div><div class="t m0 x9 h7 y60 ff5 fs0 fc0 sc0 ls2a ws4f">or CE#, <span class="_ _0"></span>whichev<span class="_ _1"></span>er occu<span class="_ _0"></span>rs last.<span class="_ _0"></span> The data<span class="_ _0"></span> bus is latc<span class="_ _0"></span>hed on</div><div class="t m0 x9 h7 y61 ff5 fs0 fc0 sc0 ls28 ws14">the r<span class="_ _0"></span>ising<span class="_ _0"></span> edge of <span class="_ _0"></span>WE# <span class="_ _0"></span>or CE#,<span class="_ _0"></span> whichev<span class="_ _1"></span>er occ<span class="_ _0"></span>urs firs<span class="_ _0"></span>t.</div><div class="t m0 xe h3 y62 ff5 fs1 fc1 sc0 ls3c ws50">SST39LF/<span class="_ _1"></span>VF1603<span class="_ _1"></span>.0 &amp; 2.7V 16<span class="_ _1"></span>Mb (x16) MP<span class="_ _1"></span>F memories</div><div class="d m1"></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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