pinctrl-xway.rar

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  • 2015-04-21 15:40
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based on linux drivers pinctrl pinmux-pxa910 for Linux v2.13.6.
pinctrl-xway.rar
  • pinctrl-xway.c
    25.7KB
内容介绍
/* * linux/drivers/pinctrl/pinmux-xway.c * based on linux/drivers/pinctrl/pinmux-pxa910.c * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. * * Copyright (C) 2012 John Crispin <blogic@openwrt.org> */ #include <linux/err.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/of_platform.h> #include <linux/of_address.h> #include <linux/of_gpio.h> #include <linux/ioport.h> #include <linux/io.h> #include <linux/device.h> #include <linux/platform_device.h> #include "pinctrl-lantiq.h" #include <lantiq_soc.h> /* we have 3 1/2 banks of 16 bit each */ #define PINS 16 #define PORT3 3 #define PORT(x) (x / PINS) #define PORT_PIN(x) (x % PINS) /* we have 2 mux bits that can be set for each pin */ #define MUX_ALT0 0x1 #define MUX_ALT1 0x2 /* * each bank has this offset apart from the 1/2 bank that is mixed into the * other 3 ranges */ #define REG_OFF 0x30 /* these are the offsets to our registers */ #define GPIO_BASE(p) (REG_OFF * PORT(p)) #define GPIO_OUT(p) GPIO_BASE(p) #define GPIO_IN(p) (GPIO_BASE(p) + 0x04) #define GPIO_DIR(p) (GPIO_BASE(p) + 0x08) #define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C) #define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10) #define GPIO_OD(p) (GPIO_BASE(p) + 0x14) #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) /* the 1/2 port needs special offsets for some registers */ #define GPIO3_OD (GPIO_BASE(0) + 0x24) #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) #define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24) /* macros to help us access the registers */ #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p))) #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r) #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r) #define MFP_XWAY(a, f0, f1, f2, f3) \ { \ .name = #a, \ .pin = a, \ .func = { \ XWAY_MUX_##f0, \ XWAY_MUX_##f1, \ XWAY_MUX_##f2, \ XWAY_MUX_##f3, \ }, \ } #define GRP_MUX(a, m, p) \ { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), } #define FUNC_MUX(f, m) \ { .func = f, .mux = XWAY_MUX_##m, } #define XWAY_MAX_PIN 32 #define XR9_MAX_PIN 56 enum xway_mux { XWAY_MUX_GPIO = 0, XWAY_MUX_SPI, XWAY_MUX_ASC, XWAY_MUX_PCI, XWAY_MUX_CGU, XWAY_MUX_EBU, XWAY_MUX_JTAG, XWAY_MUX_EXIN, XWAY_MUX_TDM, XWAY_MUX_STP, XWAY_MUX_SIN, XWAY_MUX_GPT, XWAY_MUX_NMI, XWAY_MUX_MDIO, XWAY_MUX_MII, XWAY_MUX_EPHY, XWAY_MUX_DFE, XWAY_MUX_SDIO, XWAY_MUX_GPHY, XWAY_MUX_NONE = 0xffff, }; static const struct ltq_mfp_pin xway_mfp[] = { /* pin f0 f1 f2 f3 */ MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE), MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY), MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY), MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY), MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN), MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE), MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI), MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE), MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE), MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE), MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE), MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG), MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG), MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG), MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE), MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE), MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT), MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE), MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP), MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI), MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC), MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM), MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC), MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE), MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE), MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE), MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE), MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU), MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU), MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU), MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU), MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU), MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE), MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE), MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE), MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), }; static const struct ltq_mfp_pin ase_mfp[] = { /* pin f0 f1 f2 f3 */ MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM), MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU), MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY), MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU), MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII), MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT), MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN), MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG), MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG), MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG), MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG), MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG), MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO), MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU), MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU), MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO), MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO), MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO), MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO), MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU), MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU), MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII), MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT), MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO), MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII), MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO), MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN), MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE), MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE), }; static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; static const unsigned pins_asc0[] = {GPIO11, GPIO12}; static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6}; static const unsigned pins_nmi[] = {GPIO8}; static const unsigned pins_mdio[] = {GPIO42, GPIO43}; static const unsigned pins_gphy0_led0[] = {GPIO5}; static const unsigned pins_gphy0_led1[] = {GPIO7}; static const unsigned pins_gphy0_led2[] = {GPIO2}; static const unsigned pins_gphy1_led0[] = {GPIO44}; static const unsigned pins_gphy1_led1[] = {GPIO45}; static const unsigned pins_gphy1_led2[] = {GPIO47}; static const unsigned pins_ebu_a24[] = {GPIO13}; static const unsigned pins_ebu_clk[] = {GPIO21}; static const unsigned pins_ebu_cs1[] = {GPIO23}; static const unsigned pins_ebu_a23[] = {GPIO24}; static const unsigned pins_ebu_wait[] = {GPIO26}; static const unsigned pins_ebu_a25[] = {GPIO31}; static const unsigned pins_ebu_rdy[] = {GPIO48}; static const unsigned pins_ebu_rd[] = {GPIO49}; static const unsigned pins_nand_ale[] = {GPIO13}; static const unsigned pins_nand_cs1[] = {GPIO23}; static const unsigned pins_nand_cle[] = {GPIO24}; static const unsigned pins_nand_rdy[] = {GPIO48}; static const unsigned pins_nand_rd[] = {GPIO49}; static const unsigned pins_exin0[] = {GPIO0}; static const unsigned pins_exin1[] = {GPIO1}; static const unsigned pins_exin2[] = {GPIO2}; static const unsigned pins_exin3[] = {GPIO39}; static const unsigned pins_exin4[] =
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