cx18-dvb.rar

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  • 2015-05-13 16:15
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cx18 functions for DVB support for Linux v2.13.6.
cx18-dvb.rar
  • cx18-dvb.c
    16.7KB
  • cx18-dvb.h
    946B
内容介绍
/* * cx18 functions for DVB support * * Copyright (c) 2008 Steven Toth <stoth@linuxtv.org> * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net rel='nofollow' onclick='return false;'> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "cx18-version.h" #include "cx18-dvb.h" #include "cx18-io.h" #include "cx18-queue.h" #include "cx18-streams.h" #include "cx18-cards.h" #include "cx18-gpio.h" #include "s5h1409.h" #include "mxl5005s.h" #include "s5h1411.h" #include "tda18271.h" #include "zl10353.h" #include <linux/firmware.h> #include "mt352.h" #include "mt352_priv.h" #include "tuner-xc2028.h" DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); #define FWFILE "dvb-cx18-mpc718-mt352.fw" #define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000 #define CX18_CLOCK_ENABLE2 0xc71024 #define CX18_DMUX_CLK_MASK 0x0080 /* * CX18_CARD_HVR_1600_ESMT * CX18_CARD_HVR_1600_SAMSUNG */ static struct mxl5005s_config hauppauge_hvr1600_tuner = { .i2c_address = 0xC6 >> 1, .if_freq = IF_FREQ_5380000HZ, .xtal_freq = CRYSTAL_FREQ_16000000HZ, .agc_mode = MXL_SINGLE_AGC, .tracking_filter = MXL_TF_C_H, .rssi_enable = MXL_RSSI_ENABLE, .cap_select = MXL_CAP_SEL_ENABLE, .div_out = MXL_DIV_OUT_4, .clock_out = MXL_CLOCK_OUT_DISABLE, .output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM, .top = MXL5005S_TOP_25P2, .mod_mode = MXL_DIGITAL_MODE, .if_mode = MXL_ZERO_IF, .qam_gain = 0x02, .AgcMasterByte = 0x00, }; static struct s5h1409_config hauppauge_hvr1600_config = { .demod_address = 0x32 >> 1, .output_mode = S5H1409_SERIAL_OUTPUT, .gpio = S5H1409_GPIO_ON, .qam_if = 44000, .inversion = S5H1409_INVERSION_OFF, .status_mode = S5H1409_DEMODLOCKING, .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, .hvr1600_opt = S5H1409_HVR1600_OPTIMIZE }; /* * CX18_CARD_HVR_1600_S5H1411 */ static struct s5h1411_config hcw_s5h1411_config = { .output_mode = S5H1411_SERIAL_OUTPUT, .gpio = S5H1411_GPIO_OFF, .vsb_if = S5H1411_IF_44000, .qam_if = S5H1411_IF_4000, .inversion = S5H1411_INVERSION_ON, .status_mode = S5H1411_DEMODLOCKING, .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, }; static struct tda18271_std_map hauppauge_tda18271_std_map = { .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 6, .rfagc_top = 0x37 }, .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, .if_lvl = 6, .rfagc_top = 0x37 }, }; static struct tda18271_config hauppauge_tda18271_config = { .std_map = &hauppauge_tda18271_std_map, .gate = TDA18271_GATE_DIGITAL, .output_opt = TDA18271_OUTPUT_LT_OFF, }; /* * CX18_CARD_LEADTEK_DVR3100H */ /* Information/confirmation of proper config values provided by Terry Wu */ static struct zl10353_config leadtek_dvr3100h_demod = { .demod_address = 0x1e >> 1, /* Datasheet suggested straps */ .if2 = 45600, /* 4.560 MHz IF from the XC3028 */ .parallel_ts = 1, /* Not a serial TS */ .no_tuner = 1, /* XC3028 is not behind the gate */ .disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */ }; /* * CX18_CARD_YUAN_MPC718 */ /* * Due to * * 1. an absence of information on how to prgram the MT352 * 2. the Linux mt352 module pushing MT352 initialzation off onto us here * * We have to use an init sequence that *you* must extract from the Windows * driver (yuanrap.sys) and which we load as a firmware. * * If someone can provide me with a Zarlink MT352 (Intel CE6352?) Design Manual * with chip programming details, then I can remove this annoyance. */ static int yuan_mpc718_mt352_reqfw(struct cx18_stream *stream, const struct firmware **fw) { struct cx18 *cx = stream->cx; const char *fn = FWFILE; int ret; ret = request_firmware(fw, fn, &cx->pci_dev->dev); if (ret) CX18_ERR("Unable to open firmware file %s\n", fn); else { size_t sz = (*fw)->size; if (sz < 2 || sz > 64 || (sz % 2) != 0) { CX18_ERR("Firmware %s has a bad size: %lu bytes\n", fn, (unsigned long) sz); ret = -EILSEQ; release_firmware(*fw); *fw = NULL; } } if (ret) { CX18_ERR("The MPC718 board variant with the MT352 DVB-T" "demodualtor will not work without it\n"); CX18_ERR("Run 'linux/Documentation/dvb/get_dvb_firmware " "mpc718' if you need the firmware\n"); } return ret; } static int yuan_mpc718_mt352_init(struct dvb_frontend *fe) { struct cx18_dvb *dvb = container_of(fe->dvb, struct cx18_dvb, dvb_adapter); struct cx18_stream *stream = dvb->stream; const struct firmware *fw = NULL; int ret; int i; u8 buf[3]; ret = yuan_mpc718_mt352_reqfw(stream, &fw); if (ret) return ret; /* Loop through all the register-value pairs in the firmware file */ for (i = 0; i < fw->size; i += 2) { buf[0] = fw->data[i]; /* Intercept a few registers we want to set ourselves */ switch (buf[0]) { case TRL_NOMINAL_RATE_0: /* Set our custom OFDM bandwidth in the case below */ break; case TRL_NOMINAL_RATE_1: /* 6 MHz: 64/7 * 6/8 / 20.48 * 2^16 = 0x55b6.db6 */ /* 7 MHz: 64/7 * 7/8 / 20.48 * 2^16 = 0x6400 */ /* 8 MHz: 64/7 * 8/8 / 20.48 * 2^16 = 0x7249.249 */ buf[1] = 0x72; buf[2] = 0x49; mt352_write(fe, buf, 3); break; case INPUT_FREQ_0: /* Set our custom IF in the case below */ break; case INPUT_FREQ_1: /* 4.56 MHz IF: (20.48 - 4.56)/20.48 * 2^14 = 0x31c0 */ buf[1] = 0x31; buf[2] = 0xc0; mt352_write(fe, buf, 3); break; default: /* Pass through the register-value pair from the fw */ buf[1] = fw->data[i+1]; mt352_write(fe, buf, 2); break; } } buf[0] = (u8) TUNER_GO; buf[1] = 0x01; /* Go */ mt352_write(fe, buf, 2); release_firmware(fw); return 0; } static struct mt352_config yuan_mpc718_mt352_demod = { .demod_address = 0x1e >> 1, .adc_clock = 20480, /* 20.480 MHz */ .if2 = 4560, /* 4.560 MHz */ .no_tuner = 1, /* XC3028 is not behind the gate */ .demod_init = yuan_mpc718_mt352_init, }; static struct zl10353_config yuan_mpc718_zl10353_demod = { .demod_address = 0x1e >> 1, /* Datasheet suggested straps */ .if2 = 45600, /* 4.560 MHz IF from the XC3028 */ .parallel_ts = 1, /* Not a serial TS */ .no_tuner = 1, /* XC3028 is not behind the gate */ .disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */ }; static struct zl10353_config gotview_dvd3_zl10353_demod = { .demod_address = 0x1e >> 1, /* Datasheet suggested straps */ .if2 = 45600, /* 4.560 MHz IF from the XC3028 */ .parallel_ts = 1, /* Not a serial TS */ .no_tuner = 1, /* XC3028 is not behind the gate */ .disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */ }; static int dvb_register(struct cx18_stream *stream); /* Kernel DVB framework calls this when the feed needs to start. * The CX18 framework should enable the transport DMA handling * and queue processing. */ static int cx18_dvb_start_feed(struct dvb_demux_feed *feed) { struct dvb_demux *demux = feed->demux; struct cx18_stream *stream = (struct cx18_stream *) demux->priv; struct cx18 *cx; int ret; u32 v; if (!stream) return -EINVAL; c
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