omap3.rar

/* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/omap.h> #include "skeleton.dtsi" / { compatible = "ti,omap3430", "ti,omap3"; interrupt-parent = <&intc>; aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; device_type = "cpu"; reg = <0x0>; clocks = <&dpll1_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; pmu { compatible = "arm,cortex-a8-pmu"; reg = <0x54000000 0x800000>; interrupts = <3>; ti,hwmods = "debugss"; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; }; iva: iva { compatible = "ti,iva2.2"; ti,hwmods = "iva"; dsp { compatible = "ti,omap3-c64"; }; }; }; /* * XXX: Use a flat representation of the OMAP3 interconnect. * The real OMAP interconnect network is quite complex. * Since it will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ ocp { compatible = "ti,omap3-l3-smx", "simple-bus"; reg = <0x68000000 0x10000>; interrupts = <9 10>; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; aes: aes@480c5000 { compatible = "ti,omap3-aes"; ti,hwmods = "aes"; reg = <0x480c5000 0x50>; interrupts = <0>; }; prm: prm@48306000 { compatible = "ti,omap3-prm"; reg = <0x48306000 0x4000>; interrupts = <11>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prm_clockdomains: clockdomains { }; }; cm: cm@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; cm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_clockdomains: clockdomains { }; }; scrm: scrm@48002000 { compatible = "ti,omap3-scrm"; reg = <0x48002000 0x2000>; scrm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; scrm_clockdomains: clockdomains { }; }; counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; ti,hwmods = "counter_32k"; }; intc: interrupt-controller@48200000 { compatible = "ti,omap3-intc"; interrupt-controller; #interrupt-cells = <1>; reg = <0x48200000 0x1000>; }; sdma: dma-controller@48056000 { compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; reg = <0x48056000 0x1000>; interrupts = <12>, <13>, <14>, <15>; #dma-cells = <1>; #dma-channels = <32>; #dma-requests = <96>; }; omap3_pmx_core: pinmux@48002030 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x48002030 0x0238>; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; omap3_pmx_wkup: pinmux@48002a00 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x48002a00 0x5c>; #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; omap3_scm_general: tisyscon@48002270 { compatible = "syscon"; reg = <0x48002270 0x2f0>; }; pbias_regulator: pbias_regulator { compatible = "ti,pbias-omap"; reg = <0x2b0 0x4>; syscon = <&omap3_scm_general>; pbias_mmc_reg: pbias_mmc_omap2430 { regulator-name = "pbias_mmc_omap2430"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; }; gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; reg = <0x48310000 0x200>; interrupts = <29>; ti,hwmods = "gpio1"; ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@49050000 { compatible = "ti,omap3-gpio"; reg = <0x49050000 0x200>; interrupts = <30>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@49052000 { compatible = "ti,omap3-gpio"; reg = <0x49052000 0x200>; interrupts = <31>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@49054000 { compatible = "ti,omap3-gpio"; reg = <0x49054000 0x200>; interrupts = <32>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio5: gpio@49056000 { compatible = "ti,omap3-gpio"; reg = <0x49056000 0x200>; interrupts = <33>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio6: gpio@49058000 { compatible = "ti,omap3-gpio"; reg = <0x49058000 0x200>; interrupts = <34>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; uart1: serial@4806a000 { compatible = "ti,omap3-uart"; reg = <0x4806a000 0x2000>; interrupts-extended = <&intc 72>; dmas = <&sdma 49 &sdma 50>; dma-names = "tx", "rx"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap3-uart"; reg = <0x4806c000 0x400>; interrupts-extended = <&intc 73>; dmas = <&sdma 51 &sdma 52>; dma-names = "tx", "rx"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@49020000 { compatible = "ti,omap3-uart"; reg = <0x49020000 0x400>; interrupts-extended = <&intc 74>; dmas = <&sdma 53 &sdma 54>; dma-names = "tx", "rx"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; reg = <0x48070000 0x80>; interrupts = <56>; dmas = <&sdma 27 &sdma 28>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; }; i2c2: i2c@48072000 { compatible = "ti,omap3-i2c"; reg = <0x48072000 0x80>; interrupts = <57>; dmas = <&sdma 29 &sdma 30>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; }; i2c3: i2c@48060000 { compatible = "ti,omap3-i2c"; reg = <0x48060000 0x80>; interrupts = <61>; dmas = <&sdma 25 &sdma 26>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; mailbox: mailbox@48094000 { compatible = "ti,omap3-mailbox"; ti,hwmods = "mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; mbox_dsp: dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; }; mcspi1: spi@48098000 { compatible = "ti,omap2-mcspi"; reg = <0x48098000 0x100>; interrupts = <65>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; ti,spi-num-cs = <4>; dmas = <&sdma 35>, <&sdma 36>, <&sdma 37>, <&sdma 38>, <&sdma 39>, <&sdma 40>, <&sdma 41>, <&sdma 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; mcspi2: spi@4809a000 { compatible = "ti,omap2-mcspi"; reg = <0x4809a00