mv7100.rar

/* sysLib.c - mv7100 system-dependent library */ /* * Copyright (c) 2008-2009 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* Copyright 2004-2005 Motorola Inc. All Rights Reserved */ /* modification history -------------------- 01h,14sep09,x_z replace sysSvrGet() with vxSvrGet() of vxALib.s 01g,21may09,e_d remove sysGetMpxClkRtc() and set oscFreq variable to 66666666 01f,16feb09,e_d change CPU1_INIT_START_FUNC from RAM_LOW_ADRS to sysCpu1loop 01e,12feb09,e_d add wrLoad support 01d,07jan09,e_d add INCLUDE_PCI_BUS 01c,10sep08,y_w fixed Copyright notice 01b,25apr08,mdg fixed bug when INCLUDE_SM_COMMON was undef'ed and compiler warnrings. 01a,17mar08,mdg created from MVME7100 and hpc8641net BSPs. */ /* DESCRIPTION This library provides board-specific routines. The chip drivers included are: sysEpic.c - programmable interrupt controller driver flashMem.c - 29F040 flash memory device driver. sysCacheLib.s - L1 and L2 cache lock support sysDuart.c - Serial support ns16550.c - optional now linked via vxBus ppcDecTimer - Optional now linked via vxBus motTsecEnd.c - Optional vxBus HEnd driver now used INCLUDE FILES: sysLib.h SEE ALSO: .pG "Configuration" */ /* includes */ #include <vxWorks.h> #include <stdio.h> #include <vme.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <logLib.h> #include <taskLib.h> #include <vxLib.h> #include <tyLib.h> #include <vmLib.h> #include <smUtilLib.h> #include <arch/ppc/mmu603Lib.h rel='nofollow' onclick='return false;'> #include <arch/ppc/vxPpcLib.h rel='nofollow' onclick='return false;'> #ifdef INCLUDE_CACHE_L2 #include "sysL2Cache.h" #endif #include <vxBusLib.h> #include <hwif/vxbus/vxBus.h> #ifdef INCLUDE_PCI_BUS #include <drv/pci/pciConfigLib.h> #include <drv/pci/pciIntLib.h> #include <drv/pci/pciAutoConfigLib.h> #include "mot85xxPci.h" #endif /* INCLUDE_PCI_BUS */ #if defined (INCLUDE_ALTIVEC) #include <altivecLib.h rel='nofollow' onclick='return false;'> #endif #ifdef INCLUDE_AMP #include <vxIpiLib.h> IMPORT int sysStartType; int sysSerialCore [] = { COM0_CORE, #ifdef INCLUDE_QUAD_UART QUART_CORE, QUART_CORE, QUART_CORE, QUART_CORE #endif /* INCLUDE_QUAD_UART */ }; #endif /* INCLUDE_AMP */ IMPORT int (* _func_altivecProbeRtn) () ; /* * This must be updated after the bore bring-up specified in the SMP HLD * implemented. */ IMPORT cpuset_t vxCpuEnabled; /* defines */ #undef BUS_PROBE_TEST /* test routines for sysBusProbe support */ #define ZERO 0 /* globals */ /* * sysBatDesc[] is used to initialize the block address translation (BAT) * registers within the PowerPC 603/604 MMU. BAT hits take precedence * over Page Table Entry (PTE) hits and are faster. Overlap of memory * coverage by BATs and PTEs is permitted in cases where either the IBATs * or the DBATs do not provide the necessary mapping (PTEs apply to both * instruction AND data space, without distinction). * * The primary means of memory control for VxWorks is the MMU PTE support * provided by vmLib and cacheLib. Use of BAT registers will conflict * with vmLib support. User's may use BAT registers for i/o mapping and * other purposes but are cautioned that conflicts with caching and mapping * through vmLib may arise. Be aware that memory spaces mapped through a BAT * are not mapped by a PTE and any vmLib() or cacheLib() operations on such * areas will not be effective, nor will they report any error conditions. * * Note: BAT registers CANNOT be disabled - they are always active. * For example, setting them all to zero will yield four identical data * and instruction memory spaces starting at local address zero, each 128KB * in size, and each set as write-back and cache-enabled. Hence, the BAT regs * MUST be configured carefully. * * With this in mind, it is recommended that the BAT registers be used * to map LARGE memory areas external to the processor if possible. * If not possible, map sections of high RAM and/or PROM space where * fine grained control of memory access is not needed. This has the * beneficial effects of reducing PTE table size (8 bytes per 4k page) * and increasing the speed of access to the largest possible memory space. * Use the PTE table only for memory which needs fine grained (4KB pages) * control or which is too small to be mapped by the BAT regs. * * The BAT configuration for 4xx/6xx-based PPC boards is as follows: * All BATs point to PROM/FLASH memory so that end customer may configure * them as required. * * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments] */ UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT +_MMU_NUM_EXTRA_IBAT+_MMU_NUM_EXTRA_DBAT)] = { /* I BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* I BAT 1 */ 0,0, /* I BAT 2 */ 0,0, /* I BAT 3 */ 0,0, /* D BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* D BAT 1 */ ((CCSBAR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((CCSBAR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 2 */ ((LOCAL_BOARD_ACCESS_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256K | _MMU_UBAT_VS | _MMU_UBAT_VP), ((LOCAL_BOARD_ACCESS_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* D BAT 3 */ ((PCI0_MEM_LOCAL_START & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1G | _MMU_UBAT_VS | _MMU_UBAT_VP), ((PCI0_MEM_LOCAL_START & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED) /* * These entries are for the I/D BAT's (4-7) on the MPC7455/755. * They should be defined in the following order. * IBAT4U,IBAT4L,IBAT5U,IBAT5L,IBAT6U,IBAT6L,IBAT7U,IBAT7L, * DBAT4U,DBAT4L,DBAT5U,DBAT5L,DBAT6U,DBAT6L,DBAT7U,DBAT7L, */ , /* I BAT 4 */ 0,0, /* I BAT 5 */ 0,0, /* I BAT 6 */ 0,0, /* I BAT 7 */ 0,0, /* D BAT 4 */ ((SBC_MRAM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512K | _MMU_UBAT_VS | _MMU_UBAT_VP), ((SBC_MRAM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 5 */ ((PCI1_MEM_LOCAL_START & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((PCI1_MEM_LOCAL_START & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 6 */ ((PCI0_IO_LOCAL_START & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((PCI0_IO_LOCAL_START & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 7 */ ((PCI1_IO_LOCAL_START & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((PCI1_IO_LOCAL_START & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), }; /* * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array * used by the MMU to translate addresses with single page (4k) granularity. * PTE memory space should not, in general, overlap BAT memory space but * may be allowed if only Data or Instruction access is mapped via BAT. * * Address translations for local RAM, memory mapped PCI bus, memory mapped * VME A16 space and local PROM/FLASH are set here. * * All entries in this table both ad