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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6287d9feb305d84a4f96d44d/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">Zeal Education Society’s Dnyanganga College of Engineering<span class="_ _0"></span> & Research, Narhe, Pune</div><div class="t m0 x2 h3 y3 ff2 fs0 fc1 sc0 ls0 ws0"> Lecture Notes on </div><div class="t m0 x3 h4 y4 ff1 fs1 fc2 sc0 ls0 ws0">VLSI Design & Technology</div><div class="t m0 x4 h3 y5 ff1 fs0 fc2 sc0 ls0 ws0">(Course Code:<span class="ff2 fs2 fc0"> </span>(<span class="fc3">404181</span>)</div><div class="t m0 x5 h3 y6 ff1 fs0 fc2 sc0 ls0 ws0">B.E. Electronics & telecommunication Engineering </div><div class="t m0 x6 h3 y7 ff1 fs0 fc2 sc0 ls0 ws0">(2012 course)</div><div class="t m0 x6 h3 y8 ff1 fs0 fc2 sc0 ls0 ws0">Developed by </div><div class="t m0 x7 h3 y9 ff1 fs0 fc2 sc0 ls0 ws0">Prof. Bhosale S.A. </div><div class="t m0 x8 h3 ya ff1 fs0 fc2 sc0 ls0 ws0">Asst. Professor in Electronics & telecommunication Engineering</div><div class="t m0 x9 h3 yb ff2 fs0 fc0 sc0 ls0 ws0">Zeal Education Society’s</div><div class="t m0 xa h3 yc ff2 fs0 fc0 sc0 ls0 ws0">Dnyanganga College of Engineering & Research, Narhe, Pune-411041</div><div class="t m0 xb h3 yd ff2 fs0 fc0 sc0 ls0 ws0">Maharashtra (INDIA)</div><div class="t m0 xc h3 ye ff2 fs0 fc0 sc0 ls0 ws0">JUNE 2015</div><div class="t m0 xd h3 yf ff3 fs0 fc0 sc0 ls0 ws0">Bhosale S.A. VLSI Design & T<span class="_ _1"></span>echnology<span class="_ _2"> </span><span class="ff1">1</span></div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6287d9feb305d84a4f96d44d/bg2.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">Zeal Education Society’s Dnyanganga College of Engineering<span class="_ _0"></span> & Research, Narhe, Pune</div><div class="t m0 xd h5 y10 ff4 fs1 fc4 sc0 ls0 ws0">Unit 2: PLD Architectures</div><div class="t m0 xd h6 y11 ff2 fs3 fc0 sc0 ls0 ws0">Programmable logic device (PLD)</div><div class="t m0 xd h3 y12 ff1 fs0 fc0 sc0 ls0 ws0">A PLD is a general-purpose chip for implementing logic circuit. </div><div class="t m0 xd h3 y13 ff1 fs0 fc0 sc0 ls0 ws0">It contains a collection of logic circuit elements<span class="_ _0"></span> that can be customized in different ways. </div><div class="t m0 xd h3 y14 ff1 fs0 fc0 sc0 ls0 ws0">A PLD can be viewed as a “black box” that contains logic gates and programmable<span class="_ _0"></span> switches.</div><div class="t m0 xd h3 y15 ff1 fs0 fc0 sc0 ls0 ws0">The<span class="_ _3"></span> <span class="_ _3"></span>programmable<span class="_ _3"></span> <span class="_ _3"></span>switches<span class="_ _3"></span> <span class="_ _3"></span>allow<span class="_ _3"></span> <span class="_ _4"></span>the<span class="_ _3"></span> <span class="_ _3"></span>logic<span class="_ _3"></span> <span class="_ _3"></span>gates<span class="_ _3"></span> <span class="_ _4"></span>inside<span class="_ _3"></span> <span class="_ _3"></span>the<span class="_ _3"></span> <span class="_ _3"></span>PLD<span class="_ _3"></span> <span class="_ _3"></span>to<span class="_ _3"></span> <span class="_ _3"></span>be<span class="_ _3"></span> <span class="_ _3"></span>connected<span class="_ _4"></span> <span class="_ _3"></span>together<span class="_ _5"> </span> <span class="_ _3"></span>to</div><div class="t m0 xd h3 y16 ff1 fs0 fc0 sc0 ls0 ws0">implement logic circuits.</div><div class="t m0 xd h3 y17 ff2 fs0 fc0 sc0 ls0 ws0">Programmable logic device as a black box</div><div class="t m0 xd h3 y18 ff2 fs0 fc0 sc0 ls0 ws0">Different types of PLD:</div><div class="t m0 xd h3 y19 ff1 fs0 fc0 sc0 ls0 ws0">1) Simple PLD (SPLD)</div><div class="t m0 xd h3 y1a ff1 fs0 fc0 sc0 ls0 ws0">Programmable logic array (PLA)</div><div class="t m0 xd h3 y1b ff1 fs0 fc0 sc0 ls0 ws0">Programmable array logic (PAL)</div><div class="t m0 xd h3 y1c ff1 fs0 fc0 sc0 ls0 ws0">2)Complex PLD (CPLD)</div><div class="t m0 xd h3 y1d ff1 fs0 fc0 sc0 ls0 ws0">3)Field-programmable gate arrays (FPGA)</div><div class="t m0 xd h3 yf ff3 fs0 fc0 sc0 ls0 ws0">Bhosale S.A. VLSI Design & T<span class="_ _1"></span>echnology<span class="_ _2"> </span><span class="ff1">2</span></div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6287d9feb305d84a4f96d44d/bg3.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">Zeal Education Society’s Dnyanganga College of Engineering<span class="_ _0"></span> & Research, Narhe, Pune</div><div class="t m0 xd h6 y1e ff2 fs3 fc0 sc0 ls0 ws0">Programmable logic array (PLA)</div><div class="t m0 xd h3 y1f ff1 fs0 fc0 sc0 ls0 ws0">PLA is developed based on the sum-of-product form.</div><div class="t m0 xd h3 y20 ff1 fs0 fc0 sc0 ls0 ws0">Figure: General structure of a PLA</div><div class="t m0 xd h3 y21 ff1 fs0 fc0 sc0 ls0 ws0">A<span class="_ _0"></span> <span class="_ _3"></span>PLA <span class="_ _3"></span>includes<span class="_ _0"></span> <span class="_ _0"></span>a<span class="_ _3"></span> circuit<span class="_ _3"></span> block<span class="_ _3"></span> <span class="_ _0"></span>called<span class="_ _0"></span> <span class="_ _3"></span>an<span class="_ _0"></span> <span class="_ _0"></span>AND<span class="_ _3"></span> plane<span class="_ _0"></span> <span class="_ _3"></span>(or<span class="_ _0"></span> <span class="_ _0"></span>AND<span class="_ _3"></span> array)<span class="_ _3"></span> <span class="_ _0"></span>and<span class="_ _0"></span> <span class="_ _0"></span>a<span class="_ _3"></span> circuit<span class="_ _3"></span> <span class="_ _0"></span>block<span class="_ _0"></span> <span class="_ _3"></span>calle<span class="_ _1"></span>d</div><div class="t m0 xd h3 y22 ff1 fs0 fc0 sc0 ls0 ws0">an OR plane (or OR array).</div><div class="t m0 xd h3 y23 ff1 fs0 fc0 sc0 ls0 ws0">Input Buffer/inverters And plane OR plane Output.</div><div class="t m0 xd h3 y24 ff1 fs0 fc0 sc0 ls0 ws0">PLA<span class="_ _3"></span> inputs<span class="_ _3"></span> <span class="_ _0"></span>are<span class="_ _0"></span> <span class="_ _3"></span>x1,x2………………….xn<span class="_ _0"></span> <span class="_ _3"></span>pas<span class="_ _1"></span>s<span class="_ _0"></span> <span class="_ _3"></span>through<span class="_ _0"></span> <span class="_ _3"></span>a<span class="_ _0"></span> <span class="_ _0"></span>set<span class="_ _3"></span> <span class="_ _0"></span>of<span class="_ _0"></span> <span class="_ _3"></span>buffers9which<span class="_ _0"></span> <span class="_ _0"></span>provide<span class="_ _3"></span> <span class="_ _0"></span>both<span class="_ _3"></span> <span class="_ _0"></span>the</div><div class="t m0 xd h3 y25 ff1 fs0 fc0 sc0 ls0 ws0">true value & complement of each i/p)into a circuit block<span class="_ _0"></span> called an AND plane or AND array.</div><div class="t m0 xd h3 y26 ff1 fs0 fc0 sc0 ls0 ws0">AND<span class="_ _3"></span> <span class="_ _4"></span>plane<span class="_ _4"></span> <span class="_ _3"></span>produces<span class="_ _4"></span> <span class="_ _4"></span>a<span class="_ _4"></span> <span class="_ _3"></span>set<span class="_ _4"></span> <span class="_ _4"></span>of<span class="_ _3"></span> <span class="_ _4"></span>product<span class="_ _4"></span> <span class="_ _3"></span>terms<span class="_ _4"></span> <span class="_ _4"></span>p1,p2,p3………………………..pk<span class="_ _3"></span> <span class="_ _4"></span>Each<span class="_ _4"></span> <span class="_ _4"></span>of<span class="_ _3"></span> <span class="_ _4"></span>these</div><div class="t m0 xd h3 y27 ff1 fs0 fc0 sc0 ls0 ws0">terms<span class="_ _5"> </span> <span class="_ _5"> </span>can<span class="_ _5"></span> <span class="_ _6"></span>be<span class="_ _5"> </span> <span class="_ _6"> </span>configured<span class="_ _5"> </span> <span class="_ _5"> </span>to<span class="_ _5"> </span> <span class="_ _6"> </span>implement<span class="_ _5"> </span> <span class="_ _5"> </span>any<span class="_ _5"> </span> <span class="_ _6"> </span>AND<span class="_ _5"> </span> <span class="_ _5"> </span>function<span class="_ _5"> </span> <span class="_ _6"> </span>of<span class="_ _5"> </span> <span class="_ _5"> </span>x1,x2…………………………</div><div class="t m0 xd h3 y28 ff1 fs0 fc0 sc0 ls0 ws0">xn.The<span class="_ _7"> </span> <span class="_ _7"> </span>product<span class="_ _7"> </span> <span class="_ _7"> </span>terms<span class="_ _7"> </span> <span class="_ _7"> </span>serve<span class="_ _7"> </span> <span class="_ _7"> </span>as<span class="_ _7"> </span> <span class="_ _7"> </span>the<span class="_ _7"> </span> <span class="_ _7"> </span>i/p<span class="_ _7"> </span> <span class="_ _7"> </span>to<span class="_ _7"> </span> <span class="_ _7"> </span>an<span class="_ _7"> </span> <span class="_ _7"> </span>OR<span class="_ _7"> </span> <span class="_ _7"> </span>plane<span class="_ _7"> </span> <span class="_ _7"> </span>which<span class="_ _7"> </span> <span class="_ _7"> </span>produces<span class="_ _7"> </span> <span class="_ _7"> </span>o/ps</div><div class="t m0 xd h3 y29 ff1 fs0 fc0 sc0 ls0 ws0">f1,f2…………………………….fm each o/p is configured as sum of products.</div><div class="t m0 xd h3 yf ff3 fs0 fc0 sc0 ls0 ws0">Bhosale S.A. VLSI Design & T<span class="_ _1"></span>echnology<span class="_ _2"> </span><span class="ff1">3</span></div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6287d9feb305d84a4f96d44d/bg4.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">Zeal Education Society’s Dnyanganga College of Engineering<span class="_ _0"></span> & Research, Narhe, Pune</div><div class="t m0 xd h6 y1e ff2 fs3 fc0 sc0 ls0 ws0">Gate-level diagram of a PLA</div><div class="t m0 xd h3 y2a ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xe h6 y2b ff2 fs3 fc0 sc0 ls0 ws0">Programmable array logic (PAL) device<span class="ff1"> </span></div><div class="t m0 xe h3 y2c ff1 fs0 fc0 sc0 ls0 ws0">PAL is a programmable logic device similar to PLA.</div><div class="t m0 xe h3 y2d ff1 fs0 fc0 sc0 ls0 ws0"> Difference between PLA and PAL </div><div class="t m0 xe h3 y2e ff1 fs0 fc0 sc0 ls0 ws0">PLA: both AND plane and OR plane are programmable.</div><div class="t m0 xe h3 y2f ff1 fs0 fc0 sc0 ls0 ws0">PAL: Only AND plane is programmable, while OR plane is fixed.</div><div class="t m0 xe h3 y30 ff1 fs0 fc0 sc0 ls0 ws0">In PLA programmable switches presented two difficulties</div><div class="t m0 xe h3 y31 ff1 fs0 fc0 sc0 ls0 ws0">1)They were hard to fabricate correctly.</div><div class="t m0 xe h3 y32 ff1 fs0 fc0 sc0 ls0 ws0">2)They reduced the speed-performance of circuit implemented in PLAs.</div><div class="t m0 xe h3 y33 ff1 fs0 fc0 sc0 ls0 ws0">These<span class="_ _5"> </span> <span class="_ _5"> </span>drawbacks<span class="_ _5"> </span> <span class="_ _5"> </span>led<span class="_ _5"> </span> <span class="_ _5"> </span>to<span class="_ _5"> </span> <span class="_ _5"> </span>the<span class="_ _5"> </span> <span class="_ _5"> </span>development<span class="_ _8"> </span> <span class="_ _5"> </span>of<span class="_ _5"> </span> <span class="_ _5"> </span>a<span class="_ _5"> </span> <span class="_ _5"> </span>similar<span class="_ _5"> </span> <span class="_ _5"> </span>device<span class="_ _5"> </span> <span class="_ _5"> </span>in<span class="_ _8"> </span> <span class="_ _6"> </span>which<span class="_ _8"> </span> <span class="_ _6"> </span>AND<span class="_ _5"> </span> <span class="_ _5"> </span>plane<span class="_ _8"> </span> <span class="_ _5"> </span>is</div><div class="t m0 xe h3 y34 ff1 fs0 fc0 sc0 ls0 ws0">programmable but OR plane is fixed this is called PAL. </div><div class="t m0 xd h3 yf ff3 fs0 fc0 sc0 ls0 ws0">Bhosale S.A. VLSI Design & T<span class="_ _1"></span>echnology<span class="_ _2"> </span><span class="ff1">4</span></div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6287d9feb305d84a4f96d44d/bg5.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">Zeal Education Society’s Dnyanganga College of Engineering<span class="_ _0"></span> & Research, Narhe, Pune</div><div class="t m0 xd h3 y35 ff1 fs0 fc0 sc0 ls0 ws0">An example of a PAL</div><div class="t m0 xd h6 y36 ff2 fs3 fc0 sc0 ls0 ws0">Comparison between PLA and PAL</div><div class="t m0 xd h3 y37 ff2 fs0 fc0 sc0 ls0 ws0">Drawbacks of PLA</div><div class="t m0 xd h3 y38 ff1 fs0 fc0 sc0 ls0 ws0">1)PLA were hard to be implemented</div><div class="t m0 xd h3 y39 ff1 fs0 fc0 sc0 ls0 ws0">2)PLA reduced the speed performance of circuits. </div><div class="t m0 xd h3 y3a ff2 fs0 fc0 sc0 ls0 ws0">Advantage of PAL</div><div class="t m0 xd h3 y3b ff1 fs0 fc0 sc0 ls0 ws0">1)Simple to manufacturers</div><div class="t m0 xd h3 y3c ff1 fs0 fc0 sc0 ls0 ws0">2)Less expensive</div><div class="t m0 xd h3 y3d ff1 fs0 fc0 sc0 ls0 ws0">3)Better performance</div><div class="t m0 xd h3 y3e ff2 fs0 fc0 sc0 ls0 ws0">Disadvantage of PAL</div><div class="t m0 xd h3 y3f ff1 fs0 fc0 sc0 ls0 ws0">1)Not flexible as compared PLA, because OR plane is fixed </div><div class="t m0 xd h3 yf ff3 fs0 fc0 sc0 ls0 ws0">Bhosale S.A. VLSI Design & T<span class="_ _1"></span>echnology<span class="_ _2"> </span><span class="ff1">5</span></div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
VLSI Notes
