MPC860 Revision D PLL.zip

  • RezaAzad
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  • 2017-10-10 17:07
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The capacitor value of XFC depends on the voltage controlled oscillator (VCO) frequency and the resulting multiplication factor.
MPC860 Revision D PLL.zip
  • MPC860 Revision D PLL.pdf
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6250247374bc5c01055bf893/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250247374bc5c01055bf893/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">The capacitor value of XFC depends on the voltage controlled oscillator (VCO) frequency and</div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws1">the resulting multiplication factor. The larger the capacitor value, the slower the feedback</div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls0 ws2">loop. The MPC860 User&#8217;s Manual (MPC860UM/AD Rev. 1) recommends XFC values</div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls0 ws3">depending on the multiplication factor (MF). If the XFC value is below the recommended</div><div class="t m0 x1 h2 y5 ff1 fs0 fc0 sc0 ls0 ws4">range, the jitter of the VCO output increases. If the XFC value is larger than the recommended</div><div class="t m0 x1 h2 y6 ff1 fs0 fc0 sc0 ls0 ws5">range, the PLL may never achieve lock after system startup. </div><div class="t m0 x1 h3 y7 ff2 fs1 fc0 sc0 ls0 ws5">1.1<span class="_ _0"> </span>Device Nomenclature and Current XFC </div><div class="t m0 x2 h3 y8 ff2 fs1 fc0 sc0 ls1 ws5">Table</div><div class="t m0 x1 h2 y9 ff1 fs0 fc0 sc0 ls0 ws6">The formula in table 15-2 on page 15-8 in the MPC860 Users Manual is valid for all revision</div><div class="t m0 x1 h2 ya ff1 fs0 fc0 sc0 ls0 ws7">C silicon and eariler. The revision of the silicon can be derived from last 2 digits of the part</div><div class="t m0 x1 h2 yb ff1 fs0 fc0 sc0 ls0 ws8">number, e.g. XPC860ENZP66C1 is a C revision silicon. XPC860PZP80D4 is a revision D</div><div class="t m0 x1 h2 yc ff1 fs0 fc0 sc0 ls0 ws5">silicon.</div><div class="t m0 x1 h3 yd ff2 fs1 fc0 sc0 ls0 ws5">1.2<span class="_ _0"> </span>Revision D XFC Implementation</div><div class="t m0 x1 h2 ye ff1 fs0 fc0 sc0 ls0 ws9">Due to the change of manufacturing technology used for revision D silicon, a revised set of</div><div class="t m0 x1 h2 yf ff1 fs0 fc0 sc0 ls0 wsa">formula must be used to calculate the appropriate XFC value. The XFC values are larger for</div><div class="t m0 x1 h2 y10 ff1 fs0 fc0 sc0 ls0 wsb">revision D compared to revision C formula to obtain lower jitter. For systems which are</div><div class="t m0 x1 h2 y11 ff1 fs0 fc0 sc0 ls0 wsc">migrating from revision C to revision D, the XFC capacitor value may need to change, to &#64257;t</div><div class="t m0 x1 h2 y12 ff1 fs0 fc0 sc0 ls0 wsd">within the new calculation ranges. It may be possible to go from a revision C to a revision D</div><div class="t m0 x1 h2 y13 ff1 fs0 fc0 sc0 ls0 wse">MPC860 without changing the XFC value. However, the system must have timing margins of</div><div class="t m0 x1 h2 y14 ff1 fs0 fc0 sc0 ls0 wsf">at least 2.0 ns on all propogation delay values of the bus signals, especially of SDRAM signals.</div><div class="t m0 x1 h2 y15 ff1 fs0 fc0 sc0 ls2 ws5">Table 1 shows the revised XFC formula for revision D silicon and later.</div><div class="t m0 x3 h4 y16 ff2 fs2 fc0 sc0 ls0 ws10">Table 1. <span class="fs3 ws11">XFC Capacitor Value for Revision D Silicon and later Based on </span></div><div class="t m0 x4 h4 y17 ff2 fs3 fc0 sc0 ls0 ws5">PLPRCR[MF]<span class="fs2">.</span></div><div class="t m0 x5 h5 y18 ff3 fs2 fc0 sc0 ls0 ws5">MF Range<span class="_ _1"> </span>Minimum Capacitance<span class="_ _2"> </span>Maximum Capacitance<span class="_ _3"> </span>Unit</div><div class="t m0 x5 h5 y19 ff3 fs2 fc0 sc0 ls0 ws5">1 &lt;= (MF+1) &lt;= 4<span class="_ _4"> </span>XFC = [(MF+1) x 580] - 100<span class="_ _5"> </span>XFC = [(MF+1) x 780] - 140<span class="_ _5"> </span>pF</div><div class="t m0 x5 h5 y1a ff3 fs2 fc0 sc0 ls0 ws5">(MF+1) &gt; 4<span class="_ _6"> </span>XFC = (MF+1) x 830<span class="_ _7"> </span>XFC = (MF+1) x 1470<span class="_ _8"> </span>pF</div><div class="t m0 x6 h6 y1b ff4 fs3 fc1 sc0 ls3 ws5">Advance Information</div><div class="t m0 x6 h7 y1c ff5 fs0 fc1 sc0 ls4 ws5">AN2181/D</div><div class="t m0 x6 h7 y1d ff5 fs0 fc1 sc0 ls5 ws5">Rev. 0.1, 11/2001</div><div class="t m0 x6 h7 y1e ff5 fs0 fc1 sc0 ls6 ws5">MPC860 Revision D PLL </div><div class="t m0 x6 h7 y1f ff5 fs0 fc1 sc0 ls7 ws5">Considerations</div><div class="t m0 x6 h8 y1 ff6 fs0 fc0 sc0 ls0 ws5">Michael Drozd</div><div class="t m0 x6 h8 y2 ff6 fs0 fc0 sc0 ls0 ws5">NCSG Applications</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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