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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626bcf147ae5df2aa719d3f8/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">EC2357 VLSI DESIGN</div><div class="t m0 x2 h3 y3 ff1 fs0 fc0 sc0 ls0 ws0">LIST OF EXPERIMENT</div><div class="t m0 x3 h3 y4 ff1 fs0 fc0 sc0 ls0 ws0">EXPERIMENT USING ALTERA (QUARTUS II)</div><div class="t m0 x4 h3 y5 ff1 fs0 fc0 sc0 ls0 ws0">(Simulation , Synthesis report, Floorplaning, Place & Route, Gate counts )</div><div class="t m0 x4 h4 y6 ff2 fs0 fc0 sc0 ls0 ws0">1. Design and simulation of 8-bit adder (gate level model & dataflow model)</div><div class="t m0 x4 h4 y7 ff2 fs0 fc0 sc0 ls0 ws0">2. Design and simulation of 4:1 MUX and 1:4 DEMUX</div><div class="t m0 x4 h4 y8 ff2 fs0 fc0 sc0 ls0 ws0">3. Design and simulation of Booth Multiplier</div><div class="t m0 x4 h4 y9 ff2 fs0 fc0 sc0 ls0 ws0">4. Design and simulation of Encoder and Decoder</div><div class="t m0 x4 h4 ya ff2 fs0 fc0 sc0 ls0 ws0">5. Design and simulation of UP/DOWN counter</div><div class="t m0 x4 h4 yb ff2 fs0 fc0 sc0 ls0 ws0">6. Design and simulation of flip-flops</div><div class="t m0 x4 h4 yc ff2 fs0 fc0 sc0 ls0 ws0">7. Design and simulation of PRBS generator</div><div class="t m0 x4 h4 yd ff2 fs0 fc0 sc0 ls0 ws0">8. Design and simulation of Accumulator</div><div class="t m0 x4 h3 ye ff1 fs0 fc0 sc0 ls0 ws0">EXPERIMENT USING TANNER/ CADENCE</div><div class="t m0 x4 h4 yf ff2 fs0 fc0 sc0 ls0 ws0">9. <span class="_ _0"></span>SPICE simul<span class="_ _0"></span>ation of<span class="_ _0"></span> MOS <span class="_ _0"></span>differential <span class="_ _0"></span>amplifier. <span class="_ _0"></span>Determination of<span class="_ _0"></span> gain,<span class="_ _0"></span> band<span class="_ _0"></span> width, <span class="_ _0"></span>output <span class="_ _0"></span>impedance</div><div class="t m0 x4 h4 y10 ff2 fs0 fc0 sc0 ls0 ws0">and CMRR. </div><div class="t m0 x4 h4 y11 ff2 fs0 fc0 sc0 ls0 ws0">10. SPICE simulation of CMOS inverter and verify its DC characteristics.</div><div class="t m0 x4 h4 y12 ff2 fs0 fc0 sc0 ls0 ws0">11. Layout design of CMOS Inverter</div><div class="t m0 x4 h4 y13 ff2 fs0 fc0 sc0 ls0 ws0">12. Layout design of CMOS 2input NAND, 2input NOR</div><div class="t m0 x4 h3 y14 ff1 fs0 fc0 sc0 ls0 ws0">Additional Experiments </div><div class="t m0 x4 h4 y15 ff2 fs0 fc0 sc0 ls0 ws0">1. Developing coding for various combinational and sequential circuits .</div><div class="t m0 x4 h4 y16 ff2 fs0 fc0 sc0 ls0 ws0">2. Developing coding for various arithmetic algorithms.</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626bcf147ae5df2aa719d3f8/bg2.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x4 h5 y17 ff1 fs1 fc0 sc0 ls0 ws0">EX. NO. <span class="_ _1"> </span>DESIGN AND SIMULATION OF 4 BIT UP DOWN COUNTER</div><div class="t m0 x4 h5 y18 ff1 fs1 fc0 sc0 ls0 ws0">DATE</div><div class="t m0 x4 h5 y19 ff1 fs1 fc0 sc0 ls0 ws0">AIM</div><div class="t m0 x5 h6 y1a ff2 fs1 fc0 sc0 ls0 ws0">To<span class="_ _2"></span> <span class="_ _2"></span>Design<span class="_ _2"></span> <span class="_ _2"></span>And<span class="_ _0"></span> <span class="_ _2"></span>Implement<span class="_ _2"></span> <span class="_ _2"></span>4<span class="_ _2"></span> <span class="_ _2"></span>Bit<span class="_ _2"></span> <span class="_ _2"></span>Up<span class="_ _2"></span> <span class="_ _2"></span>Down<span class="_ _0"></span> <span class="_ _2"></span>Counter<span class="_ _2"></span> <span class="_ _2"></span>Using<span class="_ _2"></span> <span class="_ _2"></span>Verilog<span class="_ _2"></span> <span class="_ _2"></span>HDL<span class="_ _2"></span> <span class="_ _2"></span>And<span class="_ _0"></span> <span class="_ _2"></span>Observe</div><div class="t m0 x4 h6 y1b ff2 fs1 fc0 sc0 ls0 ws0">The Output waveform.</div><div class="t m0 x4 h5 y1c ff1 fs1 fc0 sc0 ls0 ws0">PROGRAM</div><div class="t m0 x4 h6 y1d ff2 fs1 fc0 sc0 ls0 ws0">module counter (count, clk, k);</div><div class="t m0 x4 h6 y1e ff2 fs1 fc0 sc0 ls0 ws0">input clk,k;</div><div class="t m0 x4 h6 y1f ff2 fs1 fc0 sc0 ls0 ws0">output[3:0] count;</div><div class="t m0 x4 h6 y20 ff2 fs1 fc0 sc0 ls0 ws0">reg count = 4'b0000;</div><div class="t m0 x4 h6 y21 ff2 fs1 fc0 sc0 ls0 ws0">always @ (posedge clk)</div><div class="t m0 x4 h6 y22 ff2 fs1 fc0 sc0 ls0 ws0">if (k==0)</div><div class="t m0 x4 h6 y23 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x5 h6 y24 ff2 fs1 fc0 sc0 ls0 ws0">count = count+1;<span class="_ _3"> </span>// up count</div><div class="t m0 x4 h6 y25 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y26 ff2 fs1 fc0 sc0 ls0 ws0">else</div><div class="t m0 x4 h6 y27 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x5 h6 y28 ff2 fs1 fc0 sc0 ls0 ws0">count=count-1;<span class="_ _4"> </span>//down count</div><div class="t m0 x4 h6 y29 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y2a ff2 fs1 fc0 sc0 ls0 ws0">end module</div><div class="t m0 x4 h5 y2b ff1 fs1 fc0 sc0 ls0 ws0">// TEST BENCH PROGRAM</div><div class="t m0 x4 h6 y2c ff2 fs1 fc0 sc0 ls0 ws0">module testbench();</div><div class="t m0 x4 h6 y2d ff2 fs1 fc0 sc0 ls0 ws0">wire[3:0] count;</div><div class="t m0 x4 h6 y2e ff2 fs1 fc0 sc0 ls0 ws0">reg clk,k;</div><div class="t m0 x4 h6 y2f ff2 fs1 fc0 sc0 ls0 ws0">counter countt(count, clk, k);</div><div class="t m0 x4 h6 y30 ff2 fs1 fc0 sc0 ls0 ws0">initial</div><div class="t m0 x4 h6 y31 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x4 h6 y32 ff2 fs1 fc0 sc0 ls0 ws0">clk=0;</div><div class="t m0 x4 h6 y33 ff2 fs1 fc0 sc0 ls0 ws0">forever #10 clk=~clk;</div><div class="t m0 x4 h6 y34 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y35 ff2 fs1 fc0 sc0 ls0 ws0">initial</div><div class="t m0 x4 h6 y36 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x5 h6 y37 ff2 fs1 fc0 sc0 ls0 ws0">k=1;</div><div class="t m0 x4 h6 y38 ff2 fs1 fc0 sc0 ls0 ws0">#150 k=0;</div><div class="t m0 x4 h6 y39 ff2 fs1 fc0 sc0 ls0 ws0">#100 $finish;</div><div class="t m0 x4 h6 y3a ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y3b ff2 fs1 fc0 sc0 ls0 ws0">endmodule</div><div class="t m0 x4 h5 y3c ff1 fs1 fc0 sc0 ls0 ws0">RESULT</div><div class="t m0 x5 h6 y3d ff2 fs1 fc0 sc0 ls0 ws0">Thus<span class="_ _2"></span> <span class="_ _0"></span>the<span class="_ _2"></span> <span class="_ _2"></span>design<span class="_ _2"></span> <span class="_ _0"></span>and<span class="_ _2"></span> <span class="_ _2"></span>simulation<span class="_ _2"></span> <span class="_ _2"></span>of<span class="_ _0"></span> <span class="_ _2"></span>4<span class="_ _2"></span> <span class="_ _0"></span>bit<span class="_ _2"></span> <span class="_ _2"></span>up<span class="_ _2"></span> <span class="_ _0"></span>down<span class="_ _2"></span> <span class="_ _2"></span>counter<span class="_ _2"></span> <span class="_ _0"></span>using<span class="_ _2"></span> <span class="_ _2"></span>Verilog<span class="_ _2"></span> <span class="_ _0"></span>HDL<span class="_ _2"></span> <span class="_ _2"></span>has<span class="_ _2"></span> <span class="_ _0"></span>been</div><div class="t m0 x4 h6 y3e ff2 fs1 fc0 sc0 ls0 ws0">implemented successfully.</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626bcf147ae5df2aa719d3f8/bg3.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x4 h5 y17 ff1 fs1 fc0 sc0 ls0 ws0">EX. NO. <span class="_ _5"> </span>DESIGN AND SIMULATION OF RING COUNTER</div><div class="t m0 x4 h5 y18 ff1 fs1 fc0 sc0 ls0 ws0">DATE</div><div class="t m0 x4 h5 y19 ff1 fs1 fc0 sc0 ls0 ws0">AIM</div><div class="t m0 x5 h6 y1a ff2 fs1 fc0 sc0 ls0 ws0">To<span class="_ _6"></span> <span class="_ _6"></span>design<span class="_ _6"></span> <span class="_ _6"></span>and<span class="_ _6"></span> <span class="_ _6"></span>implement<span class="_ _6"></span> <span class="_ _6"></span>Ring<span class="_ _6"></span> <span class="_ _6"></span>Counter<span class="_ _6"></span> <span class="_ _6"> </span>Using<span class="_ _6"></span> <span class="_ _6"></span>Verilog<span class="_ _6"></span> <span class="_ _6"></span>HDL<span class="_ _6"> </span> <span class="_ _6"> </span>and<span class="_ _6"></span> <span class="_ _6"> </span>observe<span class="_ _6"> </span> <span class="_ _6"> </span>the<span class="_ _6"> </span> <span class="_ _6"> </span>output</div><div class="t m0 x4 h6 y1b ff2 fs1 fc0 sc0 ls0 ws0">waveform.</div><div class="t m0 x4 h5 y1c ff1 fs1 fc0 sc0 ls0 ws0">PROGRAM</div><div class="t m0 x4 h6 y3f ff2 fs1 fc0 sc0 ls0 ws0">module ring(clk,init,count)</div><div class="t m0 x4 h6 y1d ff2 fs1 fc0 sc0 ls0 ws0">input clk, init;</div><div class="t m0 x4 h6 y1e ff2 fs1 fc0 sc0 ls0 ws0">output [7:0] count;</div><div class="t m0 x4 h6 y1f ff2 fs1 fc0 sc0 ls0 ws0">reg [7:0] count;</div><div class="t m0 x4 h6 y20 ff2 fs1 fc0 sc0 ls0 ws0">always @ (posedge clk)</div><div class="t m0 x4 h6 y21 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x5 h6 y22 ff2 fs1 fc0 sc0 ls0 ws0">if(init)</div><div class="t m0 x4 h6 y23 ff2 fs1 fc0 sc0 ls0 ws0">count=8'b10000000;</div><div class="t m0 x5 h6 y24 ff2 fs1 fc0 sc0 ls0 ws0">else begin</div><div class="t m0 x6 h6 y25 ff2 fs1 fc0 sc0 ls0 ws0">count=count<<1;</div><div class="t m0 x6 h6 y26 ff2 fs1 fc0 sc0 ls0 ws0">count[0]=count[7];</div><div class="t m0 x6 h6 y27 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x5 h6 y28 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y29 ff2 fs1 fc0 sc0 ls0 ws0">endmodule</div><div class="t m0 x4 h5 y40 ff1 fs1 fc0 sc0 ls0 ws0">// TEST BENCH PROGRAM</div><div class="t m0 x4 h6 y41 ff2 fs1 fc0 sc0 ls0 ws0">module testbench();</div><div class="t m0 x4 h6 y2c ff2 fs1 fc0 sc0 ls0 ws0">reg clk, init;</div><div class="t m0 x4 h6 y2d ff2 fs1 fc0 sc0 ls0 ws0">wire [7:0] count;</div><div class="t m0 x4 h6 y2e ff2 fs1 fc0 sc0 ls0 ws0">ring ringt(clk,init,count);</div><div class="t m0 x4 h6 y2f ff2 fs1 fc0 sc0 ls0 ws0">initial</div><div class="t m0 x4 h6 y30 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x5 h6 y31 ff2 fs1 fc0 sc0 ls0 ws0">clk=0;</div><div class="t m0 x5 h6 y32 ff2 fs1 fc0 sc0 ls0 ws0">forever #10 clk=~clk;</div><div class="t m0 x4 h6 y33 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y34 ff2 fs1 fc0 sc0 ls0 ws0">#100 $finish;</div><div class="t m0 x4 h6 y35 ff2 fs1 fc0 sc0 ls0 ws0">end</div><div class="t m0 x4 h6 y36 ff2 fs1 fc0 sc0 ls0 ws0">endmodule</div><div class="t m0 x4 h5 y38 ff1 fs1 fc0 sc0 ls0 ws0">RESULT</div><div class="t m0 x5 h6 y3a ff2 fs1 fc0 sc0 ls0 ws0">Thus the design and simulation<span class="_ _0"></span> of ring counter using <span class="_ _0"></span>Verilog HDL has been implemented</div><div class="t m0 x4 h6 y3b ff2 fs1 fc0 sc0 ls0 ws0">successfully.</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626bcf147ae5df2aa719d3f8/bg4.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x4 h5 y17 ff1 fs1 fc0 sc0 ls0 ws0">EX. NO. <span class="_ _5"> </span>DESIGN AND SIMULATION OF FLIP FLOPS</div><div class="t m0 x4 h5 y18 ff1 fs1 fc0 sc0 ls0 ws0">DATE</div><div class="t m0 x4 h5 y19 ff1 fs1 fc0 sc0 ls0 ws0">AIM</div><div class="t m0 x5 h6 y1a ff2 fs1 fc0 sc0 ls0 ws0">To<span class="_ _2"></span> <span class="_ _2"></span>design<span class="_ _2"></span> <span class="_ _2"></span>and<span class="_ _0"></span> <span class="_ _6"></span>i<span class="_ _7"></span>mplement<span class="_ _2"></span> <span class="_ _2"></span>of<span class="_ _2"></span> <span class="_ _2"></span>FLIP<span class="_ _2"></span> <span class="_ _0"></span>FLOPS<span class="_ _2"></span> <span class="_ _2"></span>Using<span class="_ _2"></span> <span class="_ _2"></span>Verilog<span class="_ _2"></span> <span class="_ _2"></span>HDL<span class="_ _2"></span> <span class="_ _2"></span>and<span class="_ _2"></span> <span class="_ _0"></span>observe<span class="_ _2"></span> <span class="_ _2"></span>the<span class="_ _2"></span> <span class="_ _2"></span>output</div><div class="t m0 x4 h6 y1b ff2 fs1 fc0 sc0 ls0 ws0">waveform.</div><div class="t m0 x4 h5 y1c ff1 fs1 fc0 sc0 ls0 ws0">PROGRAM</div><div class="t m0 x4 h5 y3f ff1 fs1 fc0 sc0 ls0 ws0">//J-K FLIP FLOP</div><div class="t m0 x4 h6 y1e ff2 fs1 fc0 sc0 ls0 ws0">module jkff (j,k,qn, qnext);</div><div class="t m0 x4 h6 y1f ff2 fs1 fc0 sc0 ls0 ws0">input j,k,qn;</div><div class="t m0 x4 h6 y20 ff2 fs1 fc0 sc0 ls0 ws0">output qnext;</div><div class="t m0 x4 h6 y21 ff2 fs1 fc0 sc0 ls0 ws0">always@(j or k or qn);</div><div class="t m0 x4 h6 y22 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x4 h6 y23 ff2 fs1 fc0 sc0 ls0 ws0">if (j==0 & k==0)</div><div class="t m0 x5 h6 y24 ff2 fs1 fc0 sc0 ls0 ws0">qnext=qn;</div><div class="t m0 x4 h6 y25 ff2 fs1 fc0 sc0 ls0 ws0">elseif (j==0 & k==1)</div><div class="t m0 x5 h6 y26 ff2 fs1 fc0 sc0 ls0 ws0">qnext=0;</div><div class="t m0 x4 h6 y27 ff2 fs1 fc0 sc0 ls0 ws0">elseif(j==1 &k ==0)</div><div class="t m0 x5 h6 y28 ff2 fs1 fc0 sc0 ls0 ws0">qnext=1;</div><div class="t m0 x4 h6 y29 ff2 fs1 fc0 sc0 ls0 ws0">elseif(j==1&k==1)</div><div class="t m0 x5 h6 y2a ff2 fs1 fc0 sc0 ls0 ws0">qnext=~qn;</div><div class="t m0 x4 h6 y40 ff2 fs1 fc0 sc0 ls0 ws0">end </div><div class="t m0 x4 h6 y2b ff2 fs1 fc0 sc0 ls0 ws0">endmodule</div><div class="t m0 x4 h5 y2c ff1 fs1 fc0 sc0 ls0 ws0">// TEST BENCH PROGRAM</div><div class="t m0 x4 h6 y2e ff2 fs1 fc0 sc0 ls0 ws0">module testbench();</div><div class="t m0 x4 h6 y2f ff2 fs1 fc0 sc0 ls0 ws0">reg j,k,qn;</div><div class="t m0 x4 h6 y30 ff2 fs1 fc0 sc0 ls0 ws0">wire qnext;</div><div class="t m0 x4 h6 y31 ff2 fs1 fc0 sc0 ls0 ws0">jkff jkfft(j,k,qn,qnext);</div><div class="t m0 x4 h6 y32 ff2 fs1 fc0 sc0 ls0 ws0">initial</div><div class="t m0 x4 h6 y33 ff2 fs1 fc0 sc0 ls0 ws0">begin</div><div class="t m0 x5 h6 y34 ff2 fs1 fc0 sc0 ls0 ws0">j=0;k=0;qn=0;</div><div class="t m0 x4 h6 y35 ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=0;k=0;qn=1;</div><div class="t m0 x4 h6 y36 ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=0;k=1;qn=0;</div><div class="t m0 x4 h6 y37 ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=0;k=1;qn=1;</div><div class="t m0 x4 h6 y38 ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=1;k=0;qn=0;</div><div class="t m0 x4 h6 y39 ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=1;k=0;qn=1;</div><div class="t m0 x4 h6 y3a ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=1;k=1;qn=0;</div><div class="t m0 x4 h6 y3b ff2 fs1 fc0 sc0 ls0 ws0">#10<span class="_ _8"> </span>j=1;k=1;qn=1;</div><div class="t m0 x4 h6 y42 ff2 fs1 fc0 sc0 ls0 ws0">#50 $finish</div><div class="t m0 x4 h6 y3c ff2 fs1 fc0 sc0 ls0 ws0">end </div><div class="t m0 x4 h6 y3d ff2 fs1 fc0 sc0 ls0 ws0">endmodule</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
