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booth multiplier using booth algorithm
VLSI verilog.rar
  • VLSI DESIGN LAB MANUAL.doc
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/626bcf147ae5df2aa719d3f8/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626bcf147ae5df2aa719d3f8/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">EC2357 VLSI DESIGN</div><div class="t m0 x2 h3 y3 ff1 fs0 fc0 sc0 ls0 ws0">LIST OF EXPERIMENT</div><div class="t m0 x3 h3 y4 ff1 fs0 fc0 sc0 ls0 ws0">EXPERIMENT USING ALTERA (QUARTUS II)</div><div class="t m0 x4 h3 y5 ff1 fs0 fc0 sc0 ls0 ws0">(Simulation , Synthesis report, Floorplaning, Place &amp; Route, Gate counts )</div><div class="t m0 x4 h4 y6 ff2 fs0 fc0 sc0 ls0 ws0">1. Design and simulation of 8-bit adder (gate level model &amp; dataflow model)</div><div class="t m0 x4 h4 y7 ff2 fs0 fc0 sc0 ls0 ws0">2. Design and simulation of 4:1 MUX and 1:4 DEMUX</div><div class="t m0 x4 h4 y8 ff2 fs0 fc0 sc0 ls0 ws0">3. Design and simulation of Booth Multiplier</div><div class="t m0 x4 h4 y9 ff2 fs0 fc0 sc0 ls0 ws0">4. Design and simulation of Encoder and Decoder</div><div class="t m0 x4 h4 ya ff2 fs0 fc0 sc0 ls0 ws0">5. Design and simulation of UP/DOWN counter</div><div class="t m0 x4 h4 yb ff2 fs0 fc0 sc0 ls0 ws0">6. Design and simulation of flip-flops</div><div class="t m0 x4 h4 yc ff2 fs0 fc0 sc0 ls0 ws0">7. Design and simulation of PRBS generator</div><div class="t m0 x4 h4 yd ff2 fs0 fc0 sc0 ls0 ws0">8. Design and simulation of Accumulator</div><div class="t m0 x4 h3 ye ff1 fs0 fc0 sc0 ls0 ws0">EXPERIMENT USING TANNER/ CADENCE</div><div class="t m0 x4 h4 yf ff2 fs0 fc0 sc0 ls0 ws0">9. <span class="_ _0"></span>SPICE simul<span class="_ _0"></span>ation of<span class="_ _0"></span> MOS <span class="_ _0"></span>differential <span class="_ _0"></span>amplifier. <span class="_ _0"></span>Determination of<span class="_ _0"></span> gain,<span class="_ _0"></span> band<span class="_ _0"></span> width, <span class="_ _0"></span>output <span class="_ _0"></span>impedance</div><div class="t m0 x4 h4 y10 ff2 fs0 fc0 sc0 ls0 ws0">and CMRR. </div><div class="t m0 x4 h4 y11 ff2 fs0 fc0 sc0 ls0 ws0">10. SPICE simulation of CMOS inverter and verify its DC characteristics.</div><div class="t m0 x4 h4 y12 ff2 fs0 fc0 sc0 ls0 ws0">11. Layout design of CMOS Inverter</div><div class="t m0 x4 h4 y13 ff2 fs0 fc0 sc0 ls0 ws0">12. Layout design of CMOS 2input NAND, 2input NOR</div><div class="t m0 x4 h3 y14 ff1 fs0 fc0 sc0 ls0 ws0">Additional Experiments </div><div class="t m0 x4 h4 y15 ff2 fs0 fc0 sc0 ls0 ws0">1. Developing coding for various combinational and sequential circuits .</div><div class="t m0 x4 h4 y16 ff2 fs0 fc0 sc0 ls0 ws0">2. Developing coding for various arithmetic algorithms.</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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