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MB86H61 DEVICE MANUAL
MB86H61_DeviceManual.rar
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/62511bc26caf59619238f1e8/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62511bc26caf59619238f1e8/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Device Manual </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 h4 y3 ff2 fs2 fc0 sc0 ls2 ws1">MB86H61 </div><div class="t m0 x1 h5 y4 ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 h6 y5 ff2 fs3 fc0 sc0 ls3 ws2">Multi Standard De<span class="_ _0"></span>coder for Set-Top-B<span class="_ _0"></span>oxes </div><div class="t m0 x1 h7 y6 ff2 fs4 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 h7 y7 ff2 fs4 fc0 sc0 ls1 ws1"> </div><div class="t m0 x2 h8 y8 ff3 fs1 fc0 sc0 ls1 ws1"><span class="fc1 sc0"> </span></div><div class="t m0 x2 h8 y9 ff3 fs1 fc0 sc0 ls4 ws1"> <span class="_ _0"></span> <span class="_ _0"></span> <span class="_ _0"></span> <span class="_ _0"></span> <span class="ff2 ls1"> </span></div><div class="t m0 x1 h8 ya ff3 fs1 fc0 sc0 ls5 ws3">Copyright&#169; 2012 FUJITSU Semiconduct<span class="_ _1"></span>or Europe GmbH <span class="_ _2"> </span>Confidential<span class="_ _1"></span> </div><div class="c x3 yb w2 h9"><div class="t m0 x0 h8 yc ff3 fs1 fc0 sc0 ls1 ws1"> </div></div><div class="t m0 x1 h8 yd ff3 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 ha ye ff3 fs5 fc0 sc0 ls6 ws1">Disclai<span class="_ _1"></span>mer:<span class="_ _1"></span><span class="ff2 ls7 ws4"> <span class="_ _3"> </span>The conte<span class="_ _1"></span>nts of <span class="_ _1"></span>this doc<span class="_ _1"></span>umen<span class="_ _1"></span>t are s<span class="_ _1"></span>ubject t<span class="_ _1"></span>o chan<span class="_ _1"></span>ge with<span class="_ _1"></span>out no<span class="_ _1"></span>tice. Cus<span class="_ _1"></span>tom<span class="_ _1"></span>ers ar<span class="_ _1"></span>e advise<span class="_ _1"></span>d to c<span class="_ _1"></span>onsult <span class="_ _1"></span>with <span class="_ _1"></span>FUJIT<span class="_ _1"></span>SU sales<span class="_ _1"></span> repr<span class="_ _1"></span>es<span class="ls1 ws1">entative<span class="_ _1"></span>s </span></span></div><div class="t m0 x4 hb yf ff2 fs5 fc0 sc0 ls8 ws5">before or<span class="_ _1"></span>deri<span class="_ _1"></span>ng. Th<span class="_ _1"></span>e inform<span class="_ _1"></span>ation<span class="_ _1"></span> and ci<span class="_ _1"></span>rcuit <span class="_ _1"></span>diagr<span class="_ _1"></span>ams in t<span class="_ _1"></span>his doc<span class="_ _1"></span>ument<span class="_ _1"></span> are <span class="_ _1"></span>present<span class="_ _1"></span>ed &#8220;as<span class="_ _1"></span> is&#8221;,<span class="_ _1"></span> no lic<span class="_ _1"></span>ense i<span class="_ _1"></span>s gra<span class="_ _1"></span>nted b<span class="_ _1"></span>y im<span class="_ _1"></span>plicat<span class="ls9 ws6">ion o<span class="_ _1"></span>r othe<span class="_ _1"></span>rwis<span class="_ _1"></span>e. </span></div><div class="t m0 x5 h7 y10 ff2 fs4 fc0 sc0 lsa ws7">April 2<span class="_ _1"></span>012 </div><div class="t m0 x6 h7 y11 ff2 fs4 fc0 sc0 lsb ws8">Edition 1.<span class="_ _1"></span>3 </div><div class="t m0 x7 hc y12 ff2 fs6 fc0 sc0 lsc ws1">IR</div><div class="t m0 x8 hc y13 ff2 fs6 fc0 sc0 lsd ws1">PL<span class="_ _0"></span>L</div><div class="t m0 x9 hc y14 ff2 fs6 fc0 sc0 lse ws1">Wak<span class="_ _0"></span>e</div><div class="t m0 xa hc y15 ff2 fs6 fc0 sc0 lsf ws1">up</div><div class="t m0 xb hc y14 ff2 fs6 fc0 sc0 ls10 ws1">Power</div><div class="t m0 xc hc y15 ff2 fs6 fc0 sc0 ls11 ws1">ctrl</div><div class="t m0 xd hc y16 ff2 fs6 fc0 sc0 ls12 ws9">Po<span class="_ _0"></span>w<span class="_ _0"></span>er I<span class="_ _4"></span>sla<span class="_ _0"></span>nd</div><div class="t m0 xe hc y12 ff2 fs6 fc0 sc0 ls13 ws1">CEC</div><div class="t m0 xf hc y17 ff2 fs6 fc0 sc0 ls14 ws1">36/27M<span class="_ _4"></span>Hz</div><div class="t m0 x10 hc y18 ff2 fs6 fc0 sc0 ls13 wsa">CCIR /</div><div class="t m0 x11 hc y19 ff2 fs6 fc0 sc0 ls15 ws1">SM<span class="_ _4"></span>PT<span class="_ _4"></span>E</div><div class="t m0 x12 hc y1a ff2 fs6 fc0 sc0 lsf ws1">274M</div><div class="t m0 x13 hc y1b ff2 fs6 fc0 sc0 ls16 ws1">4x</div><div class="t m0 x14 hc y1c ff2 fs6 fc0 sc0 lsc ws1">I2S<span class="_ _1"></span> </div><div class="t m0 x15 hc y1d ff2 fs6 fc0 sc0 ls17 ws1">UPI</div><div class="t m0 x16 hc y1e ff2 fs6 fc0 sc0 ls18 ws1">GPI<span class="_ _4"></span>O</div><div class="t m0 x17 hc y1f ff2 fs6 fc0 sc0 ls19 ws1">AT<span class="_ _1"></span>A</div><div class="t m0 x18 hc y20 ff2 fs6 fc0 sc0 ls13 ws1">USB</div><div class="t m0 x18 hc y21 ff2 fs6 fc0 sc0 ls1a ws1">PH<span class="_ _1"></span>Y</div><div class="t m0 x18 hc y22 ff2 fs6 fc0 sc0 ls13 ws1">USB</div><div class="t m0 x18 hc y23 ff2 fs6 fc0 sc0 ls1a ws1">PH<span class="_ _1"></span>Y</div><div class="t m0 x19 hc y24 ff2 fs6 fc0 sc0 ls1b ws1">DM<span class="_ _4"></span>A</div><div class="t m0 x1a hc y25 ff2 fs6 fc0 sc0 ls16 wsb">6 c<span class="_ _4"></span>h<span class="_ _1"></span>anne<span class="_ _1"></span>l</div><div class="t m0 x1b hc y26 ff2 fs6 fc0 sc0 ls1c ws1">Memo<span class="_ _1"></span>ry </div><div class="t m0 x1c hc y27 ff2 fs6 fc0 sc0 ls1d ws1">con<span class="_ _0"></span>tr<span class="_ _4"></span>oller</div><div class="t m0 x1d hc y28 ff2 fs6 fc0 sc0 lsd ws1">SAT<span class="_ _4"></span>A</div><div class="t m0 x18 hc y29 ff2 fs6 fc0 sc0 ls1a ws1">PH<span class="_ _1"></span>Y</div><div class="t m0 x1e hc y2a ff2 fs6 fc0 sc0 ls1e ws1">DMA</div><div class="t m0 x1f hc y2b ff2 fs6 fc0 sc0 ls13 ws1">DDR2</div><div class="t m0 x20 hc y2c ff2 fs6 fc0 sc0 ls16 ws1">800</div><div class="t m1 x21 hc y2d ff2 fs6 fc0 sc0 ls1f ws1">GPI<span class="_ _4"></span>O</div><div class="t m0 x22 hc y2e ff2 fs6 fc0 sc0 ls16 wsc">4 x</div><div class="t m0 x23 hc y2f ff2 fs6 fc0 sc0 ls20 ws1">TSD</div><div class="t m0 x17 hc y30 ff2 fs6 fc0 sc0 ls21 ws1">Descramb<span class="_ _1"></span>ler</div><div class="t m0 x17 hc y31 ff2 fs6 fc0 sc0 ls22 wsd">DVB CS<span class="_ _5"></span>A2.<span class="_ _0"></span>1</div><div class="t m0 x24 hc y32 ff2 fs6 fc0 sc0 ls1d wse">Mu<span class="_ _0"></span>lti 2</div><div class="t m0 x25 hc y33 ff2 fs6 fc0 sc0 ls13 ws1">DES/<span class="_ _4"></span>A<span class="_ _1"></span>ES</div><div class="t m0 x26 hc y2e ff2 fs6 fc0 sc0 ls19 ws1">Buff<span class="_ _1"></span>e<span class="_ _1"></span>r</div><div class="t m0 x19 hc y2f ff2 fs6 fc0 sc0 lsf ws1">Mana<span class="_ _0"></span>ger</div><div class="t m0 x27 hc y34 ff2 fs6 fc0 sc0 ls23 ws1">Audio</div><div class="t m0 x28 hc y35 ff2 fs6 fc0 sc0 ls21 ws1">Dec<span class="_ _1"></span>oder</div><div class="t m0 x29 hc y36 ff2 fs6 fc0 sc0 lsf wsf">4x I<span class="_ _4"></span>2S o<span class="_ _0"></span>ut</div><div class="t m0 x2a hc y37 ff2 fs6 fc0 sc0 ls19 ws1">SP<span class="_ _1"></span>D<span class="_ _1"></span>IF</div><div class="t m1 x2b hc y38 ff2 fs6 fc0 sc0 ls18 ws1">GPI<span class="_ _4"></span>O</div><div class="t m0 x2c hc y39 ff2 fs6 fc0 sc0 lsc ws1">I/P</div><div class="t m0 x2d hc y3a ff2 fs6 fc0 sc0 lsf ws1">Conv<span class="_ _4"></span>erter</div><div class="t m0 x2e hc y3b ff2 fs6 fc0 sc0 ls15 ws1">Vi<span class="_ _4"></span>d<span class="_ _4"></span>eo</div><div class="t m0 x2e hc y3c ff2 fs6 fc0 sc0 ls23 ws1">Scaler</div><div class="t m0 x2f hc y39 ff2 fs6 fc0 sc0 ls13 ws1">Dis<span class="_ _0"></span>play</div><div class="t m0 x30 hc y3a ff2 fs6 fc0 sc0 ls24 ws1">Mix<span class="_ _4"></span>er</div><div class="t m0 x31 hc y3d ff2 fs6 fc0 sc0 lsd ws1">Sca<span class="_ _4"></span>ler</div><div class="t m0 x32 hc y3e ff2 fs6 fc0 sc0 ls25 ws1">(S<span class="_ _1"></span>D<span class="_ _1"></span>)</div><div class="t m0 x33 hc y3f ff2 fs6 fc0 sc0 ls19 ws10">PA<span class="_ _1"></span>L<span class="_ _1"></span> /<span class="_ _1"></span> N<span class="_ _1"></span>T<span class="_ _1"></span>SC</div><div class="t m0 x34 hc y40 ff2 fs6 fc0 sc0 ls1a ws1">SECAM </div><div class="t m0 x34 hc y41 ff2 fs6 fc0 sc0 ls26 ws1">Encoder</div><div class="t m0 x7 hc y42 ff2 fs6 fc0 sc0 ls21 ws11">Digital R<span class="_ _1"></span>GB</div><div class="t m0 x35 hc y36 ff2 fs6 fc0 sc0 ls27 ws1">2D-G<span class="_ _1"></span>raph<span class="_ _1"></span>ic</div><div class="t m0 x35 hc y37 ff2 fs6 fc0 sc0 ls16 ws1">Acce<span class="_ _1"></span>lerator</div><div class="t m0 x1d hc y43 ff2 fs6 fc0 sc0 ls16 wsc">10 B<span class="_ _1"></span>it</div><div class="t m0 x18 hc y44 ff2 fs6 fc0 sc0 ls17 ws1">ADC</div><div class="t m0 x18 hc y45 ff2 fs6 fc0 sc0 ls27 ws1">(fou<span class="_ _1"></span>r </div><div class="t m0 x36 hc y46 ff2 fs6 fc0 sc0 ls28 ws1">chan<span class="_ _4"></span>nel)</div><div class="t m0 x37 hc y18 ff2 fs6 fc0 sc0 ls29 ws1">Fron<span class="_ _0"></span>t</div><div class="t m0 x37 hc y19 ff2 fs6 fc0 sc0 ls19 ws1">Pan<span class="_ _1"></span>e<span class="_ _1"></span>l</div><div class="t m0 x38 hc y1a ff2 fs6 fc0 sc0 ls2a ws12">co<span class="_ _4"></span>n<span class="_ _4"></span>tr<span class="_ _4"></span>ol<span class="_ _4"></span> </div><div class="t m0 x39 hc y1b ff2 fs6 fc0 sc0 ls16 ws1">2x</div><div class="t m0 x3a hc y1c ff2 fs6 fc0 sc0 ls19 ws1">SPI</div><div class="t m0 x3b hc y1b ff2 fs6 fc0 sc0 lsf ws13">2x ISO</div><div class="t m0 x3c hc y1c ff2 fs6 fc0 sc0 ls16 ws1">7816</div><div class="t m0 x3d hc y1b ff2 fs6 fc0 sc0 ls16 ws1">2x</div><div class="t m0 x3e hc y1c ff2 fs6 fc0 sc0 ls21 ws1">UART</div><div class="t m0 x1e hc y1d ff2 fs6 fc0 sc0 ls19 ws1">SDIO</div><div class="t m0 x16 hc y1b ff2 fs6 fc0 sc0 ls21 ws1">NA<span class="_ _1"></span>ND</div><div class="t m0 x3f hc y1c ff2 fs6 fc0 sc0 ls2b ws1">Fl<span class="_ _1"></span>a<span class="_ _1"></span>s<span class="_ _1"></span>h</div><div class="t m0 x40 hc y28 ff2 fs6 fc0 sc0 lsd ws1">SAT<span class="_ _4"></span>A</div><div class="t m0 x22 hc y29 ff2 fs6 fc0 sc0 lsf ws1">LI<span class="_ _0"></span>NK</div><div class="t m0 x41 hc y47 ff2 fs6 fc0 sc0 ls21 ws14">NOR F<span class="_ _1"></span>la<span class="_ _1"></span>sh</div><div class="t m0 x42 hc y48 ff2 fs6 fc0 sc0 ls13 ws1">DVB-<span class="_ _0"></span>CI<span class="_ _4"></span>/<span class="_ _1"></span>CI+</div><div class="t m0 x1a hc y1d ff2 fs6 fc0 sc0 ls15 ws1">SF<span class="_ _4"></span>l<span class="_ _0"></span>a<span class="_ _4"></span>sh</div><div class="t m0 x43 hc y49 ff2 fs6 fc0 sc0 ls2c ws15">Ethernet c<span class="_ _1"></span>o<span class="_ _1"></span>n<span class="_ _0"></span>t<span class="_ _1"></span>roller</div><div class="t m0 x44 hc y4a ff2 fs6 fc0 sc0 lsc ws1">IRQ</div><div class="t m0 x45 hc y4b ff2 fs6 fc0 sc0 ls2d ws1">C<span class="_ _1"></span>o<span class="_ _1"></span>nt<span class="_ _5"></span>ro<span class="_ _1"></span>l<span class="_ _5"></span>ler</div><div class="t m0 x46 hc y4c ff2 fs6 fc0 sc0 ls15 ws1">S-<span class="_ _4"></span>Fl<span class="_ _4"></span>a<span class="_ _4"></span>sh</div><div class="t m0 x47 hc y4d ff2 fs6 fc0 sc0 ls2e ws1">MI<span class="_ _1"></span>I</div><div class="t m0 x48 hc y12 ff2 fs6 fc0 sc0 ls20 ws1">Ti<span class="_ _4"></span>m<span class="_ _1"></span>er</div><div class="t m1 x49 hc y4e ff2 fs6 fc0 sc0 lsf ws13">HDMI Li<span class="_ _4"></span>nk</div><div class="t m1 x2b hc y13 ff2 fs6 fc0 sc0 ls1f ws1">GP<span class="_ _4"></span>IO</div><div class="t m0 x4a hc y4f ff2 fs6 fc0 sc0 ls13 ws1">CVBS</div><div class="t m0 x4a hc y50 ff2 fs6 fc0 sc0 ls1a ws1">Y/C</div><div class="t m0 x4a hc y51 ff2 fs6 fc0 sc0 ls2f ws1">RGB</div><div class="t m0 x4b hc y52 ff2 fs6 fc0 sc0 lsd ws1">YPb<span class="_ _4"></span>Pr</div><div class="t m0 x4b hc y53 ff2 fs6 fc0 sc0 ls21 ws1">RGB</div><div class="t m0 x4a hc y54 ff2 fs6 fc0 sc0 ls13 ws16">HDMI<span class="_ _0"></span> 1.<span class="_ _4"></span>3</div><div class="t m0 x4c hc y55 ff2 fs6 fc0 sc0 lsd ws1">Aud<span class="_ _4"></span>i<span class="_ _0"></span>o</div><div class="t m0 x4d hc y56 ff2 fs6 fc0 sc0 ls30 ws1">L/R</div><div class="t m0 x4e hc y57 ff2 fs6 fc0 sc0 ls31 ws17">USB 2.0</div><div class="t m0 x4f hc y58 ff2 fs6 fc0 sc0 ls32 ws1">Host/f<span class="_ _1"></span>unction</div><div class="t m0 x50 hc y59 ff2 fs6 fc0 sc0 ls19 ws1">SAT<span class="_ _1"></span>A</div><div class="t m0 x4f hc y5a ff2 fs6 fc0 sc0 ls23 ws1">eSATA</div><div class="t m0 x51 hc y39 ff2 fs6 fc0 sc0 ls33 ws1">Video </div><div class="t m0 x52 hc y3a ff2 fs6 fc0 sc0 ls34 ws1">Dec<span class="_ _1"></span>oder</div><div class="t m0 x37 hc y26 ff2 fs6 fc0 sc0 ls35 ws18">BO<span class="_ _1"></span>O<span class="_ _1"></span>T<span class="_ _1"></span> RO<span class="_ _5"></span>M <span class="_ _1"></span>/</div><div class="t m0 x53 hc y27 ff2 fs6 fc0 sc0 lsc ws1">In<span class="_ _1"></span>te<span class="_ _1"></span>rn<span class="_ _1"></span>a<span class="_ _1"></span>l<span class="_ _1"></span> R<span class="_ _1"></span>A<span class="_ _1"></span>M</div><div class="t m0 x54 hc y5b ff2 fs6 fc0 sc0 ls19 ws1">PW<span class="_ _1"></span>M</div><div class="t m0 x55 hc y34 ff2 fs6 fc0 sc0 ls36 ws19">4 x OSD, Cursor </div><div class="t m0 x56 hc y35 ff2 fs6 fc0 sc0 lsf ws1a">(wi<span class="_ _0"></span>th S<span class="_ _0"></span>ca<span class="_ _0"></span>ler<span class="_"> </span>f<span class="_ _4"></span>unction)</div><div class="t m0 x35 hc y1b ff2 fs6 fc0 sc0 lsf ws1">2x</div><div class="t m0 x35 hc y1c ff2 fs6 fc0 sc0 ls37 ws1">I2<span class="_ _1"></span>C</div><div class="t m0 x57 hc y5c ff2 fs6 fc0 sc0 ls38 ws1">AR<span class="_ _1"></span>M1176</div><div class="t m1 x49 hc y5d ff2 fs6 fc0 sc0 ls1e ws1">MUX</div><div class="t m0 x58 hc y5e ff2 fs6 fc0 sc0 lsf wsf">3 x <span class="_ _4"></span>Vi<span class="_ _0"></span>deo </div><div class="t m0 x59 hc y5f ff2 fs6 fc0 sc0 ls13 wsa">DAC<span class="_ _4"></span> S<span class="_ _1"></span>D</div><div class="t m0 x58 hc y60 ff2 fs6 fc0 sc0 lsf wsf">3 x <span class="_ _4"></span>Vi<span class="_ _0"></span>deo </div><div class="t m0 x59 hc y61 ff2 fs6 fc0 sc0 ls13 wsa">DAC HD</div><div class="t m0 x5a hc y62 ff2 fs6 fc0 sc0 ls21 ws1">HDM<span class="_ _1"></span>I</div><div class="t m0 x5b hc y63 ff2 fs6 fc0 sc0 ls36 ws1b">(<span class="_ _1"></span>with HDCP<span class="_ _5"></span>)</div><div class="t m0 x5c hc y64 ff2 fs6 fc0 sc0 lsf ws1">Ster<span class="_ _4"></span>eo</div><div class="t m0 x5a hc y65 ff2 fs6 fc0 sc0 lsd ws1">Aud<span class="_ _4"></span>i<span class="_ _0"></span>o</div><div class="t m0 x5d hc y66 ff2 fs6 fc0 sc0 ls21 ws1">DAC</div><div class="t m0 xd hc y67 ff2 fs6 fc0 sc0 ls21 ws11">CCIR 656</div><div class="t m0 x1 hd y68 ff4 fs1 fc0 sc0 ls39 ws1">INTR<span class="_ _1"></span>ODU<span class="_ _1"></span>CTI<span class="_ _1"></span>ON<span class="_ _1"></span> </div><div class="t m0 x1 he y69 ff4 fs7 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 hd y6a ff2 fs1 fc0 sc0 ls3a ws1">The <span class="ff4 ls3b">M<span class="_ _1"></span>B86H61</span><span class="ls3c ws1c"> is<span class="_ _1"></span> a highly integrated HD Multi-S<span class="_ _1"></span>tandard Digit<span class="_ _1"></span>al </span></div><div class="t m0 x1 h5 y6b ff2 fs1 fc0 sc0 ls3d ws1d">Television Dec<span class="_ _1"></span>oder designed t<span class="_ _1"></span>o meet the needs of<span class="_ _1"></span> tomorrow&#8217;s </div><div class="t m0 x1 hd y6c ff2 fs1 fc0 sc0 ls5 ws1e">HD set-top-box and IDTV m<span class="_ _1"></span>arket featuring <span class="ff4 ls3e ws1">CI<span class="_ _1"></span>+</span><span class="ls3f ws1f"> or embedded </span></div><div class="t m0 x1 hd y6d ff2 fs1 fc0 sc0 ls40 ws20">CAS for <span class="ff4 ls41 ws21">advanced secur<span class="_ _4"></span>i<span class="_ _1"></span>ty<span class="ff2 ls42 ws22">. The MB86H61 is a singl<span class="_ _1"></span>e-chip </span></span></div><div class="t m0 x1 h5 y6e ff2 fs1 fc0 sc0 ls43 ws23">video decoder support<span class="_ _1"></span>ing H.264 / AVC, MPEG-2, AVS<span class="_ _1"></span> and </div><div class="t m0 x1 h5 y6f ff2 fs1 fc0 sc0 ls44 ws24">VC-1 video decoding up t<span class="_ _1"></span>o high defini<span class="_ _1"></span>tion resolut<span class="_ _1"></span>ion with up to </div><div class="t m0 x1 hd y70 ff4 fs1 fc0 sc0 ls45 ws1">1080p<span class="ff2 ls46 ws25"> 50/60Hz output. </span></div><div class="t m0 x1 h5 y71 ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 hd y72 ff2 fs1 fc0 sc0 ls3f ws26">A high performance <span class="_ _1"></span><span class="ff4 ls47 ws27">A<span class="_ _0"></span>RM 1176JZF-S</span></div><div class="t m0 x5e hf y73 ff4 fs8 fc0 sc0 ls48 ws1">TM</div><div class="t m0 x5f h5 y74 ff2 fs1 fc0 sc0 ls49 ws28"> CP<span class="_ _1"></span>U wit<span class="_ _1"></span>h<span class="_ _1"></span> m<span class="_ _1"></span>or<span class="_ _1"></span>e t<span class="_ _1"></span>ha<span class="_ _1"></span>n </div><div class="t m0 x1 h5 y75 ff2 fs1 fc0 sc0 ls3f ws29">475DMIPS, a 16kB<span class="_ _1"></span> data and instruc<span class="_ _1"></span>tion c<span class="_ _1"></span>aches and TCM is </div><div class="t m0 x1 h5 y76 ff2 fs1 fc0 sc0 ls3d ws2a">included.<span class="_ _1"></span> The CPU features an integrated memory </div><div class="t m0 x1 h5 y77 ff2 fs1 fc0 sc0 ls5 ws2b">management unit and a f<span class="_ _1"></span>loating point co-process<span class="_ _1"></span>or. The chip </div><div class="t m0 x1 h5 y78 ff2 fs1 fc0 sc0 ls3c ws2c">uses t<span class="_ _1"></span>wo DDR2 interfaces<span class="_ _1"></span> in shared memory arc<span class="_ _1"></span>hitectu<span class="_ _1"></span>re. </div><div class="t m0 x1 hd y79 ff2 fs1 fc0 sc0 ls3f ws2d">Also integrat<span class="_ _1"></span>ed is a <span class="ff4 ls4a ws2e">2D graph<span class="_ _4"></span>i<span class="_ _1"></span>c engine<span class="_ _0"></span><span class="ff2 ls4b ws2f"> to ac<span class="_ _0"></span>celer<span class="_ _0"></span>ate O<span class="_ _0"></span>SD. </span></span></div><div class="t m0 x1 h5 y7a ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 h5 y7b ff2 fs1 fc0 sc0 ls44 ws30">An advanced, program<span class="_ _1"></span>mable audio proc<span class="_ _1"></span>essor solut<span class="_ _1"></span>ion offers </div><div class="t m0 x1 h5 y7c ff2 fs1 fc0 sc0 ls41 ws31">full flexibility. It is c<span class="_ _1"></span>apable of decoding MPEG1 layer 1, 2 and <span class="_ _1"></span>3 </div><div class="t m0 x1 h5 y7d ff2 fs1 fc0 sc0 ls4c ws32">(MP3), HE-AAC,<span class="_ _1"></span> Dolby Digital (planning) and Dol<span class="_ _1"></span>by Digital </div><div class="t m0 x1 h5 y7e ff2 fs1 fc0 sc0 ls3d ws33">plus (planning).<span class="_ _1"></span> Available audi<span class="_ _1"></span>o outputs are 4x I&#178;S from<span class="_ _1"></span> 8kHz </div><div class="t m0 x1 h5 y7f ff2 fs1 fc0 sc0 ls3c ws34">to 192kHz, SPDIF and stereo audio DAC. </div><div class="t m0 x1 h5 y80 ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 h5 y81 ff2 fs1 fc0 sc0 ls3f ws35">The TV or display can be connect<span class="_ _1"></span>ed in HD resolution anal<span class="_ _1"></span>og <span class="_ _6"></span> </div><div class="t m0 x1 hd y82 ff2 fs1 fc0 sc0 ls43 ws36">via component<span class="_ _1"></span> output or digital via c<span class="_ _1"></span>opy protect<span class="_ _1"></span>ed <span class="ff4 ls3e ws1">HDMI<span class="ff2 ls1"> </span></span></div><div class="t m0 x1 h5 y83 ff2 fs1 fc0 sc0 ls3d ws37">interfac<span class="_ _1"></span>e. A down-sampl<span class="_ _1"></span>ed SD format can be provided in<span class="_ _1"></span> </div><div class="t m0 x1 h5 y84 ff2 fs1 fc0 sc0 ls3b ws38">parallel. A<span class="_ _1"></span>dditionally the decoded video can be out<span class="_ _1"></span>put via </div><div class="t m0 x1 h5 y85 ff2 fs1 fc0 sc0 ls46 ws25">CCIR656 (SD) or SMPTE 296M/274M (HD). </div><div class="t m0 x1 h5 y86 ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 hd y87 ff2 fs1 fc0 sc0 ls5 ws39">The MB86H61 supports<span class="_ _1"></span> <span class="ff4 ls4d ws3a">eSATA/S<span class="_ _1"></span>ATA<span class="_ _0"></span> 3Gb/s<span class="ff2 ls3b ws3b"> interf<span class="_ _1"></span>ace for </span></span></div><div class="t m0 x1 hd y88 ff2 fs1 fc0 sc0 ls3b ws3c">external hard disk dri<span class="_ _1"></span>ves and <span class="ff4 ls4e ws1">SDIO</span><span class="ls4f ws3d"> e.g. for SDHC memory </span></div><div class="t m0 x1 hd y89 ff2 fs1 fc0 sc0 ls50 ws3e">card<span class="_ _0"></span>s. Two<span class="_ _0"></span> <span class="ff4 ls51 ws3f">USB 2.<span class="_ _1"></span>0 </span><span class="ls44 ws1">ports<span class="ff4 ls1"> <span class="_ _5"></span></span><span class="ls3d ws40">c<span class="_ _1"></span>onfigurable as host<span class="_ _1"></span> or device and </span></span></div><div class="t m0 x1 hd y8a ff2 fs1 fc0 sc0 ls42 ws41">10/100 Base-T <span class="ff4 ls52 ws42">Ethernet<span class="_ _0"></span> M<span class="_ _1"></span>A<span class="_ _4"></span>C<span class="ff2 ls53 ws43"> are provi<span class="_ _1"></span>ded for connectivit<span class="_ _1"></span>y. </span></span></div><div class="t m0 x1 h5 y8b ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 hd y8c ff2 fs1 fc0 sc0 ls54 ws1">A <span class="ff4 ls41 ws44">deep power</span><span class="ls1"> <span class="ff4 ls39">dow<span class="_ _1"></span>n<span class="_ _1"></span></span><span class="ls45 ws45"> mode has been added to allow a system </span></span></div><div class="t m0 x1 h5 y8d ff2 fs1 fc0 sc0 ls46 ws46">design with very low power cons<span class="_ _1"></span>umption during standby </div><div class="t m0 x1 h5 y8e ff2 fs1 fc0 sc0 ls45 ws47">mode. </div><div class="t m0 x1 h5 y8f ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x1 h5 y90 ff2 fs1 fc0 sc0 ls55 ws48">The MB86H61 comes with the Fujitsu Driver Application </div><div class="t m0 x1 h5 y91 ff2 fs1 fc0 sc0 ls44 ws49">Programming Int<span class="_ _1"></span>erface (FAPI) to help customers achieving the </div><div class="t m0 x1 h5 y92 ff2 fs1 fc0 sc0 ls44 ws4a">shortest<span class="_ _1"></span> possible developm<span class="_ _1"></span>ent cycle. FAPI is a complete </div><div class="t m0 x1 h5 y93 ff2 fs1 fc0 sc0 ls44 ws4b">driver set allowing fas<span class="_ _1"></span>t and efficient customer software design.<span class="_ _1"></span> </div><div class="t m0 x1 h5 y94 ff2 fs1 fc0 sc0 ls1 ws1"> </div><div class="t m0 x60 hd y95 ff4 fs1 fc0 sc0 ls56 ws1">FEAT<span class="_ _0"></span>URES </div><div class="t m0 x60 h10 y69 ff2 fs7 fc0 sc0 ls1 ws1"> </div><div class="t m0 x60 hd y6a ff4 fs1 fc0 sc0 ls3d ws1">System: </div><div class="t m0 x60 h5 y96 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls57 ws4c"> CPU: <span class="_ _7"></span>ARM <span class="_ _7"></span>1176JZF-S</span></div><div class="t m0 x61 h11 y97 ff2 fs8 fc0 sc0 ls58 ws1">TM</div><div class="t m0 x62 h5 y98 ff2 fs1 fc0 sc0 ls43 ws4d"> @ 475DMIPS </div><div class="t m0 x60 h5 y99 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls46 ws25"> <span class="_ _8"> </span>Memory: 2x 16-bit DDR2-800 S<span class="_ _1"></span>DRAM interface. </span></div><div class="t m0 x60 h5 y9a ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3c ws34"> <span class="_ _8"> </span>Bootdevic<span class="_ _1"></span>es: Parallel NOR, NAND or serial flash supported </span></div><div class="t m0 x60 h5 y9b ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3b ws4b"> <span class="_ _8"> </span>Standby: Power Isl<span class="_ _1"></span>and for deep pow<span class="_ _0"></span>er down </span></div><div class="t m0 x60 hd y9c ff4 fs1 fc0 sc0 ls59 ws1">Video/A<span class="_ _4"></span>udio:<span class="_ _1"></span> </div><div class="t m0 x60 h5 y9d ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3b ws4b"> <span class="_ _8"> </span>Transport stream dec<span class="_ _1"></span>oder : 4x incl. DVB descramblers </span></div><div class="t m0 x60 h5 y9e ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3c ws34"> <span class="_ _8"> </span>Cipher engine with DVB CSA 2.1, AES/<span class="_ _1"></span>DES, Multi-2, secure boot, </span></div><div class="t m0 x63 h5 y9f ff2 fs1 fc0 sc0 ls44 ws4e">control word protecti<span class="_ _1"></span>on, OTP and memory encryption. </div><div class="t m0 x60 h5 ya0 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3c ws34"> <span class="_ _8"> </span>Multi-st<span class="_ _1"></span>andard video decoder for H.264/AVC Level<span class="_ _1"></span> 4.1 HP, MPEG-</span></div><div class="t m0 x63 h5 ya1 ff2 fs1 fc0 sc0 ls44 ws4e">2 MP@HL, AVS Jizhun Profile Level 6.0, VC-1 AP Level3. </div><div class="t m0 x60 h5 ya2 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls43 ws4d"> <span class="_ _8"> </span>Video Output: Up to 1080p @ 50/60Hz, 7 layers with flexible order: </span></div><div class="t m0 x63 h5 ya3 ff2 fs1 fc0 sc0 ls43 ws4d">backplane, vi<span class="_ _1"></span>deo, cursor, 4xOSD (up to true-color in HD resolution, </div><div class="t m0 x63 h5 ya4 ff2 fs1 fc0 sc0 ls46 ws25">one layer scalabl<span class="_ _1"></span>e with flicker fixer), Y<span class="_ _1"></span>CrCb/RGB color space. </div><div class="t m0 x60 h5 ya5 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3d ws4f"> <span class="_ _8"> </span>2D graphic engine </span></div><div class="t m0 x60 h5 ya6 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3f ws50"> <span class="_ _8"> </span>PA<span class="_ _1"></span>L/NTSC/SECAM encoder inc<span class="_ _1"></span>l. Cross<span class="_ _1"></span> color / <span class="_ _1"></span>luminance filt<span class="_ _1"></span>ers / </span></div><div class="t m0 x63 h5 ya7 ff2 fs1 fc0 sc0 ls5a ws51">Telet<span class="_ _1"></span>ext /<span class="_ _1"></span> WSS / CC / VBID ins<span class="_ _1"></span>ertio<span class="_ _1"></span>n </div><div class="t m0 x60 h5 ya8 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3f ws2d"> <span class="_ _8"> </span>Audiodecoder:<span class="_ _1"></span> Programmable audio decoder supporting MPEG1 </span></div><div class="t m0 x63 h5 ya9 ff2 fs1 fc0 sc0 ls51 ws52">layer 1, 2 and 3 (MP3), HE-AAC, Dolby Digit<span class="_ _1"></span>al (planning), Dolby </div><div class="t m0 x63 h5 yaa ff2 fs1 fc0 sc0 ls44 ws4e">Digital pl<span class="_ _1"></span>us (planning) and others </div><div class="t m0 x60 hd yab ff4 fs1 fc0 sc0 ls5 ws3">Interfaces: </div><div class="t m0 x60 hd yac ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls5b ws53"> <span class="_ _8"> </span>HDMI Link and PHY with HDCP and CEC cont<span class="_ _1"></span>roller</span><span class="ff4"> </span></div><div class="t m0 x60 h5 yad ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3d ws4f"> <span class="_ _8"> </span>16bit digital vi<span class="_ _1"></span>deo incl. SAV/EAV: 1x<span class="_ _0"></span> Input /<span class="_ _1"></span> 1x Output (compliant to </span></div><div class="t m0 x63 h5 yae ff2 fs1 fc0 sc0 ls3f ws2d">SMPTE 296M and SMPTE 274M) </div><div class="t m0 x60 h5 yaf ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3d ws4f"> <span class="_ _8"> </span>24bit digital out<span class="_ _1"></span>put (compliant to EIA/CAE-861) </span></div><div class="t m0 x60 h5 yb0 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3b ws4b"> <span class="_ _8"> </span>ITU-R 656 video: 2x Input / 1x Output </span></div><div class="t m0 x60 h5 yb1 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls46 ws25"> <span class="_ _8"> </span>6x analog video DACs for YPrPb/RGB,<span class="_ _1"></span> YC and CVBS </span></div><div class="t m0 x60 h5 yb2 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3d ws4f"> <span class="_ _8"> </span>Stereo audio DACs / I&#178;S: 4x input and 4x output / SPDIF output for </span></div><div class="t m0 x63 h5 yb3 ff2 fs1 fc0 sc0 ls46 ws25">PCM / MPEG /Dolby Digital 5.1 </div><div class="t m0 x60 h5 yb4 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3b ws4b"> <span class="_ _8"> </span>2x USB 2.0 incl. PHY (host or device) </span></div><div class="t m0 x60 h5 yb5 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls5c ws54"> <span class="_ _8"> </span>eSATA/<span class="_ _0"></span>SATA in<span class="_ _0"></span>cl. PH<span class="_ _0"></span>Y (3G<span class="_ _0"></span>b/s) </span></div><div class="t m0 x60 h5 yb6 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls43 ws4d"> <span class="_ _8"> </span>Ethernet 10/100 Base-T MAC (MII) </span></div><div class="t m0 x60 h5 yb7 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls46 ws25"> <span class="_ _8"> </span>Universal proc<span class="_ _1"></span>essor interface (NAND/NOR,<span class="_ _1"></span>DVB-CI/ CI+,IDE,<span class="_ _1"></span>ATA) </span></div><div class="t m0 x60 h5 yb8 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls53 ws55"> <span class="_ _8"> </span>Universa<span class="_ _1"></span>l s<span class="_ _1"></span>lave interf<span class="_ _1"></span>ace (CI, I<span class="_ _1"></span>DE, ATA) </span></div><div class="t m0 x60 h5 yb9 ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3f ws2d"> <span class="_ _8"> </span>96x Shared GPIO, 2x UART, 2x Smart Card, 2x I&#178;C, 4x P<span class="_ _0"></span>W<span class="_ _1"></span>M, IR </span></div><div class="t m0 x63 h5 yba ff2 fs1 fc0 sc0 ls53 ws43">Rx, 2x SPI Master/Sla<span class="_ _1"></span>ve, SDIO, 4x 7-segment LED, 8x Key Input </div><div class="t m0 x60 h5 ybb ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3b ws4b"> <span class="_ _8"> </span>4 channels Analog-Digit<span class="_ _1"></span>al Converter (10bit) </span></div><div class="t m0 x60 hd ybc ff4 fs1 fc0 sc0 ls5d ws1">Package/Technology<span class="_ _0"></span>: </div><div class="t m0 x60 h5 ybd ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls3d ws4f"> <span class="_ _8"> </span>PBGA484 Package / Fujitsu CMOS 90nm technology </span></div><div class="t m0 x60 h5 ybe ff5 fs1 fc0 sc0 ls1 ws1">&#8226;<span class="ff2 ls45 ws47"> <span class="_ _8"> </span>Voltage: 1.2V core, 3.3V I/O (5V tolerant input)</span></div><div class="t m0 x1 h5 ybf ff2 fs1 fc0 sc0 ls4 ws1"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>
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