FPGA_implementation_DPD.zip_algorithm_DPD_matlab例程_数值算法/人工智能下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6250fcdb6caf5961923331bd/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250fcdb6caf5961923331bd/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">FPGA IMPLEMENTATION OF DIGITAL PREDISTORTION LINEARIZERS</div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">FOR WIDEBAND POWER AMPLIFIERS</div><div class="t m0 x3 h3 y3 ff2 fs0 fc0 sc0 ls0 ws0">Navid Lashkarian, Signal Processing Division, Xilinx Inc., San Jose, USA,</div><div class="t m0 x4 h3 y4 ff2 fs0 fc0 sc0 ls0 ws0">navid.lashkarian@xilinx.com,</div><div class="t m0 x5 h3 y5 ff2 fs0 fc0 sc0 ls0 ws0">Chris Dick, Signal Processing Division, Xilinx Inc., San Jose, USA,</div><div class="t m0 x6 h3 y6 ff2 fs0 fc0 sc0 ls0 ws0">chris.dick@xilinx.com</div><div class="t m0 x7 h4 y7 ff3 fs1 fc0 sc0 ls0 ws0">ABSTRACT</div><div class="t m0 x8 h5 y8 ff4 fs1 fc0 sc0 ls0 ws0">This paper reports on the FPGA implementation of a</div><div class="t m0 x8 h5 y9 ff4 fs1 fc0 sc0 ls0 ws0">Volterra series PA pre-distorter. The implementation</div><div class="t m0 x8 h5 ya ff4 fs1 fc0 sc0 ls0 ws0">of the pre-distorter and the indirect learning architec-</div><div class="t m0 x8 h5 yb ff4 fs1 fc0 sc0 ls0 ws0">ture for initializing the system is described. We sup-</div><div class="t m0 x8 h5 yc ff4 fs1 fc0 sc0 ls0 ws0">ply insight into the implementation of the adaptive</div><div class="t m0 x8 h5 yd ff4 fs1 fc0 sc0 ls0 ws0">process itself and how the pre-distorter can exploit</div><div class="t m0 x8 h5 ye ff4 fs1 fc0 sc0 ls0 ws0">new generation heterogeneous FPGAs that provide a</div><div class="t m0 x8 h5 yf ff4 fs1 fc0 sc0 ls0 ws0">massively parallel compute fabric for demanding real-</div><div class="t m0 x8 h5 y10 ff4 fs1 fc0 sc0 ls0 ws0">time tasks and an embedded processor for processes</div><div class="t m0 x8 h5 y11 ff4 fs1 fc0 sc0 ls0 ws0">that have softer schedules. A recent generation vi-</div><div class="t m0 x8 h5 y12 ff4 fs1 fc0 sc0 ls0 ws0">sual programming design ﬂow has been used for the</div><div class="t m0 x8 h5 y13 ff4 fs1 fc0 sc0 ls0 ws0">implementation. The paper comments on the design</div><div class="t m0 x8 h5 y14 ff4 fs1 fc0 sc0 ls0 ws0">productivity and eﬃciency aspects of the ﬁnal FPGA</div><div class="t m0 x8 h5 y15 ff4 fs1 fc0 sc0 ls0 ws0">implementation using this development environment.</div><div class="t m0 x9 h4 y16 ff3 fs1 fc0 sc0 ls0 ws0">1. INTRODUCTION</div><div class="t m0 x8 h5 y17 ff4 fs1 fc0 sc0 ls0 ws0">Bandwidth eﬃciency and transmission power eﬃ-</div><div class="t m0 x8 h5 y18 ff4 fs1 fc0 sc0 ls0 ws0">ciency are often conﬂicting criteria in digital communi-</div><div class="t m0 x8 h5 y19 ff4 fs1 fc0 sc0 ls0 ws0">cation systems. One usually has to be traded-oﬀ with</div><div class="t m0 x8 h5 y1a ff4 fs1 fc0 sc0 ls0 ws0">the other according to the system requirements. In</div><div class="t m0 x8 h5 y1b ff4 fs1 fc0 sc0 ls0 ws0">wireless applications, the cost of bandwidth accounts</div><div class="t m0 x8 h5 y1c ff4 fs1 fc0 sc0 ls0 ws0">for a considerable portion of overall cost, and it is</div><div class="t m0 x8 h5 y1d ff4 fs1 fc0 sc0 ls0 ws0">therefore important to accommodate as many users</div><div class="t m0 x8 h5 y1e ff4 fs1 fc0 sc0 ls0 ws0">in the system within the link frequency budget. This</div><div class="t m0 x8 h5 y1f ff4 fs1 fc0 sc0 ls0 ws0">requirement imp oses a heavy constraint on the power</div><div class="t m0 x8 h5 y20 ff4 fs1 fc0 sc0 ls0 ws0">eﬃciency of the ampliﬁer, contributing to nonlinear</div><div class="t m0 x8 h5 y21 ff4 fs1 fc0 sc0 ls0 ws0">behavior in this part of the transmitter [1]. Nonlinear</div><div class="t m0 x8 h5 y22 ff4 fs1 fc0 sc0 ls0 ws0">radio frequency (RF) power ampliﬁers (PA) generate</div><div class="t m0 x8 h5 y23 ff4 fs1 fc0 sc0 ls0 ws0">intermodulation (IM) distortion as adjacent channel</div><div class="t m0 x8 h5 y24 ff4 fs1 fc0 sc0 ls0 ws0">interference for many modulation formats. Therefore,</div><div class="t m0 x8 h5 y25 ff4 fs1 fc0 sc0 ls0 ws0">the design of linearizers has become a key technology</div><div class="t m0 x8 h5 y26 ff4 fs1 fc0 sc0 ls0 ws0">in wideband mobile communication transceivers.</div><div class="t m0 xa h5 y27 ff4 fs1 fc0 sc0 ls0 ws0">One solution is the linearization of the ampliﬁer by</div><div class="t m0 x8 h5 y28 ff4 fs1 fc0 sc0 ls0 ws0">means of predistorter as shown in Figure 1. The digital</div><div class="t m0 x8 h5 y29 ff4 fs1 fc0 sc0 ls0 ws0">predistortion (DPD) linearizer creates a version of the</div><div class="t m0 x8 h5 y2a ff4 fs1 fc0 sc0 ls0 ws0">desired modulation making use of the feedback mea-</div><div class="t m0 x8 h5 y2b ff4 fs1 fc0 sc0 ls0 ws0">surements of the actual ampliﬁer output. The result-</div><div class="t m0 x8 h5 y2c ff4 fs1 fc0 sc0 ls0 ws0">ing signal, when passed through the nonlinear power</div><div class="t m0 x8 h5 y2d ff4 fs1 fc0 sc0 ls0 ws0">ampliﬁer creates a signal in which the power sp ectral</div><div class="t m0 x8 h5 y2e ff4 fs1 fc0 sc0 ls0 ws0">density has signiﬁcantly lower spectral leakage com-</div><div class="t m0 xb h6 y2f ff5 fs2 fc1 sc0 ls0 ws0">MODEM Pre-Distorter Power Amplifier</div><div class="t m0 xc h6 y30 ff5 fs2 fc1 sc0 ls0 ws1">Demodulator</div><div class="t m0 xd h5 y31 ff4 fs1 fc0 sc0 ls0 ws0">Figure 1: Adaptive digital predistortion.</div><div class="t m0 xe h5 y32 ff4 fs1 fc0 sc0 ls0 ws0">pared to an uncompensated transmit signal.</div><div class="t m0 xf h5 y33 ff4 fs1 fc0 sc0 ls0 ws0">Traditionally, digital predistortion was imple-</div><div class="t m0 xe h5 y34 ff4 fs1 fc0 sc0 ls0 ws0">mented using a lookup table (LUT) approach. The</div><div class="t m0 xe h5 y35 ff4 fs1 fc0 sc0 ls0 ws0">LUT employed in this approach is representative of the</div><div class="t m0 xe h5 y36 ff4 fs1 fc0 sc0 ls0 ws0">inverse of characteristic of the ampliﬁer [2]. While this</div><div class="t m0 xe h5 y37 ff4 fs1 fc0 sc0 ls0 ws0">approach has widespread application in narrowband</div><div class="t m0 xe h5 y38 ff4 fs1 fc0 sc0 ls0 ws0">power ampliﬁer (memoryless nonlinear systems) lin-</div><div class="t m0 xe h5 y39 ff4 fs1 fc0 sc0 ls0 ws0">earization, its eﬀectiveness is hampered by the mem-</div><div class="t m0 xe h5 y3a ff4 fs1 fc0 sc0 ls0 ws0">ory eﬀects in wideband power ampliﬁers, such as those</div><div class="t m0 xe h5 y3b ff4 fs1 fc0 sc0 ls0 ws0">used in multi-carrier Universal Mobile Telecommuni-</div><div class="t m0 xe h5 y3c ff4 fs1 fc0 sc0 ls0 ws0">cations System (UMTS) and CDMA2000 systems.</div><div class="t m0 xf h5 y3d ff4 fs1 fc0 sc0 ls0 ws0">In this paper, we address the design of a lin-</div><div class="t m0 xe h5 y3e ff4 fs1 fc0 sc0 ls0 ws0">earizer based on an adaptive truncated Volterra se-</div><div class="t m0 xe h5 y3f ff4 fs1 fc0 sc0 ls0 ws0">ries (TVS) approach. TVS systems have become a</div><div class="t m0 xe h5 y40 ff4 fs1 fc0 sc0 ls0 ws0">very popular tool in adaptive nonlinear signal process-</div><div class="t m0 xe h5 y41 ff4 fs1 fc0 sc0 ls0 ws0">ing [3]. However, their real-time implementation has</div><div class="t m0 xe h5 y42 ff4 fs1 fc0 sc0 ls0 ws0">been restricted by the computational complexity as-</div><div class="t m0 xe h5 y43 ff4 fs1 fc0 sc0 ls0 ws0">sociated with the ﬁltering and adaptive mechanisms.</div><div class="t m0 xe h5 y44 ff4 fs1 fc0 sc0 ls0 ws0">Field programmable gate arrays (FPGAs) are an at-</div><div class="t m0 xe h5 y45 ff4 fs1 fc0 sc0 ls0 ws0">tractive option for realization of these highly com-</div><div class="t m0 xe h5 y46 ff4 fs1 fc0 sc0 ls0 ws0">plex signal processing functions for reasons of perfor-</div><div class="t m0 xe h5 y47 ff4 fs1 fc0 sc0 ls0 ws0">mance, power consumption and conﬁgurability. We</div><div class="t m0 xe h5 y48 ff4 fs1 fc0 sc0 ls0 ws0">propose an eﬃcient and robust architecture for the</div><div class="t m0 xe h5 y49 ff4 fs1 fc0 sc0 ls0 ws0">linearizer based on truncated Volterra ﬁlters and pro-</div><div class="t m0 xe h5 y4a ff4 fs1 fc0 sc0 ls0 ws0">vide a simulation model of the system within the Xil-</div><div class="t m0 xe h5 y4b ff4 fs1 fc0 sc0 ls0 ws0">inx System Generator for DSP</div><div class="t m0 x10 h7 y4c ff6 fs3 fc0 sc0 ls0 ws0">TM</div><div class="t m0 xc h5 y4d ff4 fs1 fc0 sc0 ls0 ws0">[4] design ﬂow. The</div><div class="t m0 xe h5 y4e ff4 fs1 fc0 sc0 ls0 ws0">implementation achieves up to 50 dB spectral suppres-</div><div class="t m0 xe h5 y4f ff4 fs1 fc0 sc0 ls0 ws0">sion in neighboring frequency bands.</div><div class="t m0 x11 h8 y50 ff7 fs4 fc0 sc0 ls0 ws0">Proceeding of the SDR 04 Technical Conference and Product Exposition. Copyright © 2004 SDR Forum. All Rights Reserved</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250fcdb6caf5961923331bd/bg2.jpg"><div class="t m0 x12 h6 y51 ff5 fs2 fc1 sc0 ls0 ws0">Predistorter</div><div class="t m0 x13 h6 y52 ff5 fs2 fc1 sc0 ls0 ws0">Power</div><div class="t m0 x14 h6 y53 ff5 fs2 fc1 sc0 ls0 ws0">Amplifier</div><div class="t m0 x15 h6 y54 ff5 fs2 fc1 sc0 ls0 ws0">Predistorter</div><div class="t m0 x16 h6 y55 ff5 fs2 fc1 sc0 ls0 ws0">Training</div><div class="t m0 x17 h9 y56 ff8 fs2 fc1 sc0 ls0 ws0">e(n)</div><div class="t m0 x18 h9 y57 ff8 fs2 fc1 sc0 ls0 ws0">z(n)</div><div class="t m0 x19 h9 y58 ff8 fs2 fc1 sc0 ls0 ws0">z</div><div class="t m0 x1a h9 y59 ff5 fs2 fc1 sc0 ls0 ws0">(n)</div><div class="t m0 x19 h6 y5a ff5 fs2 fc1 sc0 ls0 ws0">^</div><div class="t m0 x1b h9 y5b ff8 fs2 fc1 sc0 ls0 ws0">x</div><div class="t m0 x1c h9 y5c ff5 fs2 fc1 sc0 ls0 ws0">(n) y(n)</div><div class="t m0 x1d h6 y5d ff5 fs2 fc1 sc0 ls0 ws0">1</div><div class="t m0 x1e h9 y5e ff8 fs2 fc1 sc0 ls0 ws0">G</div><div class="t m0 x8 h5 y5f ff4 fs1 fc0 sc0 ls0 ws0">Figure 2: Baseband equivalent model of the DPD cir-</div><div class="t m0 x8 h5 y60 ff4 fs1 fc0 sc0 ls0 ws0">cuit. G represents the gain of the power ampliﬁer.</div><div class="t m0 x1f h4 y61 ff3 fs1 fc0 sc0 ls0 ws0">2. PREDISTORTER ARCHITECTURE</div><div class="t m0 x8 h5 y62 ff4 fs1 fc0 sc0 ls0 ws0">Our approach to nonlinear predistortion is based on</div><div class="t m0 x8 h5 y63 ff4 fs1 fc0 sc0 ls0 ws0">the method proposed by Eun & Powers [5]. In this</div><div class="t m0 x8 h5 y64 ff4 fs1 fc0 sc0 ls0 ws0">approach, two identical truncated Volterra systems</div><div class="t m0 x8 h5 y65 ff4 fs1 fc0 sc0 ls0 ws0">are used for training and predistortion. Figure 2 de-</div><div class="t m0 x8 h5 y66 ff4 fs1 fc0 sc0 ls0 ws0">picts the block diagram of the equivalent baseband</div><div class="t m0 x8 h5 y67 ff4 fs1 fc0 sc0 ls0 ws0">model of the digital predistortion network. The ob-</div><div class="t m0 x8 h5 y68 ff4 fs1 fc0 sc0 ls0 ws0">jective of the linearizer is to ﬁnd a transformation</div><div class="t m0 x8 h5 y69 ff4 fs1 fc0 sc0 ls0 ws0">of the signal (˜z(n)=V (x(n))) that in combination</div><div class="t m0 x8 h5 y6a ff4 fs1 fc0 sc0 ls0 ws0">with the nonlinear ampliﬁer (responsible for the dis-</div><div class="t m0 x8 h5 y6b ff4 fs1 fc0 sc0 ls0 ws0">tortion) will result in an identity system that produces</div><div class="t m0 x8 h5 y6c ff4 fs1 fc0 sc0 ls0 ws0">the signal of interest without distortion at the out-</div><div class="t m0 x8 h5 y6d ff4 fs1 fc0 sc0 ls0 ws0">put of the power ampliﬁer (y(n) ' x(n )). The main</div><div class="t m0 x8 h5 y6e ff4 fs1 fc0 sc0 ls0 ws0">challenge of this approach is to track and identify the</div><div class="t m0 x8 h5 y6f ff4 fs1 fc0 sc0 ls0 ws0">time varying characteristics of the ampliﬁer. To ad-</div><div class="t m0 x8 h5 y70 ff4 fs1 fc0 sc0 ls0 ws0">dress this task a stochastic gradient adaptation mech-</div><div class="t m0 x8 h5 y71 ff4 fs1 fc0 sc0 ls0 ws0">anism is employed. The adaptation of the truncated</div><div class="t m0 x8 h5 y72 ff4 fs1 fc0 sc0 ls0 ws0">Volterra system is a two stage pro cess. During initial-</div><div class="t m0 x8 h5 y73 ff4 fs1 fc0 sc0 ls0 ws0">ization, the input and output signals of the p ower am-</div><div class="t m0 x8 h5 y74 ff4 fs1 fc0 sc0 ls0 ws0">pliﬁer are probed and the Volterra ﬁlter coeﬃcients are</div><div class="t m0 x8 h5 y75 ff4 fs1 fc0 sc0 ls0 ws0">adapted oﬀ-line using Recursive Least Squares (RLS</div><div class="t m0 x8 h5 y76 ff4 fs1 fc0 sc0 ls0 ws0">or Kalman Filtering) estimation. This process is also</div><div class="t m0 x8 h5 y77 ff4 fs1 fc0 sc0 ls0 ws0">known as initialization through indirect learning. Once</div><div class="t m0 x8 h5 y78 ff4 fs1 fc0 sc0 ls0 ws0">the adaptive ﬁlter is initialized at an optimum station-</div><div class="t m0 x8 h5 y79 ff4 fs1 fc0 sc0 ls0 ws0">ary point, a stochastic adaptive mechanism is used to</div><div class="t m0 x8 h5 y7a ff4 fs1 fc0 sc0 ls0 ws0">track the time-varying characteristics of the nonlinear</div><div class="t m0 x8 h5 y7b ff4 fs1 fc0 sc0 ls0 ws0">ampliﬁer.</div><div class="t m0 x8 ha y7c ffc fs5 fc0 sc0 ls0 ws0">2.1. Memory Polynomial Predistorter</div><div class="t m0 xa h5 y7d ff4 fs1 fc0 sc0 ls0 ws0">We use the memory polynomial model (Eq. 1) for</div><div class="t m0 x8 h5 y7e ff4 fs1 fc0 sc0 ls0 ws0">the predistorter block as described in [6]</div><div class="t m0 x1 h5 y7f ff9 fs1 fc0 sc0 ls0 ws0">z[n]=</div><div class="t m0 x20 hb y80 ffd fs6 fc0 sc0 ls0 ws0">K</div><div class="t m0 x21 hc y81 ffe fs1 fc0 sc0 ls0 ws0">X</div><div class="t m0 x22 h5 y82 ff9 fs1 fc0 sc0 ls0 ws0">k =1</div><div class="t m0 x22 h5 y83 ff9 fs1 fc0 sc0 ls0 ws0">k even</div><div class="t m0 x23 hb y84 ffd fs6 fc0 sc0 ls0 ws0">Q</div><div class="t m0 x24 hc y81 ffe fs1 fc0 sc0 ls0 ws0">X</div><div class="t m0 x24 hd y85 ffd fs6 fc0 sc0 ls0 ws0">q=0</div><div class="t m0 x1a he y7f ff9 fs1 fc0 sc0 ls0 ws0">a</div><div class="t m0 x25 hb y86 ffd fs6 fc0 sc0 ls4 ws0">kq</div><div class="t m0 x26 h5 y7f ff9 fs1 fc0 sc0 ls0 ws0">x(n − q) ∗|x(n − q)|</div><div class="t m0 x1d hd y87 ffd fs6 fc0 sc0 ls0 ws0">k−1</div><div class="t m0 x27 h5 y7f ff4 fs1 fc0 sc0 ls0 ws0">(1)</div><div class="t m0 xe h5 y88 ff4 fs1 fc0 sc0 ls0 ws0">where K is the nonlinearity order and Q represents</div><div class="t m0 xe h5 y89 ff4 fs1 fc0 sc0 ls0 ws0">the memory length of the power ampliﬁer. In order to</div><div class="t m0 xe h5 y8a ff4 fs1 fc0 sc0 ls0 ws0">reduce the implementation complexity of the predis-</div><div class="t m0 xe h5 y8b ff4 fs1 fc0 sc0 ls0 ws0">torter while maintaining acceptable performance, only</div><div class="t m0 xe h5 y8c ff4 fs1 fc0 sc0 ls0 ws0">the odd-order terms in the nonlinearity are included</div><div class="t m0 xe h5 y8d ff4 fs1 fc0 sc0 ls0 ws0">in the mo del. This compromise reduces the complex-</div><div class="t m0 xe h5 y8e ff4 fs1 fc0 sc0 ls0 ws0">ity of the predistorter by approximately 40% at the</div><div class="t m0 xe h5 y8f ff4 fs1 fc0 sc0 ls0 ws0">expense of 3 to 5 dB spectral regrowth. A detailed</div><div class="t m0 xe h5 y90 ff4 fs1 fc0 sc0 ls0 ws0">investigation of the beneﬁts of even-order terms in the</div><div class="t m0 xe h5 y91 ff4 fs1 fc0 sc0 ls0 ws0">baseband mo del is presented in [7].</div><div class="t m0 xe ha y92 ffc fs5 fc0 sc0 ls0 ws0">2.2. Indirect Learning</div><div class="t m0 xf h5 y93 ff4 fs1 fc0 sc0 ls0 ws0">Initialization of the DPD linearizer is performed</div><div class="t m0 xe h5 y94 ff4 fs1 fc0 sc0 ls0 ws0">using optimum ﬁltering, which is done as an oﬀ-line</div><div class="t m0 xe h5 y95 ff4 fs1 fc0 sc0 ls0 ws0">computation in our DPD implementation. Adaptive</div><div class="t m0 xe h5 y96 ff4 fs1 fc0 sc0 ls0 ws0">ﬁlter coeﬃcient estimation can b e considered a lin-</div><div class="t m0 xe h5 y97 ff4 fs1 fc0 sc0 ls0 ws0">ear optimization task. Any of the common estima-</div><div class="t m0 xe h5 y98 ff4 fs1 fc0 sc0 ls0 ws0">tion methods - Least Square Estimation [8], minimum</div><div class="t m0 xe h5 y99 ff4 fs1 fc0 sc0 ls0 ws0">mean squared error (MMSE) [8] or Wiener Filtering,</div><div class="t m0 xe h5 y9a ff4 fs1 fc0 sc0 ls0 ws0">Kalman [8] or recursive least squares (RLS) ﬁlter-</div><div class="t m0 xe h5 y9b ff4 fs1 fc0 sc0 ls0 ws0">ing [8] - can be used.</div><div class="t m0 xf h5 y9c ff4 fs1 fc0 sc0 ls0 ws0">We note that while all of the above methods try</div><div class="t m0 xe h5 y9d ff4 fs1 fc0 sc0 ls0 ws0">to solve one optimization problem, that is the linear</div><div class="t m0 xe h5 y9e ff4 fs1 fc0 sc0 ls0 ws0">parameter estimation, the stationary point obtained</div><div class="t m0 xe h5 y9f ff4 fs1 fc0 sc0 ls0 ws0">from using these methods might be quite diﬀerent.</div><div class="t m0 xe h5 ya0 ff4 fs1 fc0 sc0 ls0 ws0">This is mainly due to the fact that the error criterion</div><div class="t m0 xe h5 ya1 ff4 fs1 fc0 sc0 ls0 ws0">for the approaches are diﬀerent, causing a diﬀerent</div><div class="t m0 xe h5 ya2 ff4 fs1 fc0 sc0 ls0 ws0">proﬁle for the error surface.</div><div class="t m0 xe ha ya3 ffc fs5 fc0 sc0 ls0 ws0">2.3. Tracking and Direct Learning</div><div class="t m0 xf h5 ya4 ff4 fs1 fc0 sc0 ls0 ws0">The inverse of the nonlinear ampliﬁer is adaptively</div><div class="t m0 xe h5 ya5 ff4 fs1 fc0 sc0 ls0 ws0">tracked using a stochastic gradient method. Least</div><div class="t m0 xe h5 ya6 ff4 fs1 fc0 sc0 ls0 ws0">mean squares (LMS) adaptive ﬁlters are known to</div><div class="t m0 xe h5 ya7 ff4 fs1 fc0 sc0 ls0 ws0">have a slow convergence rate. However, since the</div><div class="t m0 xe h5 ya8 ff4 fs1 fc0 sc0 ls0 ws0">power ampliﬁer characteristics vary slowly as a func-</div><div class="t m0 xe h5 ya9 ff4 fs1 fc0 sc0 ls0 ws0">tion of time, the LMS approach is a reasonable choice</div><div class="t m0 xe h5 yaa ff4 fs1 fc0 sc0 ls0 ws0">for performing parameter tracking.</div><div class="t m0 xf h5 yab ff4 fs1 fc0 sc0 ls0 ws0">At each iteration of the stochastic gradient algo-</div><div class="t m0 xe h5 yac ff4 fs1 fc0 sc0 ls0 ws0">rithm, an update for the unknown vector is obtained</div><div class="t m0 xe h5 yad ff4 fs1 fc0 sc0 ls0 ws0">from</div><div class="t m0 x28 he yae ff9 fs1 fc0 sc0 ls0 ws0">W</div><div class="t m0 x29 hd yaf ffd fs6 fc0 sc0 ls0 ws0">n+1</div><div class="t m0 x2a h5 yb0 ff4 fs1 fc0 sc0 ls0 ws0">= W</div><div class="t m0 x2b hb yaf ffd fs6 fc0 sc0 ls0 ws0">n</div><div class="t m0 x2c h5 yb0 ff4 fs1 fc0 sc0 ls0 ws0">+ µ × e</div><div class="t m0 x2d hb yaf ffd fs6 fc0 sc0 ls0 ws0">n</div><div class="t m0 x2e h5 yb0 ffa fs1 fc0 sc0 ls0 ws0">× X</div><div class="t m0 x2f hf yb1 ff10 fs6 fc0 sc0 ls0 ws0">∗</div><div class="t m0 x2f hb yb2 ffd fs6 fc0 sc0 ls0 ws0">n</div><div class="t m0 x30 h5 yb0 ff4 fs1 fc0 sc0 ls0 ws0">(2)</div><div class="t m0 xe h5 yb3 ff4 fs1 fc0 sc0 ls0 ws0">where the error vector is deﬁned as</div><div class="t m0 x31 he yb4 ff9 fs1 fc0 sc0 ls0 ws0">e</div><div class="t m0 x32 hb yb5 ffd fs6 fc0 sc0 ls0 ws0">n</div><div class="t m0 x33 h5 yb4 ff4 fs1 fc0 sc0 ls0 ws0">= z(n) − W</div><div class="t m0 x34 hb yb5 ffd fs6 fc0 sc0 ls0 ws0">n</div><div class="t m0 x35 h5 yb4 ffa fs1 fc0 sc0 ls0 ws0">× X</div><div class="t m0 x36 hb yb5 ffd fs6 fc0 sc0 ls0 ws0">n</div><div class="t m0 x30 h5 yb4 ff4 fs1 fc0 sc0 ls0 ws0">(3)</div><div class="t m0 xe h5 y4f ff9 fs1 fc0 sc0 ls0 ws0">X is the vector containing all the necessary nonlinear</div><div class="t m0 x11 h8 y50 ff7 fs4 fc0 sc0 ls0 ws0">Proceeding of the SDR 04 Technical Conference and Product Exposition. Copyright © 2004 SDR Forum. All Rights Reserved</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>