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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/624f4e2874bc5c01052ff49d/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Intel</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">®</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Cyclone</div><div class="t m0 x4 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">®</div><div class="t m0 x5 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> 10 LP Device Family Pin</div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls0 ws0">Connection Guidelines</div><div class="t m0 x6 h4 y4 ff1 fs2 fc0 sc0 ls0 ws0">Subscribe</div><div class="t m0 x6 h4 y5 ff1 fs2 fc0 sc0 ls0 ws0">Send Feedback</div><div class="t m0 x7 h4 y6 ff1 fs2 fc0 sc0 ls0 ws0">PCG-01021 | 2017.11.06</div><div class="t m0 x8 h4 y7 ff2 fs2 fc1 sc0 ls0 ws0">Latest document on the web: <span class="ff1 fc0">PDF</span> | <span class="ff1 fc0">HTML</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.212121,0.000000,0.000000,1.212121,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/624f4e2874bc5c01052ff49d/bg2.jpg"><div class="t m0 x9 h5 y8 ff1 fs3 fc0 sc0 ls0 ws0">Contents</div><div class="t m0 x9 h4 y9 ff1 fs2 fc1 sc0 ls0 ws0">Intel</div><div class="t m0 xa h6 ya ff1 fs4 fc1 sc0 ls0 ws0">®</div><div class="t m0 xb h4 y9 ff1 fs2 fc1 sc0 ls0 ws0"> Cyclone</div><div class="t m0 xc h6 ya ff1 fs4 fc1 sc0 ls0 ws0">®</div><div class="t m0 xd h4 y9 ff1 fs2 fc1 sc0 ls0 ws0"> 10 LP Device Family Pin Connection Guidelines................................................................................................<span class="_ _0"> </span>3</div><div class="t m0 xe h4 yb ff2 fs2 fc1 sc0 ls0 ws0">Intel</div><div class="t m0 xf h6 yc ff2 fs4 fc1 sc0 ls0 ws0">®</div><div class="t m0 x10 h4 yb ff2 fs2 fc1 sc0 ls0 ws0"> Cyclone</div><div class="t m0 x11 h6 yc ff2 fs4 fc1 sc0 ls0 ws0">®</div><div class="t m0 x12 h4 yb ff2 fs2 fc1 sc0 ls0 ws0"> 10 LP Pin Connection Guidelines.....................................................................................................................4</div><div class="t m0 x13 h4 yd ff2 fs2 fc1 sc0 ls0 ws0">Clock and PLL Pins.....................................................................................................................................................<span class="_ _1"> </span>4</div><div class="t m0 x13 h4 ye ff2 fs2 fc1 sc0 ls0 ws0">Configuration/JT<span class="_ _2"></span>AG Pins..............................................................................................................................................<span class="_ _3"></span>4</div><div class="t m0 x13 h4 yf ff2 fs2 fc1 sc0 ls0 ws0">Differential I/O Pins....................................................................................................................................................7</div><div class="t m0 x13 h4 y10 ff2 fs2 fc1 sc0 ls0 ws0">Reference Pins...........................................................................................................................................................8</div><div class="t m0 x13 h4 y11 ff2 fs2 fc1 sc0 ls0 ws0">Supply Pins...............................................................................................................................................................<span class="_ _4"></span>8</div><div class="t m0 x13 h4 y12 ff2 fs2 fc1 sc0 ls0 ws0">Notes to Intel Cyclone 10 LP Pin Connection Guidelines.................................................................................................<span class="_ _1"> </span>10</div><div class="t m0 xe h4 y13 ff2 fs2 fc1 sc0 ls0 ws0">Power Supply Sharing Guidelines.........................................................................................................................................<span class="_ _5"></span>11</div><div class="t m0 xe h4 y14 ff2 fs2 fc1 sc0 ls0 ws0">Document Revision History for Intel <span class="_ _6"></span>Cyclone 10 LP Device F<span class="_ _2"></span>amily Pin Connection Guidelines........................................................<span class="_ _4"></span>13</div><div class="t m0 x14 h7 y15 ff3 fs5 fc1 sc0 ls0 ws0">Contents</div><div class="t m0 x9 h8 y16 ff2 fs5 fc1 sc0 ls0 ws0">Intel</div><div class="t m0 x15 h9 y17 ff2 fs6 fc1 sc0 ls0 ws0">®</div><div class="t m0 x16 h8 y16 ff2 fs5 fc1 sc0 ls0 ws0"> Cyclone</div><div class="t m0 xf h9 y17 ff2 fs6 fc1 sc0 ls0 ws0">®</div><div class="t m0 x17 h8 y16 ff2 fs5 fc1 sc0 ls0 ws0"> 10 LP Device F<span class="_ _6"></span>amily Pin Connection Guidelines</div><div class="t m0 x9 h8 y18 ff2 fs5 fc1 sc0 ls0 ws0">2</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.212121,0.000000,0.000000,1.212121,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/624f4e2874bc5c01052ff49d/bg3.jpg"><div class="t m0 x9 h5 y19 ff1 fs3 fc0 sc0 ls0 ws0">Intel</div><div class="t m0 x18 ha y1a ff1 fs7 fc0 sc0 ls0 ws0">®</div><div class="t m0 x19 h5 y19 ff1 fs3 fc0 sc0 ls0 ws0"> Cyclone</div><div class="t m0 x1a ha y1a ff1 fs7 fc0 sc0 ls0 ws0">®</div><div class="t m0 x1b h5 y19 ff1 fs3 fc0 sc0 ls0 ws0"> 10 LP Device Family Pin Connection Guidelines</div><div class="c x1c y1b w2 hb"><div class="t m0 x1d hc y1c ff4 fs8 fc1 sc0 ls0 ws0">Disclaimer</div><div class="t m0 x0 hd y1d ff5 fs2 fc1 sc0 ls0 ws0">© 2017 Intel Corporation. All rights reserved. Intel<span class="_ _6"></span>, the Intel logo, A<span class="_ _6"></span>ltera, Arria, Cy<span class="_ _6"></span>clone, Enpirion, MA<span class="_ _6"></span>X, Megacore<span class="_ _6"></span>, NIOS, Quartus Prime and Stratix words and logos ar<span class="_ _6"></span>e</div><div class="t m0 x0 hd y1e ff5 fs2 fc1 sc0 ls0 ws0">trademarks of Intel Corporation in the US and/or other countries<span class="_ _6"></span>. Other marks and brands may be claimed as the proper<span class="_ _5"></span>ty of others. Intel warrants performance of its FPGA</div><div class="t m0 x0 hd y1f ff5 fs2 fc1 sc0 ls0 ws0">and semiconductor products to current specifications in accor<span class="_ _6"></span>dance with Intel's standard warran<span class="_ _6"></span>ty<span class="_ _6"></span>, but reserves the right to make changes to any pr<span class="_ _6"></span>oducts and ser<span class="_ _5"></span>vices at</div><div class="t m0 x0 hd y20 ff5 fs2 fc1 sc0 ls0 ws0">any time without notice<span class="_ _6"></span>. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as</div><div class="t m0 x0 hd y21 ff5 fs2 fc1 sc0 ls0 ws0">expressly agr<span class="_ _6"></span>eed to in writing by Intel. Intel customers ar<span class="_ _6"></span>e advised to obtain the latest v<span class="_ _6"></span>ersion of device specifications befor<span class="_ _6"></span>e relying on any published inf<span class="_ _6"></span>ormation and</div><div class="t m0 x0 hd y22 ff5 fs2 fc1 sc0 ls0 ws0">before placing or<span class="_ _6"></span>ders for pr<span class="_ _6"></span>oducts or ser<span class="_ _5"></span>vices.</div><div class="t m0 x0 hd y23 ff5 fs2 fc1 sc0 ls0 ws0">These pin connection guidelines, and your use ther<span class="_ _6"></span>eof<span class="_ _6"></span>, are subject to and gov<span class="_ _6"></span>erned by Intel’<span class="_ _2"></span>s terms and conditions below<span class="_ _6"></span>. By using these pin connection guidelines, y<span class="_ _6"></span>ou</div><div class="t m0 x0 hd y24 ff5 fs2 fc1 sc0 ls0 ws0">indicate your acc<span class="_ _6"></span>eptance of all such terms and conditions. If you do not ag<span class="_ _6"></span>ree with such terms and conditions<span class="_ _6"></span>, you may not use the pin connection guidelines, and y<span class="_ _6"></span>ou are</div><div class="t m0 x0 hd y25 ff5 fs2 fc1 sc0 ls0 ws0">required to pr<span class="_ _6"></span>omptly and irrevocably destr<span class="_ _6"></span>oy the pin connection guidelines and any copies or portions thereof in your possession or under y<span class="_ _6"></span>our control<span class="_ _6"></span>.</div><div class="t m0 x0 he y26 ff6 fs2 fc1 sc0 ls0 ws0">T<span class="_ _2"></span>erms and Conditions:</div><div class="t m0 x0 hd y27 ff5 fs2 fc1 sc0 ls0 ws0">1. These pin connection guidelines are provided as e<span class="_ _6"></span>xamples only<span class="_ _6"></span>, and should not be deemed to be technical specifications or r<span class="_ _6"></span>ecommendations. T<span class="_ _6"></span>he use of the pin</div><div class="t m0 x0 hd y28 ff5 fs2 fc1 sc0 ls0 ws0"> connection guidelines for any particular design should be verified for device oper<span class="_ _6"></span>ation with the applicable datasheet and Intel.</div><div class="t m0 x0 hd y29 ff5 fs2 fc1 sc0 ls0 ws0">2. Subject to these terms and conditions, Intel grants t<span class="_ _6"></span>o you the use of these pin connection guidelines as examples of possible pin connections of an Intel</div><div class="t m0 x0 hd y2a ff5 fs2 fc1 sc0 ls0 ws0"> programmable logic devic<span class="_ _6"></span>e-based design. Y<span class="_ _2"></span>ou may not use these pin connection guidelines for any other purpose except as expr<span class="_ _6"></span>essly permitted in these terms</div><div class="t m0 x0 hd y2b ff5 fs2 fc1 sc0 ls0 ws0"> and conditions. Intel does not rec<span class="_ _6"></span>ommend, suggest, or r<span class="_ _6"></span>equire that these pin connection guidelines be used in conjunction or combination with any other software</div><div class="t m0 x0 hd y2c ff5 fs2 fc1 sc0 ls0 ws0"> or product, and makes no representations<span class="_ _6"></span>, warranties or guaranties<span class="_ _6"></span>, implied or express as w<span class="_ _6"></span>ell as any warranties arising fr<span class="_ _6"></span>om course of performance, course of</div><div class="t m0 x0 hd y2d ff5 fs2 fc1 sc0 ls0 ws0"> dealing, or usage in trade including but not limited t<span class="_ _6"></span>o the accuracy<span class="_ _6"></span>, completeness or genuineness ther<span class="_ _6"></span>eof<span class="_ _6"></span>.</div><div class="t m0 x0 hd y2e ff5 fs2 fc1 sc0 ls0 ws0">3. Intel will not be liable for any lost r<span class="_ _6"></span>evenue<span class="_ _6"></span>, lost profits, or other c<span class="_ _6"></span>onsequential, indirect, or special damages caused by y<span class="_ _6"></span>our use of these pin connection guidelines</div><div class="t m0 x0 hd y2f ff5 fs2 fc1 sc0 ls0 ws0"> even if advised of the possibility of such damages occurring.</div><div class="t m0 x0 hd y30 ff5 fs2 fc1 sc0 ls0 ws0">4. This agreement shall be go<span class="_ _6"></span>verned in all respects by the laws of the Stat<span class="_ _6"></span>e of Delaware, without r<span class="_ _6"></span>egard to c<span class="_ _6"></span>onflict of law or choice of law principles. Y<span class="_ _2"></span>ou agree to</div><div class="t m0 x0 hd y31 ff5 fs2 fc1 sc0 ls0 ws0"> submit to the exclusiv<span class="_ _6"></span>e jurisdiction of the federal and state courts in the State of Delaware for the r<span class="_ _6"></span>esolution of any disput<span class="_ _6"></span>e or claim arising out of or relating to</div><div class="t m0 x0 hd y32 ff5 fs2 fc1 sc0 ls0 ws0"> these terms of use.</div></div><div class="t m0 x1 h8 y15 ff1 fs5 fc0 sc0 ls0 ws0">PCG-01021 | 2017.11.06</div><div class="t m0 x1e h8 y33 ff2 fs5 fc1 sc0 ls0 ws0">Intel Corporation. <span class="_ _5"></span>All <span class="_ _5"></span>rights <span class="_ _5"></span>reserved. <span class="_ _5"></span>Intel, the <span class="_ _5"></span>Intel <span class="_ _5"></span>logo, <span class="_ _5"></span>Altera, Arria, <span class="_ _5"></span>Cyclone, <span class="_ _5"></span>Enpirion, <span class="_ _5"></span>MAX, <span class="_ _5"></span>Nios, <span class="_ _5"></span>Quartus <span class="_ _5"></span>and <span class="_ _5"></span>Stratix words <span class="_ _5"></span>and <span class="_ _5"></span>logos <span class="_ _5"></span>are <span class="_ _5"></span>trademarks of <span class="_ _5"></span>Intel</div><div class="t m0 x1e h8 y34 ff2 fs5 fc1 sc0 ls0 ws0">Corporation <span class="_ _3"></span>or <span class="_ _5"></span>its <span class="_ _3"> </span>subsidiaries <span class="_ _3"> </span>in <span class="_ _3"></span>the <span class="_ _3"></span>U.S. <span class="_ _3"></span>and/or <span class="_ _3"></span>other <span class="_ _3"></span>countries. <span class="_ _3"></span>Intel <span class="_ _3"></span>warr<span class="_ _6"></span>ants <span class="_ _3"></span>performance <span class="_ _3"></span>of <span class="_ _3"></span>its <span class="_ _3"></span>FPGA <span class="_ _3"></span>and <span class="_ _5"></span>semiconductor <span class="_ _3"> </span>products <span class="_ _3"> </span>to <span class="_ _3"></span>current <span class="_ _3"></span>specifications <span class="_ _3"></span>in</div><div class="t m0 x1e h8 y35 ff2 fs5 fc1 sc0 ls0 ws0">accordance <span class="_ _4"> </span>with <span class="_ _4"> </span>Intel's <span class="_ _4"> </span>standard <span class="_ _4"> </span>warr<span class="_ _6"></span>anty<span class="_ _2"></span>, <span class="_ _4"> </span>but <span class="_ _4"> </span>reserves <span class="_ _3"> </span>the <span class="_ _4"> </span>right <span class="_ _4"> </span>to <span class="_ _4"> </span>make <span class="_ _4"> </span>changes <span class="_ _4"> </span>to <span class="_ _4"> </span>any <span class="_ _4"> </span>products <span class="_ _4"> </span>and <span class="_ _3"> </span>services <span class="_ _4"> </span>at <span class="_ _4"> </span>any <span class="_ _4"> </span>time <span class="_ _4"> </span>without <span class="_ _4"> </span>notice. <span class="_ _4"> </span>Intel <span class="_ _4"> </span>assumes <span class="_ _4"> </span>no</div><div class="t m0 x1e h8 y36 ff2 fs5 fc1 sc0 ls0 ws0">responsibility <span class="_ _3"></span>or <span class="_ _3"></span>liability <span class="_ _3"></span>arising <span class="_ _3"></span>out <span class="_ _3"></span>of <span class="_ _3"></span>the <span class="_ _3"></span>application <span class="_ _3"></span>or <span class="_ _3"></span>use <span class="_ _3"></span>of <span class="_ _3"></span>any <span class="_ _3"></span>information, <span class="_ _3"></span>product, <span class="_ _3"></span>or <span class="_ _5"></span>service <span class="_ _3"> </span>described <span class="_ _3"> </span>herein <span class="_ _3"> </span>except <span class="_ _3"></span>as <span class="_ _3"></span>expressly <span class="_ _3"></span>agreed <span class="_ _3"></span>to <span class="_ _3"></span>in <span class="_ _3"></span>writing <span class="_ _3"></span>by</div><div class="t m0 x1e h8 y37 ff2 fs5 fc1 sc0 ls0 ws0">Intel. <span class="_ _3"> </span>Intel <span class="_ _4"> </span>customers <span class="_ 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