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最新的官方发布STM32F427_429的Datasheet
STM32F427_429_Datasheet.zip
  • STM32F427_429_Datasheet.pdf
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/625c4b8e92dc900e623b2c52/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625c4b8e92dc900e623b2c52/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">This is information on a product in full prod<span class="_ _0"></span>uction. </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">January 2018<span class="_ _1"> </span>DocID024030 Rev 10<span class="_ _2"> </span>1/239</div><div class="t m0 x2 h4 y3 ff2 fs2 fc0 sc0 ls2 ws2">STM32F427xx STM32F429xx</div><div class="t m1 x3 h5 y4 ff1 fs3 fc0 sc0 ls3 ws3">32b Arm</div><div class="t m2 x4 h6 y5 ff1 fs4 fc0 sc0 ls4 ws4">&#174;</div><div class="t m1 x5 h5 y4 ff1 fs3 fc0 sc0 ls5 ws5"> Cortex</div><div class="t m2 x6 h6 y5 ff1 fs4 fc0 sc0 ls4 ws4">&#174;</div><div class="t m1 x7 h5 y4 ff1 fs3 fc0 sc0 ls6 ws6">-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB</div><div class="t m1 x8 h5 y6 ff1 fs3 fc0 sc0 ls7 ws7">OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, <span class="ls8 ws8">20 com. interfaces<span class="ls9 ws9">, camera &amp; LCD-TFT</span></span></div><div class="t m0 x9 h7 y7 ff2 fs1 fc0 sc0 lsa ws4">Datasheet <span class="ff1 fs5 ls4">-</span><span class="lsb wsa"> production data</span></div><div class="t m0 x1 h8 y8 ff2 fs6 fc0 sc0 lsc ws4">Features</div><div class="t m0 x1 h9 y9 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 lsd wsb">Core: Arm</span></div><div class="t m0 xa ha ya ff1 fs8 fc0 sc0 ls4 ws4">&#174;</div><div class="t m0 xb h9 y9 ff1 fs7 fc0 sc0 lse wsc"> 32-bit Cortex</div><div class="t m0 xc ha ya ff1 fs8 fc0 sc0 ls4 ws4">&#174;</div><div class="t m0 xd h9 y9 ff1 fs7 fc0 sc0 lsf wsd">-M4 CPU with FPU, </div><div class="t m0 xe h9 yb ff1 fs7 fc0 sc0 ls10 wse">Adaptive real-tim<span class="_ _4"></span>e accelerator (A<span class="_ _4"></span>RT </div><div class="t m0 xe h9 yc ff1 fs7 fc0 sc0 ls11 wsf">Accelerator&#8482;) allowing 0-wait state execution </div><div class="t m0 xe h9 yd ff1 fs7 fc0 sc0 ls12 ws10">from Flash memory, frequency up to 18<span class="_ _0"></span>0<span class="_ _5"> </span>MHz, </div><div class="t m0 xe h9 ye ff1 fs7 fc0 sc0 ls13 ws11">MPU, 225<span class="_"> </span>DMIPS/1.25<span class="_"> </span>DMIPS/MHz<span class="fc1 ls4 ws4"> </span></div><div class="t m0 xe h9 yf ff1 fs7 fc0 sc0 ls14 ws12">(Dhrystone 2.1), and DSP in<span class="_ _0"></span>structions</div><div class="t m0 x1 h9 y10 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls15">Memories</span></div><div class="t m0 xe h9 y11 ff1 fs7 fc0 sc0 ls16 ws13">&#8211;<span class="_ _6"> </span>Up to 2 MB of Flash memory organized into </div><div class="t m0 xf h9 y12 ff1 fs7 fc0 sc0 ls17 ws14">two banks allowing <span class="ls18 ws4">read-w<span class="_ _4"></span>hile-write</span></div><div class="t m0 xe h9 y13 ff1 fs7 fc0 sc0 ls19 ws15">&#8211;<span class="_ _6"> </span>Up to 256+4<span class="_"> </span>KB of SRAM including 64-KB </div><div class="t m0 xf h9 y14 ff1 fs7 fc0 sc0 ls1a ws16">of CCM (core coupled memory) dat<span class="_ _0"></span>a RAM</div><div class="t m0 xe h9 y15 ff1 fs7 fc0 sc0 ls1b ws17">&#8211;<span class="_ _6"> </span>Flexible ex<span class="_ _4"></span>ternal memory co<span class="_ _4"></span>ntroller with up </div><div class="t m0 xf h9 y16 ff1 fs7 fc0 sc0 ls19 ws15">to 32-bit data bus: SRAM, PSRAM, </div><div class="t m0 xf h9 y17 ff1 fs7 fc0 sc0 lsf ws18">SDRAM/LPSDR SDRAM, Compact </div><div class="t m0 xf h9 y18 ff1 fs7 fc0 sc0 ls1c ws19">Flash/NOR/NAND memories</div><div class="t m0 x1 h9 y19 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls1d ws1a">LCD parallel interface, 80<span class="_ _0"></span>80/6800 modes</span></div><div class="t m0 x1 h9 y1a ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls11 wsf">LCD-TFT controller with fully programmable </span></div><div class="t m0 xe h9 y1b ff1 fs7 fc0 sc0 ls1e ws1b">resolution (total width up to 4096 pixels, to<span class="_ _0"></span>tal </div><div class="t m0 xe h9 y1c ff1 fs7 fc0 sc0 ls1a ws16">height up to 2048 lines and pixel clock up to </div><div class="t m0 xe h9 y1d ff1 fs7 fc0 sc0 ls14 ws4">83<span class="_"> </span>MHz)</div><div class="t m0 x1 h9 y1e ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls10 wse">Chrom-ART Acce<span class="_ _4"></span>lerator&#8482; for enhan<span class="_ _4"></span>ced </span></div><div class="t m0 xe h9 y1f ff1 fs7 fc0 sc0 ls1a ws16">graphic content creation (DMA2<span class="_ _0"></span>D)</div><div class="t m0 x1 h9 y20 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls1f ws1c">Clock, reset and supply management</span></div><div class="t m0 xe h9 y21 ff1 fs7 fc0 sc0 lsf ws18">&#8211;<span class="_ _6"> </span>1.7<span class="_"> </span>V to 3.6<span class="_"> </span>V application supply and I/Os</div><div class="t m0 xe h9 y22 ff1 fs7 fc0 sc0 ls1a ws16">&#8211;<span class="_ _6"> </span>POR, PDR, PVD and BOR</div><div class="t m0 xe h9 y23 ff1 fs7 fc0 sc0 ls1c ws1d">&#8211;<span class="_ _6"> </span>4-to-26<span class="_"> </span>MHz crystal oscillator</div><div class="t m0 xe h9 y24 ff1 fs7 fc0 sc0 ls1b ws1e">&#8211;<span class="_ _6"> </span>Interna<span class="_ _4"></span>l 16<span class="_"> </span>MHz fac<span class="_ _4"></span>tory-trimme<span class="_ _4"></span>d RC (1% </div><div class="t m0 xf h9 y25 ff1 fs7 fc0 sc0 ls20 ws4">accuracy)</div><div class="t m0 xe h9 y26 ff1 fs7 fc0 sc0 ls21 ws1f">&#8211;<span class="_ _6"> </span>32 kHz oscillator for RTC with calibration</div><div class="t m0 xe h9 y27 ff1 fs7 fc0 sc0 ls11 wsf">&#8211;<span class="_ _6"> </span>Internal 32 kHz RC with c<span class="_ _4"></span>alibration</div><div class="t m0 x1 h9 y28 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _7"> </span><span class="ff1 ls22 ws20">Low power</span></div><div class="t m0 xe h9 y29 ff1 fs7 fc0 sc0 lse ws21">&#8211;<span class="_ _6"> </span>Sleep, S<span class="_ _8"></span>top and S<span class="_ _8"></span>tandby mod<span class="_ _0"></span>es</div><div class="t m0 xe h9 y2a ff1 fs7 fc0 sc0 ls23 ws4">&#8211;V</div><div class="t m0 x10 ha y2b ff1 fs8 fc0 sc0 ls24 ws4">BA<span class="_ _8"></span>T</div><div class="t m0 x11 h9 y2c ff1 fs7 fc0 sc0 ls25 ws22"> supply for R<span class="_ _8"></span>T<span class="_ _4"></span>C, 20&#215;32 bit backup </div><div class="t m0 xf h9 y2d ff1 fs7 fc0 sc0 ls26 ws23">registers + optional 4 KB backu<span class="_ _0"></span>p SRAM</div><div class="t m0 x1 h9 y2e ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls11 wsf">3&#215;12-bit, 2.4<span class="_"> </span>MSPS ADC: <span class="ls27 ws24">up to 24 channels </span></span></div><div class="t m0 xe h9 y2f ff1 fs7 fc0 sc0 lsf ws18">and 7.2<span class="_"> </span>MSPS in triple<span class="ls11 ws25"> interleaved mode</span></div><div class="t m0 x1 h9 y30 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls12 ws26">2&#215;12-bit D/A converters</span></div><div class="t m0 x1 h9 y31 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls16 ws27">General-purpose DM<span class="_ _0"></span>A: 16-stream DMA </span></div><div class="t m0 xe h9 y32 ff1 fs7 fc0 sc0 ls28 ws28">controller with FIFOs and burst support</div><div class="t m0 x1 h9 y33 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls28 ws29">Up to 17 timers: up to twelve 16-<span class="_ _0"></span>bit and two 32-</span></div><div class="t m0 xe h9 y34 ff1 fs7 fc0 sc0 ls29 ws2a">bit timers up to 180<span class="_"> </span>MHz,<span class="_ _4"></span> each with up to 4 </div><div class="t m0 xe h9 y35 ff1 fs7 fc0 sc0 ls1f ws1c">IC/OC/PWM or pulse counter and qua<span class="_ _0"></span>drature </div><div class="t m0 xe h9 y36 ff1 fs7 fc0 sc0 ls2a ws2b">(incremental) en<span class="_ _0"></span>coder input</div><div class="t m0 x12 h9 y37 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls2b ws2c">Debug mode</span></div><div class="t m0 x13 h9 y38 ff1 fs7 fc0 sc0 ls1c ws1d">&#8211;<span class="_ _6"> </span>SWD &amp; JT<span class="_ _8"></span>AG interfaces</div><div class="t m0 x13 h9 y39 ff1 fs7 fc0 sc0 ls1a ws16">&#8211;<span class="_ _6"> </span>Cortex-M4 T<span class="_ _8"></span>race Macrocell&#8482;</div><div class="t m0 x12 h9 y3a ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls11 wsf">Up to 168 I/O ports with interrupt capability</span></div><div class="t m0 x13 h9 y3b ff1 fs7 fc0 sc0 ls1d ws2d">&#8211;<span class="_ _6"> </span>Up to 164 fast I/Os up to 90<span class="_"> </span>MHz</div><div class="t m0 x13 h9 y3c ff1 fs7 fc0 sc0 ls2c ws2e">&#8211;<span class="_ _6"> </span>Up to 166 5<span class="_"> </span>V<span class="_ _8"></span>-toleran<span class="_ _0"></span>t I/Os</div><div class="t m0 x12 h9 y3d ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls13 ws11">Up to 21 communica<span class="ls18 ws2f">tion interfac<span class="_ _4"></span>es</span></span></div><div class="t m0 x13 h9 y3e ff1 fs7 fc0 sc0 lse ws30">&#8211;<span class="_ _6"> </span>Up to 3 &#215; <span class="_ _0"></span>I</div><div class="t m0 x14 ha y3f ff1 fs8 fc0 sc0 ls4 ws4">2</div><div class="t m0 x15 h9 y40 ff1 fs7 fc0 sc0 ls14 ws31">C interfaces (SMBus/PMBus)</div><div class="t m0 x13 h9 y41 ff1 fs7 fc0 sc0 ls26 ws32">&#8211;<span class="_ _6"> </span>Up to 4 USAR<span class="_ _8"></span>T<span class="_ _9"></span>s/4 UAR<span class="_ _0"></span>T<span class="_ _a"></span>s (1<span class="_ _9"></span>1.25<span class="_"> </span>Mbit/s, </div><div class="t m0 x16 h9 y42 ff1 fs7 fc0 sc0 ls26 ws23">ISO7816 interface, LIN, IrDA, modem<span class="_ _0"></span> </div><div class="t m0 x16 h9 y43 ff1 fs7 fc0 sc0 ls2d ws4">control)</div><div class="t m0 x13 h9 y44 ff1 fs7 fc0 sc0 ls1d ws2d">&#8211;<span class="_ _6"> </span>Up to 6 SPIs (45<span class="_"> </span>Mbits/s), 2 with muxed<span class="_ _0"></span> </div><div class="t m0 x16 h9 y45 ff1 fs7 fc0 sc0 ls2e ws33">full-duplex I</div><div class="t m0 x15 ha y46 ff1 fs8 fc0 sc0 ls4 ws4">2</div><div class="t m0 x17 h9 y47 ff1 fs7 fc0 sc0 lsf ws18">S for<span class="fc1 ls4 ws4"> </span><span class="ls2f ws34">audio class accuracy via </span></div><div class="t m0 x16 h9 y48 ff1 fs7 fc0 sc0 ls30 ws35">internal audi<span class="_ _4"></span>o PLL or external cloc<span class="_ _4"></span>k</div><div class="t m0 x13 h9 y49 ff1 fs7 fc0 sc0 ls31 ws36">&#8211;<span class="_ _6"> </span>1 x SAI (serial audio interface)</div><div class="t m0 x13 h9 y4a ff1 fs7 fc0 sc0 ls32 ws37">&#8211;<span class="_ _6"> </span>2 &#215; CAN (2.0B Active<span class="ls30 ws35">) and SDIO interfac<span class="_ _4"></span>e</span></div><div class="t m0 x12 h9 y4b ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls21 ws1f">Advanced connectivity</span></div><div class="t m0 x13 h9 y4c ff1 fs7 fc0 sc0 ls1a ws16">&#8211;<span class="_ _6"> </span>USB 2.0 full-speed device/host/OTG </div><div class="t m0 x16 h9 y4d ff1 fs7 fc0 sc0 ls1e ws38">controller with on-chip<span class="_ _0"></span> PHY</div><div class="t m0 x13 h9 y4e ff1 fs7 fc0 sc0 ls1f ws1c">&#8211;<span class="_ _6"> </span>USB 2.0 high-speed/full-spe<span class="_ _0"></span>ed </div><div class="t m0 x16 h9 y4f ff1 fs7 fc0 sc0 ls1f ws1c">device/host/OTG contro<span class="_ _0"></span>ller with dedicated </div><div class="t m0 x16 h9 y50 ff1 fs7 fc0 sc0 ls28 ws28">DMA, on-chip full-speed PHY and ULPI</div><div class="t m0 x13 h9 y51 ff1 fs7 fc0 sc0 ls28 ws39">&#8211;<span class="_ _6"> </span>10/100 Ethernet MAC with dedicated<span class="_ _0"></span> DMA: </div><div class="t m0 x16 h9 y52 ff1 fs7 fc0 sc0 ls33 ws3a">supports IEEE 1588v2 hardware, MI<span class="_ _4"></span>I/RMII</div><div class="t m0 x12 h9 y53 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls18 ws3b">8- to 14-bit parallel ca<span class="_ _4"></span>mera interfac<span class="_ _4"></span>e up to </span></div><div class="t m0 x13 h9 y54 ff1 fs7 fc0 sc0 ls34 ws4">54<span class="_"> </span>Mbytes/s</div><div class="t m0 x12 h9 y55 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls35 ws3c">True random<span class="_ _0"></span> number g<span class="_ _0"></span>enerator</span></div><div class="t m0 x12 h9 y56 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls14 ws31">CRC calculation unit</span></div><div class="t m0 x12 h9 y57 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls1b ws1e">RTC: subsec<span class="_ _4"></span>ond accura<span class="_ _4"></span>cy, hardware c<span class="_ _4"></span>alendar</span></div><div class="t m0 x12 h9 y58 ff3 fs7 fc0 sc0 ls4 ws4">&#8226;<span class="_ _3"> </span><span class="ff1 ls36 ws3d">96-bit unique ID</span></div><div class="c x12 y59 w2 hb"><div class="t m0 x18 hc y5a ff4 fs0 fc0 sc0 ls0 ws3e">LQFP100 (14 &#215; 14 mm)</div><div class="t m0 x18 hc y5b ff4 fs0 fc0 sc0 ls0 ws3e">LQFP144 (20 &#215; 20 mm)</div><div class="t m0 x19 hc y5c ff4 fs0 fc0 sc0 ls37 ws3f">UFBGA176 (10 x 10 mm)</div><div class="t m0 x18 hc y5d ff4 fs0 fc0 sc0 ls0 ws3e">LQFP176 (24 &#215; 24 mm)</div><div class="t m0 x18 hc y5e ff4 fs0 fc0 sc0 ls0 ws3e">LQFP208 (28 x 28 mm)</div><div class="t m0 x1a hc y5f ff4 fs0 fc0 sc0 ls38 ws4">WLCSP143</div><div class="t m0 x19 hc y60 ff4 fs0 fc0 sc0 ls38 ws40">TFBGA216 (13 x 13 mm)</div><div class="t m0 x1b hc y61 ff4 fs0 fc0 sc0 ls39 ws41">UFBGA169 (7 &#215; 7 mm)</div></div><div class="c x1c y62 w3 hd"><div class="t m0 x1d he y63 ff5 fs9 fc2 sc0 ls4 ws4">&amp;"'!</div></div><div class="t m0 x1e hf y1 ff6 fs0 fc3 sc0 ls3a ws4">www<span class="_ _8"></span>.s<span class="_ _4"></span>t.com</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.140143,0.000000,0.000000,1.140143,0.000000,0.000000]}'></div></div> </body> </html>
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