STM8L051_REFERENCE.rar_STM8L051_其他下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6253556274bc5c0105f2d28b/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253556274bc5c0105f2d28b/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">November 2016<span class="_ _0"> </span>DocID15226 Rev 1<span class="_ _1"></span>2<span class="_ _2"> </span>1/595</div><div class="t m0 x2 h3 y2 ff1 fs1 fc1 sc0 ls1 ws1">1</div><div class="t m0 x3 h4 y3 ff2 fs2 fc0 sc0 ls2 ws1">RM0031</div><div class="t m0 x4 h4 y4 ff2 fs2 fc0 sc0 ls3 ws2">Reference manual</div><div class="t m0 x5 h5 y5 ff1 fs3 fc0 sc0 ls4 ws3">STM8L051/L052 V<span class="_ _3"></span>alue Line, STM8L151/L152, STM8L162, </div><div class="t m0 x6 h5 y6 ff1 fs3 fc0 sc0 ls4 ws3">STM8AL31, STM8AL3L MCU lines</div><div class="t m0 x7 h6 y7 ff2 fs4 fc0 sc0 ls5 ws1">Introduction</div><div class="t m0 x7 h7 y8 ff1 fs5 fc0 sc0 ls6 ws4">This reference manual <span class="_ _4"></span>target<span class="_ _4"></span>s application deve<span class="ls7 ws5">loper<span class="_ _4"></span>s. It provides co<span class="ls8 ws6">mplete information on </span></span></div><div class="t m0 x7 h7 y9 ff1 fs5 fc0 sc0 ls9 ws7">how to use STM8L051/L052<span class="_ _4"></span> V<span class="_ _5"></span>alue Line, STM8L151/L1<span class="_ _4"></span>52, STM8L162, STM8AL<span class="_ _4"></span>31 and </div><div class="t m0 x7 h7 ya ff1 fs5 fc0 sc0 lsa ws8">STM8AL line microcontrolle<span class="_ _4"></span>r memory and peripherals. STM8L<span class="_ _4"></span>xxx line and STM8ALxx line </div><div class="t m0 x7 h7 yb ff1 fs5 fc0 sc0 lsb ws9">microcontrollers include familie<span class="lsc wsa">s with different memory densit<span class="lsd wsb">ies, packages and peripherals. </span></span></div><div class="t m0 x7 h7 yc ff1 fs5 fc0 sc0 lsa ws8">These product<span class="_ _4"></span>s are designed for ultra-<span class="_ _4"></span>low-power applications. Refer to the produ<span class="_ _4"></span>ct </div><div class="t m0 x7 h7 yd ff1 fs5 fc0 sc0 lse wsc">datasheet<span class="_ _4"></span>s for the complete list of available<span class="_ _4"></span> peripherals.</div><div class="t m0 x7 h7 ye ff1 fs5 fc0 sc0 lsf wsd">For ordering information, pi<span class="_ _4"></span>n description, mechan<span class="ls6 wse">ical and electrical de<span class="ls10 wsf">vice characteristics, </span></span></div><div class="t m0 x7 h7 yf ff1 fs5 fc0 sc0 ls11 ws10">please refer to the product dat<span class="_ _4"></span>asheet<span class="_ _4"></span>s. For information on the STM8 SWIM<span class="_ _4"></span> communication </div><div class="t m0 x7 h7 y10 ff1 fs5 fc0 sc0 ls12 ws11">protocol and debug mod<span class="_ _4"></span>ule, please refer to the user manual (<span class="_ _4"></span>UM0470). For informa<span class="_ _4"></span>tion on </div><div class="t m0 x7 h7 y11 ff1 fs5 fc0 sc0 ls11 ws10">the STM8 core, please refer to the STM8 CPU progr<span class="_ _4"></span>amming manual (PM0044<span class="_ _4"></span>). For </div><div class="t m0 x7 h7 y12 ff1 fs5 fc0 sc0 ls13 ws12">information on progr<span class="_ _4"></span>amming, erasing and protec<span class="_ _4"></span><span class="lsa ws8">tion of the internal Flash memor<span class="_ _4"></span>y please </span></div><div class="t m0 x7 h7 y13 ff1 fs5 fc0 sc0 ls13 ws12">refer to the STM8L Flash programm<span class="_ _4"></span>ing manual (PM0054).</div><div class="t m0 x7 h7 y14 ff1 fs5 fc0 sc0 ls14 ws13">This document covers:</div><div class="t m0 x7 h7 y15 ff2 fs5 fc0 sc0 ls15 ws14">V<span class="_ _5"></span>alue line low-density STM8L05xx devices:<span class="_ _4"></span><span class="ff1 lsa ws8"> STM8L051F3 microcontr<span class="_ _4"></span>ollers with 8-KB </span></div><div class="t m0 x7 h7 y16 ff1 fs5 fc0 sc0 ls12 ws1">Flash.</div><div class="t m0 x8 h8 y17 ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y18 ff2 fs5 fc0 sc0 ls15 ws14">V<span class="_ _5"></span>alue line medium-density STM8L05xx devices<span class="_ _4"></span>:<span class="ff1 lse wsc"> STM8L052C6 microcontrollers with 32-</span></div><div class="t m0 x7 h7 y19 ff1 fs5 fc0 sc0 ls16 ws15">KB Flash.</div><div class="t m0 x9 h8 y1a ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y1b ff2 fs5 fc0 sc0 ls9 ws7">V<span class="_ _5"></span>alue line high-density STM8L05xx dev<span class="_ _4"></span>ices:<span class="ff1 ls17 ws16"> STM8L052R8 micro<span class="_ _4"></span>controllers with 64-KB </span></div><div class="t m0 x7 h7 y1c ff1 fs5 fc0 sc0 ls12 ws1">Flash.</div><div class="t m0 x8 h8 y1d ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y1e ff2 fs5 fc0 sc0 ls18 ws17">Low-density STM8<span class="_ _4"></span>L15x devices: <span class="ff1 ls12 ws18">STM8L15<span class="_ _4"></span>1C2/K2/G2/F2, STM8L151C3<span class="_ _4"></span>/K3/G3/F3 </span></div><div class="t m0 x7 h7 y1f ff1 fs5 fc0 sc0 ls19 ws19">microcontrollers with 4-KB or 8-KB Flash.</div><div class="t m0 xa h8 y20 ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y21 ff2 fs5 fc0 sc0 ls1a ws1a">Medium-density STM8L15<span class="_ _4"></span>xx devices: <span class="ff1 ls13 ws1b">STM8L151C4/K4/G4<span class="_ _4"></span>, STM8L151C6<span class="_ _4"></span>/K6/G6, </span></div><div class="t m0 x7 h7 y22 ff1 fs5 fc0 sc0 ls11 ws10">STM8L152C4/K4 and STM8L152C6/K6 micr<span class="_ _4"></span>oc<span class="lse wsc">ontrollers with 16-KB or 32-KB Flash.</span></div><div class="t m0 xb h8 y23 ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y24 ff2 fs5 fc0 sc0 ls1b ws1c">Medium-density STM8AL<span class="_ _4"></span>313x/4x/6x and<span class="_ _4"></span> STM8AL3L4x/6x devices:<span class="ff1 lsd ws1d"> STM8AL3168, </span></div><div class="t m0 x7 h7 y25 ff1 fs5 fc0 sc0 ls9 ws7">STM8AL3166, STM8AL3<span class="_ _4"></span>148,STM8AL3146, STM8AL3<span class="_ _4"></span>138, STM8AL3136, STM8<span class="_ _4"></span>AL3L68, </div><div class="t m0 x7 h7 y26 ff1 fs5 fc0 sc0 ls12 ws11">STM8AL3L66, STM8AL3L48<span class="_ _4"></span>, STM8AL3L46 microcontr<span class="_ _4"></span>ollers with 8-KB, 16-KB or 32-KB </div><div class="t m0 x7 h7 y27 ff1 fs5 fc0 sc0 ls12 ws1">Flash.</div><div class="t m0 x8 h8 y28 ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y29 ff2 fs5 fc0 sc0 ls1c ws1e">Medium+ density STM8L15xx devic<span class="_ _4"></span>es: <span class="ff1 ls9 ws1f">STM8L151R6 and STM8L<span class="_ _4"></span>152R6 micr<span class="_ _4"></span>ocontrollers </span></div><div class="t m0 x7 h7 y2a ff1 fs5 fc0 sc0 lse wsc">with 32-KB Flash (Wider range of perip<span class="ls13 ws12">her<span class="_ _4"></span>als than medium-density devices)<span class="_ _4"></span>.</span></div><div class="t m0 xc h8 y2b ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y2c ff2 fs5 fc0 sc0 ls15 ws14">High-density STM8AL318x an<span class="_ _4"></span>d STM8AL3L8x devices:<span class="ff1 ls6 ws4"> STM8AL318A<span class="_ _3"></span>T<span class="_ _3"></span>, STM8AL3189, </span></div><div class="t m0 x7 h7 y2d ff1 fs5 fc0 sc0 ls1d ws20">STM8AL3188, STM8AL3L8A, ST<span class="ls1e ws21">M8AL3L89, <span class="_ _1"></span>STM8AL3L88<span class="_ _1"></span> microcontr<span class="_ _1"></span>ollers with 64<span class="_ _1"></span>-KB </span></div><div class="t m0 x7 h7 y2e ff1 fs5 fc0 sc0 ls12 ws1">Flash.</div><div class="t m0 x8 h8 y2f ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y30 ff2 fs5 fc0 sc0 ls1a ws1a">High-density STM8AL31E8<span class="_ _4"></span>8 and STM8AL3LE88 devices: <span class="_ _4"></span><span class="ff1 ls12 ws1">STM8AL31E88, </span></div><div class="t m0 x7 h7 y31 ff1 fs5 fc0 sc0 ls1f ws22">STM8AL3LE88 microcontrollers<span class="lsf wsd"> with 64-KB Flash (same peripheral set as high-d<span class="_ _4"></span>ensity </span></div><div class="t m0 x7 h7 y32 ff1 fs5 fc0 sc0 ls6 wse">STM8AL318x and STM8AL<span class="ls1d ws23">3L8x plus the AES hard<span class="ls20 ws24">ware accelerator).</span></span></div><div class="t m0 xd h8 y33 ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y34 ff2 fs5 fc0 sc0 ls13 ws12">High-density STM8L15xx device<span class="_ _4"></span>s: <span class="ff1 ls21 ws25">STM8L151C8<span class="_ _4"></span>/M8/R8 and<span class="_ _4"></span> the STM8L152C8<span class="_ _4"></span>/M8/R8 </span></div><div class="t m0 x7 h7 y35 ff1 fs5 fc0 sc0 lsf wsd">microcontrollers with 64-KB Flash (<span class="_ _4"></span>Same peripheral set as medium+).</div><div class="t m0 xe h8 y36 ff3 fs5 fc0 sc0 ls1 ws1"> </div><div class="t m0 x7 h7 y37 ff2 fs5 fc0 sc0 ls13 ws12">High-density STM8L16xx device<span class="_ _4"></span>s:<span class="ff1 ls22 ws26"> STM8L162M8/R8 micr<span class="_ _1"></span>ocontrollers<span class="_ _1"></span> with 64-KB Flash </span></div><div class="t m0 x7 h7 y38 ff1 fs5 fc0 sc0 ls1c ws27">(Same periphe<span class="_ _4"></span>ral set as high<span class="_ _4"></span>-density STM8L152 device<span class="_ _4"></span>s plus the AES <span class="_ _4"></span>hardware </div><div class="t m0 x7 h7 y39 ff1 fs5 fc0 sc0 ls15 ws1">accelerator).</div><div class="t m0 xf h9 y2 ff4 fs1 fc2 sc0 ls23 ws1">www<span class="_ _4"></span>.st.com</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253556274bc5c0105f2d28b/bg2.jpg"><div class="t m0 x1 ha y3a ff2 fs5 fc0 sc0 ls13 ws1">Contents<span class="_ _6"> </span><span class="ls1b">RM0031</span></div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls24 ws28">2/595<span class="_ _2"> </span>DocID1<span class="_ _1"></span>5226 Rev 12</div><div class="t m0 x1 hb y3b ff2 fs6 fc0 sc0 ls25 ws1">Content<span class="_ _4"></span>s</div><div class="t m0 x1 hc y3c ff2 fs7 fc0 sc0 ls26 ws29">1<span class="_ _7"> </span>Central processing unit (CPU) <span class="_ _8"> </span>. <span class="ls27 ws2a">. . . . . . . . . . . . . . . . <span class="ls28 ws2b">. . . . . . . . . . . . . . . <span class="_ _9"></span>30</span></span></div><div class="t m0 x7 hd y3d ff1 fs8 fc0 sc0 ls29 ws1">1.1<span class="_ _a"> </span>Introduction <span class="_"> </span> . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>30</div><div class="t m0 x7 hd y3e ff1 fs8 fc0 sc0 ls29 ws1">1.2<span class="_ _a"> </span>CPU registers <span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>30</div><div class="t m0 x10 h7 y3f ff1 fs5 fc0 sc0 ls1 ws2c">1.2.1<span class="_ _a"> </span>Description of CPU <span class="_ _1"></span>registers <span class="_"> </span>. . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 30</div><div class="t m0 x10 h7 y40 ff1 fs5 fc0 sc0 ls2a ws2c">1.2.2<span class="_ _a"> </span>STM8 CPU regis<span class="_ _1"></span>ter map <span class="_ _1"></span> . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 34</div><div class="t m0 x7 hd y41 ff1 fs8 fc0 sc0 ls2b ws2d">1.3<span class="_ _a"> </span>Global configuration register (CFG_GCR) <span class="_ _8"> </span>. . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>34</div><div class="t m0 x10 h7 y42 ff1 fs5 fc0 sc0 ls2c ws2e">1.3.1<span class="_ _a"> </span>Activation level <span class="_ _9"></span>. . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 34</div><div class="t m0 x10 h7 y43 ff1 fs5 fc0 sc0 ls2c ws2e">1.3.2<span class="_ _a"> </span>SWIM dis<span class="_ _1"></span>able <span class="_ _1"></span>. . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 34</div><div class="t m0 x10 h7 y44 ff1 fs5 fc0 sc0 ls10 wsf">1.3.3<span class="_ _a"> </span>Description of global configuration register (CFG_GC<span class="_ _1"></span>R) <span class="_ _c"></span>. . . . . . . .<span class="_ _1"></span> . . . . 35</div><div class="t m0 x10 h7 y45 ff1 fs5 fc0 sc0 ls16 ws2f">1.3.4<span class="_ _a"> </span>Global configuration register <span class="_ _4"></span>map and re<span class="ls1 ws2c">set values <span class="_"> </span> . . . . . . . . . . . . . . <span class="_ _1"></span>. 35</span></div><div class="t m0 x1 hc y46 ff2 fs7 fc0 sc0 ls2d ws30">2<span class="_ _7"> </span>Boot ROM <span class="_ _c"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="ws2b">. . . . . . . . . . . . <span class="ls28 ws31">. . . . . . . . . . . <span class="_ _9"></span>36</span></span></div><div class="t m0 x1 hc y47 ff2 fs7 fc0 sc0 ls2e ws32">3<span class="_ _7"> </span>Flash prog<span class="_ _1"></span>ram memory and data EEPROM <span class="_ _d"> </span> <span class="ls2f ws33">. . . . . . . . . . . <span class="ls26 ws34">. . . . . . . . . . <span class="_ _9"></span>37</span></span></div><div class="t m0 x7 hd y48 ff1 fs8 fc0 sc0 ls29 ws1">3.1<span class="_ _a"> </span>Introduction <span class="_"> </span> . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>37</div><div class="t m0 x7 hd y49 ff1 fs8 fc0 sc0 ls29 ws1">3.2<span class="_ _a"> </span>Glossary <span class="_ _d"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>37</div><div class="t m0 x7 hd y4a ff1 fs8 fc0 sc0 ls29 ws1">3.3<span class="_ _a"> </span>Main Flash memory features <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>38</div><div class="t m0 x7 hd y4b ff1 fs8 fc0 sc0 ls29 ws1">3.4<span class="_ _a"> </span>Memory organization <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>39</div><div class="t m0 x10 h7 y4c ff1 fs5 fc0 sc0 ls16 ws2f">3.4.1<span class="_ _a"> </span>Low-density device memory o<span class="_ _4"></span>rganization <span class="_ _1"></span> <span class="ls30 ws35">. . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 39</span></div><div class="t m0 x10 h7 y4d ff1 fs5 fc0 sc0 ls1c ws36">3.4.2<span class="_ _a"> </span>Medium-density device memo<span class="ls31 ws37">ry organization <span class="_ _b"> </span>. . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 40</span></div><div class="t m0 x10 h7 y4e ff1 fs5 fc0 sc0 ls32 ws38">3.4.3<span class="_ _a"> </span>Medium+ density dev<span class="_ _1"></span>ice memory organization <span class="_ _1"></span> . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 41</div><div class="t m0 x10 h7 y4f ff1 fs5 fc0 sc0 ls32 ws38">3.4.4<span class="_ _a"> </span>High-density device <span class="_ _1"></span>memory organization <span class="_ _9"></span>. . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 42</div><div class="t m0 x10 h7 y50 ff1 fs5 fc0 sc0 ls31 ws37">3.4.5<span class="_ _a"> </span> Proprietary code area (PCODE) <span class="_ _d"> </span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 43</div><div class="t m0 x10 h7 y51 ff1 fs5 fc0 sc0 ls33 ws39">3.4.6<span class="_ _a"> </span>User boot area (UBC) <span class="_ _d"> </span> . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 43</div><div class="t m0 x10 h7 y52 ff1 fs5 fc0 sc0 lsc ws3a">3.4.7<span class="_ _a"> </span>Data EEPROM (DA<span class="_ _5"></span>T<span class="_ _5"></span>A) <span class="_ _d"> </span> . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . 46</div><div class="t m0 x10 h7 y53 ff1 fs5 fc0 sc0 ls31 ws37">3.4.8<span class="_ _a"> </span>Main program area <span class="_"> </span> . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 46</div><div class="t m0 x10 h7 y54 ff1 fs5 fc0 sc0 ls2c ws2e">3.4.9<span class="_ _a"> </span>Option bytes <span class="_ _c"></span>. . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 46</div><div class="t m0 x7 hd y55 ff1 fs8 fc0 sc0 ls29 ws1">3.5<span class="_ _a"> </span>Memory protection . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>47</div><div class="t m0 x10 h7 y56 ff1 fs5 fc0 sc0 ls1 ws2c">3.5.1<span class="_ _a"> </span>Readout protection <span class="_"> </span> . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 47</div><div class="t m0 x10 h7 y57 ff1 fs5 fc0 sc0 ls1f ws22">3.5.2<span class="_ _a"> </span>Memory access security sys<span class="lsb ws3b">tem (MASS) <span class="_ _8"> </span> . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . <span class="_ _1"></span>. 47</span></div><div class="t m0 x10 h7 y58 ff1 fs5 fc0 sc0 ls31 ws37">3.5.3<span class="_ _a"> </span>Enabling write acc<span class="_ _1"></span>ess to option bytes <span class="_ _c"></span> . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 48</div><div class="t m0 x7 hd y59 ff1 fs8 fc0 sc0 ls29 ws1">3.6<span class="_ _a"> </span>Memory programming <span class="_ _d"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>49</div><div class="t m0 x10 h7 y5a ff1 fs5 fc0 sc0 ls2a ws3c">3.6.1<span class="_ _a"> </span>Read-while-write (RWW) <span class="_ _b"> </span>. . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 49</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a 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<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253556274bc5c0105f2d28b/bg3.jpg"><div class="t m0 x11 h2 y1 ff1 fs0 fc0 sc0 ls0 ws3d">DocID15226 Rev 12<span class="_ _2"> </span>3/595</div><div class="t m0 x1 ha y3a ff2 fs5 fc0 sc0 ls1b ws1">RM0031<span class="_ _6"> </span><span class="ls34">Contents</span></div><div class="t m0 x2 h3 y2 ff1 fs1 fc1 sc0 ls35 ws1">22</div><div class="t m0 x10 h7 y5b ff1 fs5 fc0 sc0 ls2a ws3c">3.6.2<span class="_ _a"> </span>Byte programming <span class="_"> </span>. . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 49</div><div class="t m0 x10 h7 y5c ff1 fs5 fc0 sc0 ls31 ws37">3.6.3<span class="_ _a"> </span>Word programming <span class="_ _d"> </span> . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . 50</div><div class="t m0 x10 h7 y5d ff1 fs5 fc0 sc0 ls32 ws38">3.6.4<span class="_ _a"> </span>Block programming <span class="_ _9"></span> . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . <span class="ls30 ws35">. .<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 50</span></div><div class="t m0 x10 h7 y5e ff1 fs5 fc0 sc0 ls31 ws37">3.6.5<span class="_ _a"> </span>Option byte programming <span class="_ _8"> </span> . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 52</div><div class="t m0 x7 hd y5f ff1 fs8 fc0 sc0 ls36 ws3e">3.7<span class="_ _a"> </span>Flash low-power modes <span class="_ _8"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>52</div><div class="t m0 x7 hd y60 ff1 fs8 fc0 sc0 ls29 ws1">3.8<span class="_ _a"> </span>ICP and IAP <span class="_"> </span>. . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>52</div><div class="t m0 x7 hd y61 ff1 fs8 fc0 sc0 ls29 ws1">3.9<span class="_ _a"> </span>Flash registers <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>57</div><div class="t m0 x10 h7 y62 ff1 fs5 fc0 sc0 ls31 ws37">3.9.1<span class="_ _a"> </span>Flash control register <span class="_ _1"></span>1 (FLASH_CR1) <span class="_ _d"> </span> . . . . . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _1"></span>57</div><div class="t m0 x10 h7 y63 ff1 fs5 fc0 sc0 ls31 ws37">3.9.2<span class="_ _a"> </span>Flash control register <span class="_ _1"></span>2 (FLASH_CR2) <span class="_ _d"> </span> . . . . . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _1"></span>58</div><div class="t m0 x10 h7 y64 ff1 fs5 fc0 sc0 lsf wsd">3.9.3<span class="_ _a"> </span>Flash program memory unprotecting key register (F<span class="_ _4"></span>LASH_PUKR) <span class="_ _8"> </span> . . . 58</div><div class="t m0 x10 h7 y65 ff1 fs5 fc0 sc0 ls7 ws5">3.9.4<span class="_ _a"> </span>Data EEPROM unprotection<span class="lsc ws3a"> key register (FLASH_DUK<span class="lsb ws3b">R) <span class="_ _d"> </span>. . . . . . . . . <span class="_ _1"></span>. 59</span></span></div><div class="t m0 x10 h7 y66 ff1 fs5 fc0 sc0 ls37 ws3f">3.9.5<span class="_ _a"> </span>Flash status regi<span class="ls20 ws40">ster (FLASH_IAPSR) <span class="_ _c"></span>. . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . 59</span></div><div class="t m0 x10 h7 y67 ff1 fs5 fc0 sc0 lsf ws41">3.9.6<span class="_ _a"> </span>Flash register map a<span class="_ _4"></span>nd reset values . . . <span class="ls30 ws35">. . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 60</span></div><div class="t m0 x1 hc y68 ff2 fs7 fc0 sc0 ls38 ws42">4<span class="_ _7"> </span>Single wire interface module (SWIM)<span class="ls26 ws31"> and debug module (DM) <span class="_ _e"> </span> . . . . . <span class="_ _9"></span>61</span></div><div class="t m0 x7 hd y69 ff1 fs8 fc0 sc0 ls29 ws1">4.1<span class="_ _a"> </span>Introduction <span class="_"> </span> . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>61</div><div class="t m0 x7 hd y6a ff1 fs8 fc0 sc0 ls29 ws1">4.2<span class="_ _a"> </span>Main features . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>61</div><div class="t m0 x7 hd y6b ff1 fs8 fc0 sc0 ls29 ws1">4.3<span class="_ _a"> </span>SWIM modes <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>61</div><div class="t m0 x1 hc y6c ff2 fs7 fc0 sc0 ls39 ws43">5<span class="_ _7"> </span>Memory and register map . . . . <span class="ls2f ws33">. . . . . . . . . . . . . . . . . <span class="ls28 ws2b">. . . . . . . . . . . . . . . <span class="_ _9"></span>62</span></span></div><div class="t m0 x7 hd y6d ff1 fs8 fc0 sc0 ls2b ws2d">5.1<span class="_ _a"> </span>Register description abbreviations <span class="_ _d"> </span>. . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>62</div><div class="t m0 x1 hc y6e ff2 fs7 fc0 sc0 ls3a ws44">6<span class="_ _7"> </span>Power control (PWR) . . . . . . . <span class="ls2f ws33">. . . . . . . . . . . . . . . . . <span class="ls3b ws45">. . . . . . . . . . . . . . . . <span class="_ _9"></span>63</span></span></div><div class="t m0 x7 hd y6f ff1 fs8 fc0 sc0 ls29 ws1">6.1<span class="_ _a"> </span>Power supply <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>63</div><div class="t m0 x7 hd y70 ff1 fs8 fc0 sc0 ls3c ws46">6.2<span class="_ _a"> </span>Power-on reset (POR)/power-down reset (PDR) <span class="_ _d"> </span>. . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>64</div><div class="t m0 x7 hd y71 ff1 fs8 fc0 sc0 ls2b ws2d">6.3<span class="_ _a"> </span>Brownout reset (BOR) <span class="_ _9"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>65</div><div class="t m0 x7 hd y72 ff1 fs8 fc0 sc0 ls29 ws1">6.4<span class="_ _a"> </span>Programmable voltage detect<span class="_ _4"></span>or (PVD) <span class="_ _b"> </span> . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>66</div><div class="t m0 x7 hd y73 ff1 fs8 fc0 sc0 ls2b ws2d">6.5<span class="_ _a"> </span>Internal voltage re<span class="_ _4"></span>ference (VREFINT) <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>67</div><div class="t m0 x7 hd y74 ff1 fs8 fc0 sc0 ls29 ws1">6.6<span class="_ _a"> </span>V<span class="_ _5"></span>oltage regulator <span class="_ _d"> </span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>68</div><div class="t m0 x7 hd y75 ff1 fs8 fc0 sc0 ls36 ws3e">6.7<span class="_ _a"> </span>PWR registers <span class="_ _d"> </span> . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>69</div><div class="t m0 x10 h7 y76 ff1 fs5 fc0 sc0 lsf wsd">6.7.1<span class="_ _a"> </span>Power control and status registe<span class="_ _4"></span>r 1 (P<span class="ls1 ws2c">WR_CSR1) <span class="_ _f"> </span> . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 69</span></div><div class="t m0 x10 h7 y77 ff1 fs5 fc0 sc0 ls3d ws47">6.7.2<span class="_ _a"> </span>PWR control and status regis<span class="_ _1"></span>ter 2 (PWR_CSR2) <span class="_ _c"></span> . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _1"></span>70</div><div class="t m0 x10 h7 y78 ff1 fs5 fc0 sc0 ls32 ws38">6.7.3<span class="_ _a"> </span>PWR register map and res<span class="_ _1"></span>et values <span class="_ _d"> </span> . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . 70</div><div class="t m0 x1 hc y79 ff2 fs7 fc0 sc0 ls3e ws48">7<span class="_ _7"> </span>Low power modes <span class="_ _f"> </span>. . . . <span class="ls3b ws49">. . . . . . . . . . . . . <span class="ls27 ws4a">. . . . . . . . . . . . . <span class="ls1 ws1">. . . . . . . . . . . . <span class="_ _9"></span>71</span></span></span></div><div class="t m0 x7 hd y7a ff1 fs8 fc0 sc0 ls29 ws1">7.1<span class="_ _a"> </span>Slowing down the system clocks <span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>72</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253556274bc5c0105f2d28b/bg4.jpg"><div class="t m0 x1 ha y3a ff2 fs5 fc0 sc0 ls13 ws1">Contents<span class="_ _6"> </span><span class="ls1b">RM0031</span></div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls24 ws28">4/595<span class="_ _2"> </span>DocID1<span class="_ _1"></span>5226 Rev 12</div><div class="t m0 x7 hd y7b ff1 fs8 fc0 sc0 ls29 ws1">7.2<span class="_ _a"> </span>Peripheral clock gating (PCG) <span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>72</div><div class="t m0 x7 hd y7c ff1 fs8 fc0 sc0 ls2b ws2d">7.3<span class="_ _a"> </span>W<span class="_ _4"></span>ait mode (WFI or WFE mode) <span class="_ _f"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>72</div><div class="t m0 x7 hd y7d ff1 fs8 fc0 sc0 ls29 ws1">7.4<span class="_ _a"> </span>W<span class="_ _4"></span>ait for inte<span class="_ _4"></span>rrupt (WFI) mode <span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>73</div><div class="t m0 x7 hd y7e ff1 fs8 fc0 sc0 ls29 ws1">7.5<span class="_ _a"> </span>W<span class="_ _4"></span>ait for eve<span class="_ _4"></span>nt (WFE) mode <span class="_ _9"></span> . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>73</div><div class="t m0 x10 h7 y7f ff1 fs5 fc0 sc0 ls2c ws2e">7.5.1<span class="_ _a"> </span>WFE registers <span class="_ _d"> </span> . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 74</div><div class="t m0 x10 h7 y80 ff1 fs5 fc0 sc0 ls3f ws4b">7.5.2<span class="_ _a"> </span>WF<span class="_ _1"></span>E register m<span class="_ _1"></span>ap and re<span class="_ _1"></span>set values <span class="_"> </span> . . . <span class="ls30 ws35">.<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 79</span></div><div class="t m0 x7 hd y81 ff1 fs8 fc0 sc0 ls29 ws1">7.6<span class="_ _a"> </span>Low power run mode <span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>80</div><div class="t m0 x10 h7 y82 ff1 fs5 fc0 sc0 ls40 ws4c">7.6.1<span class="_ _a"> </span>En<span class="_ _1"></span>tering Low powe<span class="_ _1"></span>r run mode <span class="_ _9"></span><span class="ls22 ws4d">. . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 80</span></div><div class="t m0 x10 h7 y83 ff1 fs5 fc0 sc0 ls41 ws4e">7.6.2<span class="_ _a"> </span>Exiting Low pow<span class="_ _1"></span>er run mode <span class="_"> </span>. . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 80</div><div class="t m0 x7 hd y84 ff1 fs8 fc0 sc0 ls29 ws1">7.7<span class="_ _a"> </span>Low power wait mode . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>80</div><div class="t m0 x7 hd y85 ff1 fs8 fc0 sc0 ls29 ws1">7.8<span class="_ _a"> </span>Halt mode <span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>81</div><div class="t m0 x10 h7 y86 ff1 fs5 fc0 sc0 ls1 ws2c">7.8.1<span class="_ _a"> </span>Entering Halt mode <span class="_ _d"> </span> . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . 81</div><div class="t m0 x10 h7 y87 ff1 fs5 fc0 sc0 ls42 ws4f">7.8.2<span class="_ _a"> </span>Exiting H<span class="_ _1"></span>alt mode <span class="_ _1"></span>. . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 81</div><div class="t m0 x7 hd y88 ff1 fs8 fc0 sc0 ls29 ws1">7.9<span class="_ _a"> </span>Active-halt mode . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>82</div><div class="t m0 x1 hc y89 ff2 fs7 fc0 sc0 ls43 ws33">8<span class="_ _7"> </span>Reset (RST) <span class="_ _f"></span> . . . . . . . . . . . . <span class="ls2d ws30">. . . . . . . . . . . . <span class="ws2b">. . . . . . . . . . . . <span class="ls28 ws31">. . . . . . . . . . . <span class="_ _9"></span>83</span></span></span></div><div class="t m0 x7 hd y8a ff1 fs8 fc0 sc0 ls29 ws1">8.1<span class="_ _a"> </span>“Reset state” an<span class="_ _4"></span>d “under reset” definitions <span class="_ _f"></span>. . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>83</div><div class="t m0 x7 hd y8b ff1 fs8 fc0 sc0 ls29 ws1">8.2<span class="_ _a"> </span>External reset (NRST pin) <span class="_ _d"> </span> . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>83</div><div class="t m0 x10 h7 y8c ff1 fs5 fc0 sc0 ls34 ws50">8.2.1<span class="_ _a"> </span>Asynchronous external reset description <span class="_ _c"></span>. . <span class="ls30 ws35">. . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 83</span></div><div class="t m0 x10 h7 y8d ff1 fs5 fc0 sc0 ls34 ws51">8.2.2<span class="_ _a"> </span>Configuring NRST/P<span class="_ _5"></span>A1 pin as general purpose output . . . . . . . . . . . . . 84</div><div class="t m0 x7 hd y8e ff1 fs8 fc0 sc0 ls29 ws1">8.3<span class="_ _a"> </span>Internal reset <span class="_ _8"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>84</div><div class="t m0 x10 h7 y8f ff1 fs5 fc0 sc0 ls31 ws37">8.3.1<span class="_ _a"> </span>Power-on reset (PO<span class="_ _1"></span>R) <span class="_ _d"> </span>. .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>84</div><div class="t m0 x10 h7 y90 ff1 fs5 fc0 sc0 ls33 ws39">8.3.2<span class="_ _a"> </span>Independent watchdog reset <span class="_"> </span>. . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 84</div><div class="t m0 x10 h7 y91 ff1 fs5 fc0 sc0 ls31 ws37">8.3.3<span class="_ _a"> </span>Window watchdog reset <span class="_ _c"></span>. . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 84</div><div class="t m0 x10 h7 y92 ff1 fs5 fc0 sc0 ls42 ws4f">8.3.4<span class="_ _a"> </span>SWIM reset <span class="_ _d"> </span> . . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>84</div><div class="t m0 x10 h7 y93 ff1 fs5 fc0 sc0 ls31 ws37">8.3.5<span class="_ _a"> </span>Illegal opcode reset <span class="_ _c"></span> . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 84</div><div class="t m0 x7 hd y94 ff1 fs8 fc0 sc0 ls29 ws1">8.4<span class="_ _a"> </span>RST registers <span class="_ _8"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>85</div><div class="t m0 x10 h7 y95 ff1 fs5 fc0 sc0 ls44 ws52">8.4.1<span class="_ _a"> </span>Reset pin configuration register (RST_CR) <span class="_ _8"> </span>. . . <span class="_ _1"></span>. . . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 85</div><div class="t m0 x10 h7 y96 ff1 fs5 fc0 sc0 ls31 ws37">8.4.2<span class="_ _a"> </span>Reset status register (RST_SR) <span class="_ _b"> </span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . 85</div><div class="t m0 x10 h7 y97 ff1 fs5 fc0 sc0 ls45 ws53">8.4.3<span class="_ _a"> </span>RST<span class="_ _1"></span> register map an<span class="_ _1"></span>d reset values <span class="_ _8"> </span>. . . . <span class="ls30 ws35">. . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 86</span></div><div class="t m0 x1 hc y98 ff2 fs7 fc0 sc0 ls26 ws54">9<span class="_ _7"> </span>Clock control (CLK) . . . . . . . . <span class="ls2f ws33">. . . . . . . . . . . . . . . . . <span class="ls3b ws45">. . . . . . . . . . . . . . . . <span class="_ _9"></span>87</span></span></div><div class="t m0 x7 hd y99 ff1 fs8 fc0 sc0 ls29 ws1">9.1<span class="_ _a"> </span>Introduction <span class="_"> </span> . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>87</div><div class="t m0 x7 hd y9a ff1 fs8 fc0 sc0 ls29 ws1">9.2<span class="_ _a"> </span>HSE clock <span class="_ _c"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _b"> </span>88</div><div class="t m0 x7 hd y9b ff1 fs8 fc0 sc0 ls29 ws1">9.3<span class="_ _a"> </span>HSI clock <span class="_ _d"> </span> . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>90</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6253556274bc5c0105f2d28b/bg5.jpg"><div class="t m0 x11 h2 y1 ff1 fs0 fc0 sc0 ls0 ws3d">DocID15226 Rev 12<span class="_ _2"> </span>5/595</div><div class="t m0 x1 ha y3a ff2 fs5 fc0 sc0 ls1b ws1">RM0031<span class="_ _6"> </span><span class="ls34">Contents</span></div><div class="t m0 x2 h3 y2 ff1 fs1 fc1 sc0 ls35 ws1">22</div><div class="t m0 x7 hd y7b ff1 fs8 fc0 sc0 ls2b ws2d">9.4<span class="_ _a"> </span>LSE clock <span class="_ _b"> </span>. . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>91</div><div class="t m0 x7 hd y7c ff1 fs8 fc0 sc0 ls2b ws2d">9.5<span class="_ _a"> </span>LSI clock <span class="_ _c"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>91</div><div class="t m0 x7 hd y7d ff1 fs8 fc0 sc0 ls29 ws1">9.6<span class="_ _a"> </span>System clock sources . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>92</div><div class="t m0 x10 h7 y9c ff1 fs5 fc0 sc0 ls2c ws2e">9.6.1<span class="_ _a"> </span>System startup <span class="_ _9"></span>. <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . 92</div><div class="t m0 x10 h7 y9d ff1 fs5 fc0 sc0 ls31 ws37">9.6.2<span class="_ _a"> </span>System clock <span class="_ _1"></span>switching procedures <span class="_ _9"></span>. . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 92</div><div class="t m0 x7 hd y9e ff1 fs8 fc0 sc0 ls29 ws1">9.7<span class="_ _a"> </span>Peripheral clock gating (PCG) <span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>95</div><div class="t m0 x7 hd y9f ff1 fs8 fc0 sc0 ls2b ws2d">9.8<span class="_ _a"> </span>Clock security system (CSS) <span class="_ _c"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>95</div><div class="t m0 x10 h7 y82 ff1 fs5 fc0 sc0 ls3d ws47">9.8.1<span class="_ _a"> </span>Clock security sy<span class="_ _1"></span>stem on HSE <span class="_ _1"></span>. . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span><span class="ls30 ws35">. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 95</span></div><div class="t m0 x10 h7 y83 ff1 fs5 fc0 sc0 lsb ws3b">9.8.2<span class="_ _a"> </span>Clock security system on L<span class="_ _1"></span><span class="ls30 ws35">SE <span class="_ _8"> </span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 96</span></div><div class="t m0 x10 h7 ya0 ff1 fs5 fc0 sc0 ls6 wse">9.8.3<span class="_ _a"> </span>CSS on LSE control and status regi<span class="ls3d ws47">ster (CSSLSE_CSR) <span class="_ _d"> </span>. . . . . . . . . . . <span class="_ _1"></span>97</span></div><div class="t m0 x10 h7 ya1 ff1 fs5 fc0 sc0 ls3f ws4b">9.8.4<span class="_ _a"> </span>CSS<span class="_ _1"></span> on LSE regis<span class="_ _1"></span>ter map <span class="_ _1"></span>and reset v<span class="_ _1"></span>alues<span class="ls30 ws35"> <span class="_ _8"> </span> . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 98</span></div><div class="t m0 x7 hd ya2 ff1 fs8 fc0 sc0 ls2b ws2d">9.9<span class="_ _a"> </span>RTC and L<span class="_ _4"></span>CD clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>98</div><div class="t m0 x7 hd ya3 ff1 fs8 fc0 sc0 ls29 ws1">9.10<span class="_ _10"> </span>BEEP clock . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _b"> </span>99</div><div class="t m0 x7 hd ya4 ff1 fs8 fc0 sc0 ls29 ws1">9.1<span class="_ _5"></span>1<span class="_ _11"> </span>Configurable clock outpu<span class="_ _4"></span>t capability (CCO) <span class="_ _b"> </span>. . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _b"> </span>99</div><div class="t m0 x7 hd ya5 ff1 fs8 fc0 sc0 ls36 ws3e">9.12<span class="_ _10"> </span>Clock-independent system clock sources for TIM2<span class="_ _4"></span>/TIM3 . . . . . . . . . . . . . <span class="_ _b"> </span>99</div><div class="t m0 x7 hd ya6 ff1 fs8 fc0 sc0 ls36 ws3e">9.13<span class="_ _10"> </span>CLK interrupt<span class="_ _4"></span>s <span class="_ _b"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . <span class="_ _b"> </span>100</div><div class="t m0 x7 hd ya7 ff1 fs8 fc0 sc0 ls29 ws1">9.14<span class="_ _10"> </span>CLK registers . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . <span class="_ _b"> </span>100</div><div class="t m0 x10 h7 ya8 ff1 fs5 fc0 sc0 ls41 ws4e">9.14.1<span class="_ _11"> </span>System clock divider register (CLK_CK<span class="_ _1"></span>DIVR) <span class="_ _d"> </span>. . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . 100</div><div class="t m0 x10 h7 ya9 ff1 fs5 fc0 sc0 ls33 ws39">9.14.2<span class="_ _11"> </span>Clock RTC register (CLK_CRTCR) . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>100</div><div class="t m0 x10 h7 yaa ff1 fs5 fc0 sc0 ls32 ws38">9.14.3<span class="_ _11"> </span>Internal clock register (CLK_ICKCR) <span class="_ _d"> </span>. . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . 102</div><div class="t m0 x10 h7 yab ff1 fs5 fc0 sc0 lse wsc">9.14.4<span class="_ _11"> </span>Periph<span class="_ _4"></span>eral clock gating register 1 (C<span class="ls33 ws39">LK_PCKENR1) <span class="_ _12"> </span>. . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>104</span></div><div class="t m0 x10 h7 yac ff1 fs5 fc0 sc0 lse wsc">9.14.5<span class="_ _11"> </span>Periph<span class="_ _4"></span>eral clock gating register 2 (C<span class="ls33 ws39">LK_PCKENR2) <span class="_ _12"> </span>. . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>105</span></div><div class="t m0 x10 h7 yad ff1 fs5 fc0 sc0 lse wsc">9.14.6<span class="_ _11"> </span>Periph<span class="_ _4"></span>eral clock gating register 3 (C<span class="ls33 ws39">LK_PCKENR3) <span class="_ _12"> </span>. . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>106</span></div><div class="t m0 x10 h7 yae ff1 fs5 fc0 sc0 ls46 ws55">9.14.7<span class="_ _11"> </span>Configurable clock output r<span class="_ _4"></span>egister (CLK_CCOR) <span class="_ _8"> </span> . . . . . . . . . . . . . . . . <span class="_ _1"></span>107</div><div class="t m0 x10 h7 yaf ff1 fs5 fc0 sc0 ls33 ws39">9.14.8<span class="_ _11"> </span>External clock register (CLK_ECKCR) <span class="_"> </span> . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . 108</div><div class="t m0 x10 h7 yb0 ff1 fs5 fc0 sc0 ls41 ws4e">9.14.9<span class="_ _11"> </span>System clock status register (CLK_SCSR) <span class="_ _c"></span> . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . 109</div><div class="t m0 x10 h7 yb1 ff1 fs5 fc0 sc0 ls31 ws37">9.14.10<span class="_ _13"> </span>System clock switch <span class="_ _1"></span>register (CLK_SWR) <span class="_ _9"></span>. <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _9"></span>1<span class="_ _5"></span>10</div><div class="t m0 x10 h7 yb2 ff1 fs5 fc0 sc0 ls1d ws20">9.14.1<span class="_ _5"></span>1<span class="_ _14"> </span>Switch control register (CLK_SWCR) <span class="_ _f"> </span> . . <span class="_ _1"></span><span class="ls47 ws1">. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . <span class="_ _9"></span>1<span class="_ _5"></span>10</span></div><div class="t m0 x10 h7 yb3 ff1 fs5 fc0 sc0 ls3d ws47">9.14.12<span class="_ _13"> </span>Clock security system register (CLK_CSSR) <span class="_ _c"></span>. . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . <span class="_ _12"> </span>1<span class="_ _5"></span>1<span class="_ _5"></span>1</div><div class="t m0 x10 h7 yb4 ff1 fs5 fc0 sc0 lsc ws3a">9.14.13<span class="_ _13"> </span>Clock BEEP register (CLK_CBEEPR) <span class="_ _12"> </span>. . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . <span class="_ _1"></span>. . . . . <span class="_ _9"></span>1<span class="_ _3"></span>1<span class="_ _1"></span>2</div><div class="t m0 x10 h7 yb5 ff1 fs5 fc0 sc0 ls6 wse">9.14.14<span class="_ _13"> </span>HSI calibration register (CLK_HSICALR) <span class="_ _b"> </span> <span class="ls47 ws1">. . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _9"></span>1<span class="_ _5"></span>12</span></div><div class="t m0 x10 h7 yb6 ff1 fs5 fc0 sc0 ls48 ws56">9.14.15<span class="_ _13"> </span>HSI clock calibration trimming register (CLK_HSI<span class="_ _1"></span>TRIMR) <span class="_ _c"></span>. . . . . <span class="_ _1"></span>. . . . . <span class="_ _9"></span>1<span class="_ _5"></span>13</div><div class="t m0 x10 h7 yb7 ff1 fs5 fc0 sc0 ls41 ws4e">9.14.16<span class="_ _13"> </span>HSI unlock register (CLK_HSIUNLC<span class="_ _1"></span>KR) <span class="_ _8"> </span>. . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _9"></span>1<span class="_ _5"></span>13</div><div class="t m0 x10 h7 yb8 ff1 fs5 fc0 sc0 ls19 ws19">9.14.17<span class="_ _13"> </span>Main regulator control st<span class="_ _4"></span>atus register<span class="ls2c ws2e"> (CLK_REGCSR) <span class="_ _c"></span>. . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . <span class="_ _9"></span>1<span class="_ _5"></span>14</span></div><div class="t m0 x10 h7 yb9 ff1 fs5 fc0 sc0 ls6 wse">9.14.18<span class="_ _13"> </span>CLK register map and reset values <span class="_ _b"> </span>. . . . <span class="ls47 ws1">. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . <span class="_ _9"></span>1<span class="_ _5"></span>15</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div 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