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STM32H743IIT6英文数据手册,详细介绍了这款开发板
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/625ea4262cc14f66361b1997/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625ea4262cc14f66361b1997/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">This is information on a product in full prod<span class="_ _0"></span>uction. </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">May 2018<span class="_ _1"> </span>DS121<span class="_ _2"></span>10 Rev 4<span class="_ _3"> </span>1/230</div><div class="t m0 x2 h4 y3 ff2 fs2 fc0 sc0 ls2 ws2">STM32H743xI</div><div class="t m0 x3 h5 y4 ff1 fs3 fc0 sc0 ls3 ws3">32-bit Arm</div><div class="t m0 x4 h6 y5 ff1 fs4 fc0 sc0 ls4 ws2">&#174;</div><div class="t m0 x5 h5 y4 ff1 fs3 fc0 sc0 ls5 ws4"> Cortex</div><div class="t m0 x6 h6 y5 ff1 fs4 fc0 sc0 ls4 ws2">&#174;</div><div class="t m0 x7 h5 y4 ff1 fs3 fc0 sc0 ls6 ws5">-M7 400MHz MCUs, up to 2MB Flash,<span class="_ _4"></span><span class="ls4 ws2"> </span></div><div class="t m0 x8 h5 y6 ff1 fs3 fc0 sc0 ls7 ws6">1MB RAM, 46 com. and analog interfaces</div><div class="t m0 x9 h7 y7 ff2 fs1 fc0 sc0 ls8 ws2">Datasheet <span class="ff1 fs5 ls4">-</span><span class="ls9 ws7"> production data</span></div><div class="t m0 x1 h8 y8 ff2 fs6 fc0 sc0 lsa ws2">Features</div><div class="t m0 x1 h9 y9 ff2 fs7 fc0 sc0 lsb ws2">Core</div><div class="t m0 x1 ha ya ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 lsc ws8">32-bit Arm</span></div><div class="t m0 x3 hb yb ff1 fs9 fc0 sc0 ls4 ws2">&#174;</div><div class="t m0 xa ha ya ff1 fs8 fc0 sc0 lsd ws9"> Cortex</div><div class="t m0 xb hb yb ff1 fs9 fc0 sc0 ls4 ws2">&#174;</div><div class="t m0 xc ha ya ff1 fs8 fc0 sc0 lse wsa">-M7 core with double-</div><div class="t m0 xd ha yc ff1 fs8 fc0 sc0 lsf wsb">precision FPU and L1 cache: 16 <span class="_ _6"></span>Kbytes of data </div><div class="t m0 xd ha yd ff1 fs8 fc0 sc0 ls10 wsc">and 16 Kbytes of instruction cache; frequency </div><div class="t m0 xd ha ye ff1 fs8 fc0 sc0 lse wsa">up to 400 MHz, MPU, 856 DMIPS/ </div><div class="t m0 xd ha yf ff1 fs8 fc0 sc0 ls11 wsd">2.14 DMIPS/MHz (Dhrystone 2.1), and DSP </div><div class="t m0 xd ha y10 ff1 fs8 fc0 sc0 ls12 ws2">instructions</div><div class="t m0 x1 h9 y11 ff2 fs7 fc0 sc0 ls13 ws2">Memories</div><div class="t m0 x1 ha y12 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls14 wse">Up to 2 Mbytes of Flash memory with read-</span></div><div class="t m0 xd ha y13 ff1 fs8 fc0 sc0 ls15 wsf">while-write support</div><div class="t m0 x1 ha y14 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls16 ws10">1 <span class="_ _6"></span>Mbyte of RAM: 192 <span class="_ _6"></span>Kbyt<span class="ls11 ws11">es of TCM RAM (inc. </span></span></div><div class="t m0 xd ha y15 ff1 fs8 fc0 sc0 lse wsa">64 Kbytes of ITCM RAM + 128 Kbytes of </div><div class="t m0 xd ha y16 ff1 fs8 fc0 sc0 ls17 ws12">DTCM RAM for time cr<span class="ls18 ws13">itical routines), </span></div><div class="t m0 xd ha y17 ff1 fs8 fc0 sc0 ls14 wse">864 Kbytes of user SRAM, and 4 Kbytes of </div><div class="t m0 xd ha y18 ff1 fs8 fc0 sc0 lsc ws14">SRAM in Backup dom<span class="_ _0"></span>ain</div><div class="t m0 x1 ha y19 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 lse ws15">Dual mode Quad-SPI memo<span class="_ _0"></span>ry interface </span></div><div class="t m0 xd ha y1a ff1 fs8 fc0 sc0 ls19 ws16">running up to 133 MHz</div><div class="t m0 x1 ha y1b ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls14 wse">Flexible external memory contr<span class="_ _0"></span>oller with up to </span></div><div class="t m0 xd ha y1c ff1 fs8 fc0 sc0 ls17 ws12">32-bit data bus: SRAM, PSRAM, </div><div class="t m0 xd ha y1d ff1 fs8 fc0 sc0 ls18 ws17">SDRAM/LPSDR SDRAM, NOR/NAND Flash </div><div class="t m0 xd ha y1e ff1 fs8 fc0 sc0 lse wsa">memory clocked up to 133 MHz in </div><div class="t m0 xd ha y1f ff1 fs8 fc0 sc0 ls1a ws18">Synchronous mode </div><div class="t m0 x1 ha y20 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls15 wsf">CRC calculation unit</span></div><div class="t m0 x1 h9 y21 ff2 fs7 fc0 sc0 ls1b ws2">Security</div><div class="t m0 x1 ha y22 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 lsd ws19">ROP, PC-ROP, active tamper</span></div><div class="t m0 x1 h9 y23 ff2 fs7 fc0 sc0 ls1c ws1a">General-purpose input/outputs</div><div class="t m0 x1 ha y24 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls1d ws1b">Up to 168 I/O ports wit<span class="ls1e ws1c">h interrupt capability</span></span></div><div class="t m0 x1 h9 y25 ff2 fs7 fc0 sc0 ls1c ws1a">Reset and power management</div><div class="t m0 x1 ha y26 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls1a ws1d">3 separate power domains which ca<span class="_ _0"></span>n be </span></div><div class="t m0 xd ha y27 ff1 fs8 fc0 sc0 ls11 ws1e">independently clock-gated or <span class="_ _0"></span>switched of<span class="_ _0"></span>f: </div><div class="t m0 xd ha y28 ff1 fs8 fc0 sc0 ls1f ws1f">&#8211;<span class="_ _7"> </span>D1: high-performance capabilities</div><div class="t m0 xd ha y29 ff1 fs8 fc0 sc0 ls20 ws20">&#8211;<span class="_ _7"> </span>D2: communication periph<span class="_ _0"></span>erals and timers</div><div class="t m0 xd ha y2a ff1 fs8 fc0 sc0 lsf ws21">&#8211;<span class="_ _7"> </span>D3: reset/clock control/power man<span class="_ _0"></span>agement</div><div class="t m0 xe ha y2b ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls10 wsc">1.62 to 3.6 V application supply and I/Os</span></div><div class="t m0 xe ha y2c ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls21 ws22">POR, PDR, PVD and BOR</span></div><div class="t m0 xe ha y2d ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls22 ws23">Dedicated USB po<span class="_ _0"></span>wer embedding a 3.3<span class="_ _0"></span> V </span></div><div class="t m0 xf ha y2e ff1 fs8 fc0 sc0 ls23 ws24">internal regulator to <span class="lsf ws21">supply the internal<span class="_ _0"></span> PHYs</span></div><div class="t m0 xe ha y2f ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls14 wse">Embedded regulator (LDO) with<span class="_ _0"></span> configurable </span></div><div class="t m0 xf ha y30 ff1 fs8 fc0 sc0 ls1f ws1f">scalable output to supply<span class="ls12 ws25"> the digital circuitry</span></div><div class="t m0 xe ha y31 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls24 ws26">Voltage scaling in<span class="_ _0"></span> Run and Stop mode<span class="_ _0"></span> (5 </span></div><div class="t m0 xf ha y32 ff1 fs8 fc0 sc0 ls21 ws22">configurable ranges)</div><div class="t m0 xe ha y33 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 lse wsa">Backup regulator (~0.9 V)</span></div><div class="t m0 xe ha y34 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls24 ws27">Voltage reference for analo<span class="_ _0"></span>g peripheral/V</span></div><div class="t m0 x10 hb y35 ff1 fs9 fc0 sc0 ls25 ws2">REF+</div><div class="t m0 xe ha y36 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls20 ws20">Low-power modes: Sleep<span class="_ _0"></span>, Stop, Standby and </span></div><div class="t m0 xf ha y37 ff1 fs8 fc0 sc0 ls4 ws2">V</div><div class="t m0 x11 hb y38 ff1 fs9 fc0 sc0 ls25 ws2">BAT </div><div class="t m0 x12 ha y39 ff1 fs8 fc0 sc0 lsf ws21">supporting battery charging</div><div class="t m0 xe h9 y3a ff2 fs7 fc0 sc0 ls26 ws28">Low-power consumption</div><div class="t m0 xe ha y3b ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls27 ws29">Total current consumpt<span class="_ _0"></span>ion down to 4 </span></div><div class="t m1 x13 ha y3b ff1 fs8 fc0 sc0 ls28 ws2">&#181;A</div><div class="t m0 x14 ha y3b ff1 fs8 fc0 sc0 ls4 ws2"> </div><div class="t m0 xe h9 y3c ff2 fs7 fc0 sc0 ls1b ws2a">Clock management</div><div class="t m0 xe ha y3d ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls1e ws1c">Internal oscillators: 64 MHz HSI, 48 MHz </span></div><div class="t m0 xf ha y3e ff1 fs8 fc0 sc0 lse wsa">HSI48, 4 MHz CSI, 32 kHz LSI</div><div class="t m0 xe ha y3f ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls21 ws2b">External oscillators: 4-48 MHz HSE, </span></div><div class="t m0 xf ha y40 ff1 fs8 fc0 sc0 ls29 ws2c">32.768 kHz LSE</div><div class="t m0 xe ha y41 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _5"> </span><span class="ff1 ls21 ws2b">3&#215; PLLs (1 for the system clock, 2 for kernel </span></div><div class="t m0 xf ha y42 ff1 fs8 fc0 sc0 ls21 ws22">clocks) with Fractional mode</div><div class="t m0 xe h9 y43 ff2 fs7 fc0 sc0 ls1b ws2a">Interconnect matrix</div><div class="t m0 xe ha y44 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _8"> </span><span class="ff1 ls2a ws2d">3 bus matrices (1 <span class="_ _2"></span>AXI and 2 <span class="_ _2"></span>AHB)</span></div><div class="t m0 xe ha y45 ff3 fs8 fc0 sc0 ls4 ws2">&#8226;<span class="_ _8"> </span><span class="ff1 ls17 ws12">Bridges (5&#215; <span class="_ _2"></span>AHB2-APB, 2&#215; <span class="_ _0"></span>AXI2-AHB)</span></div><div class="c x15 y46 w2 hc"><div class="t m0 x16 hd y47 ff4 fsa fc1 sc0 ls4 ws2">FBGA</div></div><div class="c xe y48 w3 he"><div class="t m0 x17 h2 y49 ff1 fs0 fc0 sc0 ls2b ws2">LQFP2<span class="_ _9"></span>08</div><div class="t m0 x18 h2 y4a ff1 fs0 fc0 sc0 ls2c ws2e">(28x28 mm)</div><div class="t m0 x17 h2 y4b ff1 fs0 fc0 sc0 ls2b ws2">LQFP1<span class="_ _9"></span>76</div><div class="t m0 x18 h2 y4c ff1 fs0 fc0 sc0 ls2c ws2e">(24x24 mm)</div><div class="t m0 x17 h2 y4d ff1 fs0 fc0 sc0 ls2b ws2">LQFP1<span class="_ _9"></span>44</div><div class="t m0 x18 h2 y4e ff1 fs0 fc0 sc0 ls2c ws2e">(20x20 mm)</div><div class="t m0 x17 h2 y4f ff1 fs0 fc0 sc0 ls2b ws2">LQFP1<span class="_ _9"></span>00</div><div class="t m0 x18 h2 y50 ff1 fs0 fc0 sc0 ls2c ws2e">(14x14 mm)</div><div class="t m0 x19 h2 y51 ff1 fs0 fc0 sc0 ls2d ws2f">UFBGA1<span class="_ _9"></span>76+25 (<span class="_ _9"></span>10x10<span class="_ _9"></span> mm)</div><div class="t m0 x1a h2 y52 ff1 fs0 fc0 sc0 ls2e ws30">UFBGA169 (7x7 mm)</div></div><div class="c x1b y53 w4 hf"><div class="t m2 x1c h10 y54 ff4 fsb fc1 sc0 ls4 ws2">FBGA</div></div><div class="c xe y48 w3 he"><div class="t m0 x1d h2 y55 ff1 fs0 fc0 sc0 ls0 ws0">TFBGA240+25 (14x14 mm)</div><div class="t m0 x1a h2 y56 ff1 fs0 fc0 sc0 ls2e ws2e">TFBGA100 (8x8 mm)</div><div class="t m0 x1e h11 y57 ff1 fsc fc0 sc0 ls2f ws2">(1)</div></div><div class="t m0 x1f h12 y1 ff5 fs0 fc2 sc0 ls30 ws2">www<span class="_ _0"></span>.st.com</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><div class="d m3"></div></div><div class="pi" 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