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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6265939c4c65f41259092c1f/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6265939c4c65f41259092c1f/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y4 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y5 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y6 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h4 y7 ff2 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h5 y8 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h5 y9 ff3 fs2 fc0 sc0 ls0 ws0"><span class="fc1 sc0"> </span></div><div class="t m0 x1 h3 ya ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h4 yb ff2 fs2 fc0 sc0 ls0 ws0">IS25WP<span class="ls1">128</span> </div><div class="t m0 x1 h4 yc ff2 fs2 fc0 sc0 ls0 ws0">IS25WP<span class="ls1">064</span> </div><div class="t m0 x1 h4 yd ff2 fs2 fc0 sc0 ls0 ws0">IS25WP<span class="ls1">032</span> </div><div class="t m0 x1 h3 ye ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 yf ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y10 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h6 y11 ff2 fs3 fc0 sc0 ls0 ws0">128/64/<span class="ls2">32<span class="ls3">Mb</span></span> </div><div class="t m0 x1 h7 y12 ff2 fs4 fc0 sc0 ls0 ws0">1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & </div><div class="t m0 x1 h7 y13 ff2 fs4 fc0 sc0 ls0 ws0">QUAD I/O QPI DTR INTERFACE </div><div class="t m0 x1 h7 y14 ff2 fs4 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h6 y15 ff2 fs3 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h8 y16 ff2 fs0 fc0 sc0 ls0 ws0">PRELIMINARY DATA SHEET </div><div class="t m0 x1 h2 y17 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y18 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y19 ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _0"> </span><span class="fs0"> </span></div></div><div class="pi" data-data='{"ctm":[1.566017,0.000000,0.000000,1.566017,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6265939c4c65f41259092c1f/bg2.jpg"><div class="t m0 x2 h8 y1a ff2 fs0 fc0 sc0 ls4 ws0"> <span class="_ _1"></span> <span class="ls0"> </span> <span class="ls0"> IS25WP128/064/032 </span></div><div class="t m0 x1 h9 y1b ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 ha y1c ff3 fs5 fc0 sc0 ls0 ws0">Integrated Silicon Solution, Inc.- www.issi.com<span class="ff2"> <span class="_ _2"> </span><span class="ls5"> </span> <span class="_ _3"> </span> <span class="ff1 fs1">2</span><span class="ls6"> </span> </span></div><div class="t m0 x1 ha y1d ff2 fs5 fc0 sc0 ls0 ws0">Rev. 0C </div><div class="t m0 x1 h3 y1e ff1 fs5 fc0 sc0 ls0 ws0">03/30/2016<span class="fs1"> </span></div><div class="t m0 x1 h3 y1f ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 hb y20 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 hb y21 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h3 y22 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h9 y23 ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h8 y24 ff2 fs0 fc0 sc0 ls0 ws0">FEATURES<span class="fs7"> </span></div><div class="t m0 x1 hb y25 ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2 ls7">Ind<span class="ls0">ustry Standard Serial Interface<span class="_ _5"></span> </span></span></span></div><div class="t m0 x3 hb y26 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>IS25WP<span class="ls8">128</span>: 128Mbit/16Mbyte<span class="ff2"> </span></span></div><div class="t m0 x3 hb y27 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>IS25WP<span class="ls8">064: 64Mbit/8Mbyte</span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y28 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>IS25WP<span class="ls8">032: 32Mbit/4Mbyte</span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y29 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span><span class="ls8">256 </span>bytes per Programmable Page<span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x3 hc y2a ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Supports standard SPI, Fast, Dua<span class="_ _5"></span>l, Dual </span></div><div class="t m0 x4 hc y2b ff1 fs6 fc0 sc0 ls0 ws0">I/O, Quad, Quad I/O, SPI DTR, Dual I/O </div><div class="t m0 x4 hb y2c ff1 fs6 fc0 sc0 ls0 ws0">DTR, Quad I/O DTR, and QPI<span class="_ _5"></span><span class="ff2"> </span></div><div class="t m0 x3 hc y2d ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Supports Serial Flash <span class="_ _5"></span>Discoverable </span></div><div class="t m0 x4 hb y2e ff1 fs6 fc0 sc0 ls0 ws0">Parameters (SFDP)<span class="ff2"> </span></div><div class="t m0 x4 hb y2f ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 hb y30 ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2">High Performance Serial Flash (SPI)<span class="_ _5"></span> </span></span></div><div class="t m0 x3 hb y31 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>50MHz Normal and 133Mhz Fast Read <span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y32 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>532 MHz equivalent QPI<span class="ff2"> </span></span></div><div class="t m0 x3 hb y33 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>DTR (Dual Transfer Rate) up to 6<span class="_ _5"></span>6MHz<span class="ff2"> </span></span></div><div class="t m0 x3 hc y34 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Selectable Dummy Cycles </span></div><div class="t m0 x3 hb y35 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Configurable Drive Strength<span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y36 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Supports SPI Modes 0 and 3<span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y37 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>More than <span class="ls8">100,000 Erase/Program Cycles</span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y38 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>More than 20-year Data Reten<span class="_ _5"></span>tion<span class="ff2"> </span></span></div><div class="t m0 x4 hb y39 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 hb y3a ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2 ls9">Flexible & Efficient Memory Architecture<span class="ls0"> </span></span></span></div><div class="t m0 x3 hc y3b ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Chip Erase with Uniform: Sec<span class="_ _5"></span>tor/Bloc<span class="lsa">k </span></span></div><div class="t m0 x4 hc y3c ff1 fs6 fc0 sc0 lsb ws0">Era<span class="ls0">se (4/32/64 K<span class="_ _5"></span>byte) </span></div><div class="t m0 x3 hc y3d ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Program 1 to 256 Bytes per Pag<span class="_ _5"></span>e </span></div><div class="t m0 x3 hc y3e ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Program/Erase Suspend <span class="_ _5"></span>& Resume </span></div><div class="t m0 x4 hc y3f ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 hb y40 ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2">Efficient Read and Program <span class="lsc">modes</span> </span></span></div><div class="t m0 x3 hb y41 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Low Instruction Overhead Operations<span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x3 hc y42 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Continuous Read 8/16/32/6<span class="_ _5"></span>4-Byte Burst </span></div><div class="t m0 x4 hb y43 ff1 fs6 fc0 sc0 ls0 ws0">Wrap<span class="ff2"> </span></div><div class="t m0 x3 hb y44 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Selectable Burst Length<span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x3 hb y45 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>QPI for Reduc<span class="_ _5"></span>ed Instruction Overhea<span class="_ _5"></span>d<span class="ff2"> </span></span></div><div class="t m0 x3 hb y46 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>AutoBoot Operation<span class="ff2"> </span></span></div><div class="t m0 x5 hb y25 ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2">Low Power with Wide Temp. Range<span class="_ _5"></span>s </span></span></div><div class="t m0 x6 hc y47 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Single 1.65V <span class="ls7">to <span class="ls8">1.95V</span></span> Voltage Supply </span></div><div class="t m0 x6 hc y48 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>10 mA Active Read Current<span class="_ _5"></span> </span></div><div class="t m0 x6 hc y49 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>8 µA Standby Current </span></div><div class="t m0 x6 hc y4a ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>1 µA Deep Power Down </span></div><div class="t m0 x6 hc y4b ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Temp Grades: </span></div><div class="t m0 x7 hc y4c ff1 fs6 fc0 sc0 ls0 ws0">Extended: -40°C to +105°C<span class="_ _5"></span> </div><div class="t m0 x7 hc y4d ff1 fs6 fc0 sc0 ls0 ws0">Extended+<span class="ls7">: </span>-40°C to +125°C<span class="_ _5"></span> </div><div class="t m0 x7 hc y4e ff1 fs6 fc0 sc0 ls0 ws0">Auto Grade: up to +125°C </div><div class="t m0 x7 h3 y4f ff1 fs8 fc0 sc0 ls0 ws0">Note: Extended+ should not be us<span class="_ _5"></span>ed for Automotive.<span class="fs1"> </span></div><div class="t m0 x8 hb y50 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 hb y51 ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2">Advanced Security Protection<span class="_ _5"></span> </span></span></div><div class="t m0 x6 hb y52 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Software and Hardware Write <span class="_ _5"></span>Protection<span class="ff2"> </span></span></div><div class="t m0 x6 hb y53 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>Power Supply Lock Protection<span class="_ _5"></span><span class="ff2"> </span></span></div><div class="t m0 x6 hc y54 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>4x256-Byte Dedicated Security Area </span></div><div class="t m0 x8 hb y55 ff1 fs6 fc0 sc0 ls0 ws0">with OTP User-lockable Bits<span class="_ _5"></span><span class="ff2"> </span></div><div class="t m0 x6 hc y56 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span><span class="ls8">128 bit Unique ID for Each Device</span> </span></div><div class="t m0 x8 hb y57 ff1 fs6 fc0 sc0 ls0 ws0">(Call Factory)<span class="ff2"> </span></div><div class="t m0 x8 hb y58 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 hb y59 ff4 fs6 fc0 sc0 ls0 ws0"><span class="ff1"> <span class="_ _4"></span><span class="ff2 ls7">Indus<span class="ls0">try Standard Pin-out & Packages</span></span></span></div><div class="t m0 x9 hd y5a ff2 fs9 fc0 sc0 lsd ws0">(1)</div><div class="t m0 xa hb y59 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x6 hb y5b ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>M =<span class="ls8">16</span>-pin SOIC 300mil<span class="ff2"> </span></span></div><div class="t m0 x6 hb y5c ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>B = 8-pin SOIC 208mil<span class="ff2"> </span></span></div><div class="t m0 x6 hb y5d ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span><span class="ls9">F = </span>8-<span class="ls8">pin </span>VSOP 208mil<span class="ff2"> </span></span></div><div class="t m0 x6 hb y5e ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>K = 8-contact WSON 6x5mm<span class="ff2"> </span></span></div><div class="t m0 x6 hb y5f ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span><span class="ls8">L = </span>8-contact WSON 8x6mm<span class="ff2"> </span></span></div><div class="t m0 x6 hb y60 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>G= 24-<span class="ls8">ball TFBGA 6x8<span class="lse">mm</span></span> 4x6<span class="ff2"> </span></span></div><div class="t m0 x6 hb y61 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span><span class="fs1">H = </span><span class="ls8">24</span>-ball TFBGA <span class="_ _5"></span>6x8mm 5<span class="_ _5"></span>x5<span class="fs1"> (Call Factor<span class="lsf">y)</span></span><span class="ff2"> </span></span></div><div class="t m0 x6 hb y62 ff5 fs6 fc0 sc0 ls0 ws0">-<span class="ff1"> <span class="_ _6"> </span>KGD (Call Factory)<span class="ff2"> </span></span></div><div class="t m0 xb hc y15 ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 he y63 ff1 fs8 fc0 sc0 ls10 ws0"> <span class="ls0">Notes: </span></div><div class="t m0 x5 he y64 ff1 fs8 fc0 sc0 ls10 ws0"> <span class="ls0">1. Call Factory for other pac<span class="_ _5"></span>kage options available </span></div><div class="t m0 x5 he y65 ff1 fs8 fc0 sc0 ls0 ws0"> </div><div class="t m0 xb hc y66 ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 h3 y67 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="c xc y68 w2 hf"><div class="t m0 xd h10 y69 ff2 fsa fc0 sc0 ls0 ws0">1<span class="_ _4"></span>2<span class="_ _7"></span>8<span class="_ _7"></span>/<span class="_ _4"></span>6<span class="_ _7"></span>4<span class="_ _4"></span>/<span class="_ _7"></span><span class="ls11">32<span class="ls12">Mb</span></span> </div><div class="t m0 xd hb y6a ff2 fs6 fc0 sc0 ls0 ws0">1.8V SERIAL FLASH MEMORY WITH 13<span class="_ _5"></span>3MHZ MULTI I/O SPI & <span class="_ _5"></span><span class="ff1"> </span></div><div class="t m0 xd hb y6b ff2 fs6 fc0 sc0 ls0 ws0">QUAD I/O QPI DTR INTERFACE <span class="_ _5"></span><span class="ff1"> </span></div><div class="t m0 xd hb y6c ff2 fs6 fc0 sc0 ls7 ws0"> <span class="_ _1"></span> <span class="ls0">PRELIMINARY INFORMATION </span></div></div></div><div class="pi" data-data='{"ctm":[1.566017,0.000000,0.000000,1.566017,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w3 h11" data-page-no="3"><div class="pc pc3 w3 h11"><img class="bi x0 y0 w4 h12" alt="" src="https://static.pudn.com/prod/directory_preview_static/6265939c4c65f41259092c1f/bg3.jpg"><div class="t m0 xe h8 y6d ff2 fs0 fc0 sc0 ls4 ws0"> <span class="_ _1"></span> <span class="ls0"> </span> <span class="ls0"> IS25WP128/064/032 </span></div><div class="t m0 xc h9 y6e ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc ha y6f ff3 fs5 fc0 sc0 ls0 ws0">Integrated Silicon Solution, Inc.- www.issi.com<span class="ff2"> <span class="_ _2"> </span><span class="ls5"> </span> <span class="_ _3"> </span> <span class="ff1 fs1">3</span><span class="ls6"> </span> </span></div><div class="t m0 xc ha y1d ff2 fs5 fc0 sc0 ls0 ws0">Rev. 0C </div><div class="t m0 xc h3 y70 ff1 fs5 fc0 sc0 ls0 ws0">03/30/2016<span class="fs1"> </span></div><div class="t m0 xc h13 y71 ff2 fs7 fc0 sc0 ls0 ws0">GENERAL DESCRIPT<span class="_ _1"></span>ION </div><div class="t m0 xc h14 y72 ff1 fs7 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h3 y73 ff1 fs1 fc0 sc0 ls0 ws0">The <span class="_ _8"> </span>IS25WP128/064/032 <span class="_"> </span>Serial <span class="_ _8"> </span>Flash <span class="_ _8"> </span>memory <span class="_ _8"> </span>offers <span class="_ _8"> </span>a <span class="_ _8"> </span>versatile <span class="_ _8"> </span>storage <span class="_"> </span>solution <span class="_ _8"> </span>with <span class="_ _8"> </span>high <span class="_ _8"> </span>flexibility <span class="_ _8"> </span>and </div><div class="t m0 xc h3 y74 ff6 fs1 fc0 sc0 ls0 ws0">performance <span class="_ _4"></span>in <span class="_ _4"></span>a <span class="_ _4"></span>simplified <span class="_ _9"> </span>pin <span class="_ _4"></span>count <span class="_ _4"></span>package. <span class="_ _9"></span>ISSI’s <span class="_ _4"></span>“Industry <span class="_ _4"></span>Stand<span class="_ _5"></span>ard <span class="_ _4"></span>Serial <span class="_ _4"></span>Interface” <span class="_ _4"></span>F<span class="ff1">lash <span class="_ _9"></span><span class="ls13">is</span> <span class="_ _4"></span>for <span class="_ _9"></span>systems </span></div><div class="t m0 xc h3 y75 ff1 fs1 fc0 sc0 ls0 ws0">that require limited sp<span class="_ _5"></span>ace, a low <span class="_ _5"></span>pin count, and low <span class="_ _5"></span>power consumption. The device <span class="_ _5"></span><span class="ls13">is</span> accessed through a <span class="_ _5"></span>4-wire </div><div class="t m0 xc h3 y76 ff1 fs1 fc0 sc0 ls0 ws0">SPI <span class="_ _a"> </span>Interface <span class="_ _a"> </span>consisting <span class="_ _a"> </span>of <span class="_ _a"> </span>a <span class="_ _a"> </span>Serial <span class="_ _a"> </span>Data <span class="_ _a"> </span>Input <span class="_ _b"> </span>(<span class="ls14">SI</span>), <span class="_ _a"> </span>Serial <span class="_ _b"> </span>Data <span class="_ _a"> </span>Output <span class="_ _a"> </span>(SO), <span class="_ _a"> </span>Serial <span class="_ _a"> </span>Clock <span class="_ _a"> </span>(SCK), <span class="_ _a"> </span>and <span class="_ _b"> </span>Chip </div><div class="t m0 xc h3 y77 ff1 fs1 fc0 sc0 ls0 ws0">Enable (CE#) pins, which can <span class="_ _1"></span>also be configured to serve as multi<span class="_ _1"></span>-I/O (see pin descriptions). </div><div class="t m0 xc h3 y78 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h3 y79 ff1 fs1 fc0 sc0 ls0 ws0">The <span class="_"> </span>device <span class="_ _b"> </span>su<span class="_ _5"></span>pports <span class="_"> </span>Dual <span class="_ _b"> </span>and <span class="_"> </span>Quad <span class="_"> </span>I/O <span class="_ _6"> </span>as <span class="_ _6"> </span>well <span class="_ _6"> </span>as <span class="_"> </span>standard<span class="ls15">, <span class="_ _6"> </span></span>Dual <span class="_ _6"> </span>Output, <span class="_ _6"> </span>and <span class="_"> </span><span class="ls16">Quad <span class="_ _b"> </span></span>Output <span class="_"> </span>SPI. <span class="_"> </span>Clock </div><div class="t m0 xc h3 y7a ff1 fs1 fc0 sc0 ls0 ws0">frequencies <span class="_ _7"></span>of <span class="_ _4"></span>up <span class="_ _4"></span>to <span class="_ _4"></span>133MHz <span class="_ _4"></span>allow <span class="_ _4"></span>for <span class="_ _7"></span>equivalent <span class="_ _4"></span>clock <span class="_ _4"></span>rates <span class="_ _7"></span>of <span class="_ _4"></span>up <span class="_ _4"></span>to <span class="_ _4"></span>532MHz <span class="_ _4"></span>(133MHz <span class="_ _4"></span>x <span class="_ _4"></span>4) <span class="_ _4"></span>which <span class="_ _4"></span>equates <span class="_ _7"></span>to </div><div class="t m0 xc h3 y7b ff1 fs1 fc0 sc0 ls0 ws0">66Mbytes/s <span class="_ _b"> </span>of <span class="_"> </span>data <span class="_ _b"> </span><span class="ls15">th</span>roughput. <span class="_ _b"> </span>The <span class="_"> </span>IS<span class="_ _1"></span>25xP <span class="_ _b"> </span>series <span class="_ _6"> </span>of <span class="_ _b"> </span>Flash <span class="_"> </span>adds <span class="_ _b"> </span>support <span class="_ _b"> </span>for <span class="_"> </span>DTR <span class="_ _b"> </span>(Double <span class="_ _6"> </span>Transfer<span class="_ _1"></span> <span class="_ _b"> </span>Ra<span class="_ _5"></span>te) </div><div class="t m0 xc h3 y7c ff1 fs1 fc0 sc0 ls0 ws0">commands <span class="_"> </span>that <span class="_ _8"> </span>transfer <span class="_"> </span>address<span class="ls17">es</span> <span class="_ _8"> </span>and <span class="_"> </span>read <span class="_ _8"> </span>dat<span class="_ _1"></span>a <span class="_"> </span>on <span class="_ _8"> </span>both <span class="_"> </span>edges <span class="_ _8"> </span>of <span class="_"> </span>the <span class="_ _8"> </span>clock. <span class="_"> </span>These <span class="_ _8"> </span>transfer <span class="_"> </span>rates <span class="_"> </span>ca<span class="_ _5"></span>n </div><div class="t m0 xc h3 y7d ff1 fs1 fc0 sc0 ls0 ws0">outperform 16-bit Parallel <span class="_ _5"></span>Flash memories <span class="_ _5"></span>allowing for efficient <span class="_ _5"></span>memory access <span class="_ _5"></span>to su<span class="_ _5"></span>pport XIP (e<span class="_ _5"></span>xecute in place) </div><div class="t m0 xc h3 y7e ff1 fs1 fc0 sc0 ls0 ws0">operation. </div><div class="t m0 xc h3 y7f ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h3 y80 ff1 fs1 fc0 sc0 ls0 ws0">The memory array is organized into programmable pa<span class="_ _1"></span>ges of 256-bytes. This family supports page program mod<span class="ls18">e </span></div><div class="t m0 xc h3 y81 ff1 fs1 fc0 sc0 ls0 ws0">where 1 <span class="_ _5"></span>to 256 <span class="_ _5"></span>bytes of data <span class="_ _5"></span>are <span class="_ _5"></span>programmed in <span class="_ _5"></span>a single <span class="_ _5"></span>command. QPI (Quad <span class="_ _5"></span>Peripheral Interface) <span class="_ _5"></span>supports 2-</div><div class="t m0 xc h3 y82 ff1 fs1 fc0 sc0 ls0 ws0">cycle <span class="_ _4"></span>instruction <span class="_ _4"></span>further <span class="_ _4"></span>reducing <span class="_ _4"></span>instruction <span class="_ _4"></span>times. <span class="_ _4"></span>Pages <span class="_ _9"></span>can <span class="_ _4"></span>be <span class="_ _4"></span>erased <span class="_ _4"></span>in <span class="_ _4"></span>groups <span class="_ _9"></span>of <span class="_ _4"></span>4Kbyte <span class="_ _4"></span>sectors, <span class="_ _4"></span>32Kbyte </div><div class="t m0 xc h3 y83 ff1 fs1 fc0 sc0 ls0 ws0">blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree </div><div class="t m0 xc h3 y84 ff1 fs1 fc0 sc0 ls0 ws0">of flexibility so that the device can be util<span class="_ _1"></span>ized for a broad variety of appli<span class="_ _1"></span>cations requiring solid data retentio<span class="_ _1"></span>n. </div><div class="t m0 xc hb y85 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc hb y86 ff2 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h13 y87 ff2 fs7 fc0 sc0 ls0 ws0">GLOSSARY </div><div class="t m0 xc h3 y88 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h15 y89 ff3 fs1 fc0 sc0 ls0 ws0">Standard <span class="ls14">SPI</span> </div><div class="t m0 xc h3 y8a ff1 fs1 fc0 sc0 ls0 ws0">In <span class="_ _7"></span>this <span class="_ _4"></span>operation, <span class="_ _7"></span>a <span class="_ _4"></span>4-wire <span class="_ _7"></span>SPI <span class="_ _7"></span>Interface <span class="_ _4"></span>is <span class="_ _7"></span>utilized, <span class="_ _4"></span>consisting <span class="_ _7"></span>of <span class="_ _7"></span>Serial <span class="_ _4"></span>Data <span class="_ _7"></span>Input <span class="_ _4"></span>(SI), <span class="_ _7"></span>Serial <span class="_ _7"></span>Data <span class="_ _4"></span>Output <span class="_ _7"></span>(SO), </div><div class="t m0 xc h3 y8b ff1 fs1 fc0 sc0 ls0 ws0">Serial <span class="_ _a"> </span>Clock <span class="_ _c"> </span>(SCK), <span class="_ _c"> </span>and <span class="_ _a"> </span>Chip <span class="_ _c"> </span>Enable <span class="_ _a"> </span>(CE#) <span class="_ _c"> </span>pins. <span class="_ _a"> </span>Instructions <span class="_ _a"> </span>are <span class="_ _c"> </span>sent <span class="_ _a"> </span>via <span class="_ _c"> </span>the <span class="_ _a"> </span>SI <span class="_ _c"> </span>pin <span class="_ _a"> </span>to <span class="_ _c"> </span>encode <span class="_ _a"> </span>instructions, </div><div class="t m0 xc h3 y8c ff1 fs1 fc0 sc0 ls0 ws0">addresses, or input data <span class="_ _5"></span>to the device <span class="_ _5"></span>on the rising <span class="_ _5"></span>edge of <span class="_ _5"></span>SCK. The SO <span class="_ _5"></span>pin is <span class="_ _5"></span>used to read data <span class="_ _5"></span>or to check <span class="_ _5"></span>the </div><div class="t m0 xc h9 y8d ff1 fs1 fc0 sc0 ls0 ws0">status of the device. This device <span class="_ _1"></span>supports SPI bus operation mod<span class="_ _1"></span>es (0,0) and (1,1).<span class="ff2"> </span></div><div class="t m0 xc h3 y8e ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h15 y8f ff3 fs1 fc0 sc0 ls0 ws0">Mutil I/O <span class="ls14">SPI</span> </div><div class="t m0 xc h3 y90 ff1 fs1 fc0 sc0 ls0 ws0">Multi-I/O <span class="_ _5"></span>operation <span class="_ _5"></span>utilizes <span class="_ _5"></span>an <span class="_ _5"></span>enhanced <span class="_ _5"></span>SPI <span class="_ _5"></span>protocol <span class="_ _7"></span>to <span class="_ _5"></span>allow <span class="_ _5"></span>the <span class="_ _5"></span>device <span class="_ _5"></span>to <span class="_ _7"></span>function <span class="_ _5"></span>with <span class="_ _5"></span>Dual <span class="_ _5"></span>Output, <span class="_ _7"></span>Dual <span class="_ _5"></span>Input </div><div class="t m0 xc h3 y91 ff1 fs1 fc0 sc0 ls0 ws0">and <span class="_ _5"></span>Output, <span class="_ _5"></span>Quad Output, <span class="_ _5"></span>and <span class="_ _5"></span>Quad <span class="_ _5"></span>Input <span class="_ _5"></span>and <span class="_ _5"></span>Output <span class="_ _5"></span>capability. <span class="_ _5"></span>Executing <span class="_ _5"></span>these <span class="_ _5"></span>instructions through <span class="_ _5"></span>SPI <span class="_ _5"></span>mode </div><div class="t m0 xc h3 y92 ff1 fs1 fc0 sc0 ls0 ws0">will achieve double or quad<span class="_ _1"></span>ruple the transfer bandwidt<span class="_ _1"></span>h for READ and PROGRAM operati<span class="_ _1"></span>ons. </div><div class="t m0 xc h3 y93 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h15 y94 ff3 fs1 fc0 sc0 ls0 ws0">Q<span class="ls14">PI</span> </div><div class="t m0 xc h3 y95 ff1 fs1 fc0 sc0 ls0 ws0">The <span class="_ _8"> </span>device <span class="_ _d"> </span>supports <span class="_ _8"> </span>Quad <span class="_ _d"> </span>Peripheral <span class="_ _8"> </span>Interface <span class="_ _8"> </span>(QPI) <span class="_ _8"> </span>operations <span class="_ _d"> </span>only <span class="_ _8"> </span>when <span class="_ _d"> </span>the <span class="_ _8"> </span>device <span class="_ _d"> </span>is <span class="_ _8"> </span>switched <span class="_ _8"> </span>from </div><div class="t m0 xc h3 y96 ff1 fs1 fc0 sc0 ls0 ws0">Standard/Dual/Quad <span class="_ _a"> </span>SPI <span class="_ _a"> </span>mode <span class="_ _b"> </span>to <span class="_ _a"> </span>QPI <span class="_ _a"> </span>mode <span class="_ _b"> </span>using <span class="_ _a"> </span>the <span class="_ _b"> </span>enter <span class="_ _a"> </span>QPI <span class="_ _a"> </span>(35h)<span class="_ _5"></span> <span class="_ _a"> </span>instruction. <span class="_ _a"> </span>The <span class="_ _b"> </span>typical <span class="_ _a"> </span>SPI <span class="_ _a"> </span>protocol </div><div class="t m0 xc h3 y97 ff1 fs1 fc0 sc0 ls0 ws0">requires <span class="_ _5"></span>that the <span class="_ _5"></span>by<span class="_ _5"></span>te-long instruction <span class="_ _5"></span>code <span class="_ _5"></span>being <span class="_ _5"></span>shifted <span class="_ _5"></span>into <span class="_ _5"></span>the <span class="_ _5"></span>device <span class="_ _5"></span>only <span class="_ _5"></span>via <span class="_ _5"></span>SI <span class="_ _5"></span>pin <span class="_ _5"></span>in <span class="_ _5"></span>eight <span class="_ _5"></span>serial <span class="_ _5"></span>clocks. <span class="_ _5"></span>The </div><div class="t m0 xc h3 y98 ff1 fs1 fc0 sc0 ls0 ws0">QPI <span class="_ _9"></span>mode <span class="_ _9"></span>utilizes <span class="_ _c"></span>all <span class="_ _9"></span>four <span class="_ _9"></span>I/O <span class="_ _9"></span>pins <span class="_ _c"></span>to <span class="_ _9"></span>input <span class="_ _9"></span>the <span class="_ _9"></span>instruction <span class="_ _c"></span>code <span class="_ _9"></span>thus <span class="_ _9"></span>requiring <span class="_ _9"></span>only <span class="_ _9"></span>two <span class="_ _c"></span>serial <span class="_ _9"></span>clocks. <span class="_ _9"></span>This <span class="_ _9"></span>can </div><div class="t m0 xc h3 y99 ff1 fs1 fc0 sc0 ls0 ws0">significantly <span class="_ _e"> </span>reduce <span class="_ _e"> </span>the <span class="_ _e"> </span>SPI <span class="_ _f"> </span>instruction <span class="_ _e"> </span>overhead <span class="_ _e"> </span>and <span class="_ _f"> </span>improve <span class="_ _e"> </span>system <span class="_ _e"> </span>performance. <span class="_ _e"> </span>Onl<span class="_ _5"></span>y <span class="_ _e"> </span>QPI <span class="_ _f"> </span>mode <span class="_ _e"> </span>or </div><div class="t m0 xc h3 y9a ff1 fs1 fc0 sc0 ls0 ws0">SPI/Dual/Quad mode can be active at an<span class="_ _1"></span>y given time. Enter QPI (35h) and Exit Q<span class="_ _1"></span>PI (F5h) instructions are used to </div><div class="t m0 xc h3 y9b ff1 fs1 fc0 sc0 ls0 ws0">switch <span class="_ _b"> </span>between <span class="_ _b"> </span>these <span class="_ _b"> </span>two <span class="_ _a"> </span>modes, <span class="_ _b"> </span>regardless <span class="_ _b"> </span>of <span class="_ _b"> </span>the <span class="_ _b"> </span>non<span class="_ _5"></span>-volatile <span class="_ _a"> </span>Quad <span class="_ _b"> </span>Enable <span class="_ _b"> </span>(QE) <span class="_ _b"> </span>bit <span class="_ _b"> </span>status <span class="_ _b"> </span>in <span class="_ _b"> </span>the <span class="_ _b"> </span>Status </div><div class="t m0 xc h3 y9c ff1 fs1 fc0 sc0 ls0 ws0">Register. Power <span class="_ _5"></span>Reset or <span class="_ _5"></span>Hardware/Software Reset <span class="_ _5"></span>will return <span class="_ _5"></span>the device <span class="_ _5"></span>into the <span class="_ _5"></span>standard SPI mode. <span class="_ _5"></span>SI <span class="_ _5"></span>and SO </div><div class="t m0 xc h3 y9d ff1 fs1 fc0 sc0 ls0 ws0">pins <span class="_ _4"></span>become <span class="_ _4"></span>bidirectional <span class="_ _4"></span>I/O0 <span class="_ _4"></span>and <span class="_ _4"></span>I/O1, <span class="_ _4"></span>and <span class="_ _4"></span>WP# <span class="_ _4"></span>and <span class="_ _9"></span>HOLD# <span class="_ _4"></span>pins <span class="_ _4"></span>become <span class="_ _4"></span>I/O2 <span class="_ _4"></span>and <span class="_ _4"></span>I/O3 <span class="_ _4"></span>respectively <span class="_ _4"></span>during </div><div class="t m0 xc h3 y9e ff1 fs1 fc0 sc0 ls0 ws0">QPI mode. </div><div class="t m0 xc h3 y9f ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h15 ya0 ff3 fs1 fc0 sc0 ls0 ws0">DTR </div><div class="t m0 xc h3 ya1 ff1 fs1 fc0 sc0 ls0 ws0">In <span class="_ _7"></span>addition <span class="_ _7"></span>to <span class="_ _4"></span>SPI <span class="_ _7"></span>and <span class="_ _7"></span>QPI <span class="_ _4"></span>features, <span class="_ _7"></span>the <span class="_ _4"></span>device <span class="_ _7"></span><span class="ls18">al</span>so <span class="_ _7"></span>supports <span class="_ _7"></span>Fas<span class="_ _5"></span>t <span class="_ _5"></span>READ <span class="_ _4"></span>DTR <span class="_ _7"></span>operation. <span class="_ _7"></span>DTR <span class="_ _4"></span>operation <span class="_ _5"></span>allows </div><div class="t m0 xc h3 ya2 ff1 fs1 fc0 sc0 ls0 ws0">high <span class="_ _4"></span>data <span class="_ _4"></span>throughput <span class="_ _4"></span>while <span class="_ _7"></span>ru<span class="_ _5"></span>nning <span class="_ _4"></span>at <span class="_ _4"></span>lower <span class="_ _4"></span>clock <span class="_ _4"></span>frequencies. <span class="_ _7"></span>Fast <span class="_ _4"></span>READ <span class="_ _4"></span>DTR <span class="_ _4"></span>operation <span class="_ _4"></span>uses <span class="_ _4"></span>both <span class="_ _4"></span>rising <span class="_ _4"></span>and </div><div class="t m0 xc h3 ya3 ff1 fs1 fc0 sc0 ls0 ws0">falling <span class="_ _4"></span>edges <span class="_ _7"></span>of <span class="_ _9"></span>the <span class="_ _4"></span>clock <span class="_ _4"></span>for <span class="_ _4"></span>address <span class="_ _4"></span>inputs, <span class="_ _4"></span>and <span class="_ _4"></span>data <span class="_ _7"></span>outputs, <span class="_ _4"></span>resulting <span class="_ _4"></span>in <span class="_ _4"></span>reducing <span class="_ _4"></span>inp<span class="_ _5"></span>ut <span class="_ _4"></span>and <span class="_ _4"></span>output <span class="_ _4"></span>cycles <span class="_ _4"></span>by </div><div class="t m0 xc h3 ya4 ff1 fs1 fc0 sc0 ls0 ws0">half. </div><div class="t m0 xc hb ya5 ff2 fs6 fc0 sc0 ls0 ws0"> <span class="_ _10"> </span><span class="ff1 fs1"> </span></div></div><div class="pi" data-data='{"ctm":[1.566017,0.000000,0.000000,1.566017,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w3 h11" data-page-no="4"><div class="pc pc4 w3 h11"><img class="bi x0 y0 w4 h12" alt="" src="https://static.pudn.com/prod/directory_preview_static/6265939c4c65f41259092c1f/bg4.jpg"><div class="t m0 xe h8 y6d ff2 fs0 fc0 sc0 ls4 ws0"> <span class="_ _1"></span> <span class="ls0"> </span> <span class="ls0"> IS25WP128/064/032 </span></div><div class="t m0 xc h9 y6e ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc ha y6f ff3 fs5 fc0 sc0 ls0 ws0">Integrated Silicon Solution, Inc.- www.issi.com<span class="ff2"> <span class="_ _2"> </span><span class="ls5"> </span> <span class="_ _3"> </span> <span class="ff1 fs1">4</span><span class="ls6"> </span> </span></div><div class="t m0 xc ha y1d ff2 fs5 fc0 sc0 ls0 ws0">Rev. 0C </div><div class="t m0 xc h3 y70 ff1 fs5 fc0 sc0 ls0 ws0">03/30/2016<span class="fs1"> </span></div><div class="t m0 xc h9 ya6 ff2 fs1 fc0 sc0 ls0 ws0">TABLE OF CONTENTS </div><div class="t m0 xc h3 ya7 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xf h3 ya8 ff1 fs1 fc0 sc0 ls0 ws0">FEATURES <span class="_ _11"></span><span class="ls15">............................................................................................................................................................<span class="ls0"> <span class="_ _12"></span>2<span class="ff5 fs6"> </span></span></span></div><div class="t m0 xf h3 ya9 ff1 fs1 fc0 sc0 ls0 ws0">GENERAL DES<span class="_ _1"></span>CRIPTION <span class="_ _1"></span><span class="ls15">....................................................................................................................................<span class="ls0"> <span class="_ _12"></span>3<span class="ff5 fs6"> </span></span></span></div><div class="t m0 xf h3 yaa ff1 fs1 fc0 sc0 ls0 ws0">TABLE OF CONTENTS <span class="_ _13"></span><span class="ls15">.........................................................................................................................................<span class="ls0"> <span class="_ _12"></span>4<span class="ff5 fs6"> </span></span></span></div><div class="t m0 xf h3 yab ff1 fs1 fc0 sc0 ls18 ws0">1.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">PIN CONFIGURATION <span class="_ _15"></span><span class="ls15">...................................................................................................................................<span class="ls0"> <span class="_ _12"></span>7<span class="ff5 fs6"> </span></span></span></span></div><div class="t m0 xf h3 yac ff1 fs1 fc0 sc0 ls18 ws0">2.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">PIN DESCRIPTIONS <span class="_ _13"></span><span class="ls15">......................................................................................................................................<span class="ls0"> <span class="_ _12"></span>9<span class="ff5 fs6"> </span></span></span></span></div><div class="t m0 xf h3 yad ff1 fs1 fc0 sc0 ls18 ws0">3.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">BLOCK DIAGR<span class="ls14">AM</span> <span class="_ _13"></span><span class="ls15">........................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">11<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 xf h3 yae ff1 fs1 fc0 sc0 ls18 ws0">4.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">SPI MODES DESCRIPTI<span class="_ _1"></span>ON <span class="_ _16"></span><span class="ls15">........................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">12<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 xf h3 yaf ff1 fs1 fc0 sc0 ls18 ws0">5.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">SYSTEM CONFIGURATION <span class="_ _12"></span><span class="ls15">........................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">14<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 x10 h3 yb0 ff1 fs1 fc0 sc0 ls0 ws0">5.1 BLOCK/SECTOR ADD<span class="_ _1"></span>RESSES <span class="_ _1"></span><span class="ls15">............................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">14<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 xf h3 yb1 ff1 fs1 fc0 sc0 ls18 ws0">6.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">REGISTERS <span class="_ _16"></span><span class="ls15">.................................................................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">15<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 x10 h3 yb2 ff1 fs1 fc0 sc0 ls0 ws0">6.1 STATUS REGISTER <span class="_ _16"></span><span class="ls15">..............................................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">15<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yb3 ff1 fs1 fc0 sc0 ls0 ws0">6.2 FUNCTION REGISTER <span class="_ _12"></span><span class="ls15">..........................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">18<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yb4 ff1 fs1 fc0 sc0 ls0 ws0">6.3 READ REGISTER AND EX<span class="_ _1"></span>TENDED READ REGISTER <span class="_ _17"></span><span class="ls15">.......................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">19<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yb5 ff1 fs1 fc0 sc0 ls0 ws0">6.4 AUTOBOOT REGISTER<span class="_ _1"></span> <span class="_ _16"></span><span class="ls15">........................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">22<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 xf h3 yb6 ff1 fs1 fc0 sc0 ls18 ws0">7.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">PROTECTION MODE <span class="_ _17"></span><span class="ls15">...................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">23<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 x10 h3 yb7 ff1 fs1 fc0 sc0 ls0 ws0">7.1 HARDWARE WRITE PROTE<span class="_ _1"></span>CTION <span class="_ _17"></span><span class="ls15">......................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">23<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yb8 ff1 fs1 fc0 sc0 ls18 ws0">7.<span class="ls0">2 SOFTWARE WRITE PROTE<span class="_ _1"></span>CTION <span class="_ _11"></span><span class="ls15">......................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">23<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 xf h3 yb9 ff1 fs1 fc0 sc0 ls18 ws0">8.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">DEVICE OPERATION <span class="_ _16"></span><span class="ls15">..................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">24<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 x10 h3 yba ff1 fs1 fc0 sc0 ls0 ws0">8.1 NORMAL READ OPERATION <span class="_ _1"></span>(NORD, 03h) <span class="_ _11"></span><span class="ls15">.........................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">27<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ybb ff1 fs1 fc0 sc0 ls0 ws0">8.2 FAST READ OPERATI<span class="_ _1"></span>ON (FRD, <span class="ls18">0B</span>h) <span class="_ _11"></span><span class="ls15">..................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">29<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ybc ff1 fs1 fc0 sc0 ls0 ws0">8.3 HOLD OPERATION <span class="_ _15"></span><span class="ls15">................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">31<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ybd ff1 fs1 fc0 sc0 ls0 ws0">8.4 FAST READ DUAL I/O <span class="_ _1"></span>OPERATION (FRDIO, BBh) <span class="_ _16"></span><span class="ls15">.............................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">31<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ybe ff1 fs1 fc0 sc0 ls0 ws0">8.5 <span class="_ _5"></span>F<span class="_ _5"></span>A<span class="_ _1"></span>ST <span class="_ _1"></span>READ <span class="_ _1"></span>DU<span class="_ _5"></span>AL <span class="_ _16"></span>OUT<span class="_ _5"></span>PUT OPERA<span class="_ _1"></span>T<span class="_ _5"></span>ION (FRDO, 3Bh) <span class="_ _15"></span><span class="ls15">.....................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">34<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ybf ff1 fs1 fc0 sc0 ls0 ws0">8.6 <span class="_ _5"></span>F<span class="_ _5"></span>A<span class="_ _1"></span>ST <span class="_ _1"></span>READ <span class="_ _1"></span>QUA<span class="_ _5"></span>D OUTPUT OPERA<span class="_ _1"></span>T<span class="_ _5"></span>ION (FRQO, 6Bh)<span class="ls15">....................................................................</span> <span class="_ _12"></span><span class="ls18">35<span class="ff5 fs6 ls0"> </span></span></div><div class="t m0 x10 h3 yc0 ff1 fs1 fc0 sc0 ls0 ws0">8.7 FAST READ QUAD I/O OP<span class="_ _1"></span>ERATION (FRQIO, EBh) <span class="_ _16"></span><span class="ls15">............................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">37<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc1 ff1 fs1 fc0 sc0 ls0 ws0">8.8 PAGE PROGRAM OPERATI<span class="_ _1"></span>ON (PP, 02h) <span class="_ _15"></span><span class="ls15">............................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">41<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc2 ff1 fs1 fc0 sc0 ls0 ws0">8.9 QUAD INPUT PAGE P<span class="_ _1"></span>ROGRAM OPERATION (PPQ, <span class="_ _1"></span>32h/38h) <span class="ls15">..........................................................</span> <span class="_ _15"></span><span class="ls18">43<span class="ff5 fs6 ls0"> </span></span></div><div class="t m0 x10 h3 yc3 ff1 fs1 fc0 sc0 ls0 ws0">8.10 ERASE OPERATION <span class="_ _1"></span><span class="ls15">...........................................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">44<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc4 ff1 fs1 fc0 sc0 ls0 ws0">8.11 SECTOR ERASE OPERATION (S<span class="_ _1"></span>ER, D7h/20h) <span class="_ _15"></span><span class="ls15">.................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">45<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc5 ff1 fs1 fc0 sc0 ls0 ws0">8.12 BLOCK ERASE OPE<span class="_ _1"></span>RATION (BER32K:52h, BER64K:D8h) <span class="_ _18"></span><span class="ls15">..............................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">46<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc6 ff1 fs1 fc0 sc0 ls0 ws0">8.13 CHIP ERASE OPER<span class="_ _1"></span>ATION (CER, C7h/60h) <span class="_ _11"></span><span class="ls15">.......................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">48<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc7 ff1 fs1 fc0 sc0 ls0 ws0">8.14 WRITE ENABLE OPERATION (<span class="_ _1"></span>WREN, 06h) <span class="_ _18"></span><span class="ls15">......................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">49<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc8 ff1 fs1 fc0 sc0 ls0 ws0">8.15 WRITE DISABLE OPERATI<span class="_ _1"></span>ON (WRDI, 04h) <span class="_ _15"></span><span class="ls15">.......................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">50<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yc9 ff1 fs1 fc0 sc0 ls0 ws0">8.16 READ STATUS REGI<span class="_ _1"></span>STER OPERATION (RDSR, 05h) <span class="_ _11"></span><span class="ls15">.....................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">51<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yca ff1 fs1 fc0 sc0 ls0 ws0">8.17 WRITE STATUS REGIS<span class="_ _1"></span>TER OPERATION (WRSR, <span class="_ _1"></span>01h) <span class="_ _15"></span><span class="ls15">...................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">52<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ycb ff1 fs1 fc0 sc0 ls0 ws0">8.18 READ FUNCTION REGISTE<span class="_ _1"></span>R OPERATION (RDFR, 48h) <span class="_ _12"></span><span class="ls15">................................................................<span class="ls0">. <span class="_ _12"></span><span class="ls18">53<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ycc ff1 fs1 fc0 sc0 ls0 ws0">8.19 WRITE FUNCTION REGIS<span class="_ _1"></span>TER OPERATION (WRFR, 42h<span class="_ _1"></span>)<span class="ls15">...............................................................</span> <span class="_ _15"></span><span class="ls18">54<span class="ff5 fs6 ls0"> </span></span></div><div class="t m0 x10 h3 ycd ff1 fs1 fc0 sc0 ls0 ws0">8.20 ENTER QUAD PERIPHERAL INT<span class="_ _1"></span>ERFACE (QPI) MODE OPERATI<span class="_ _1"></span>ON (QPIEN,35h<span class="ls15">; </span>QPIDI,F5h) <span class="_ _11"></span><span class="ls15">....<span class="ls0"> <span class="_ _15"></span><span class="ls18">55<span class="ff5 fs6 ls0"> </span></span></span></span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' 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<div id="pf5" class="pf w3 h11" data-page-no="5"><div class="pc pc5 w3 h11"><img class="bi x0 y0 w4 h12" alt="" src="https://static.pudn.com/prod/directory_preview_static/6265939c4c65f41259092c1f/bg5.jpg"><div class="t m0 xe h8 y6d ff2 fs0 fc0 sc0 ls4 ws0"> <span class="_ _1"></span> <span class="ls0"> </span> <span class="ls0"> IS25WP128/064/032 </span></div><div class="t m0 xc h9 y6e ff2 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc ha y6f ff3 fs5 fc0 sc0 ls0 ws0">Integrated Silicon Solution, Inc.- www.issi.com<span class="ff2"> <span class="_ _2"> </span><span class="ls5"> </span> <span class="_ _3"> </span> <span class="ff1 fs1">5</span><span class="ls6"> </span> </span></div><div class="t m0 xc ha y1d ff2 fs5 fc0 sc0 ls0 ws0">Rev. 0C </div><div class="t m0 xc h3 y70 ff1 fs5 fc0 sc0 ls0 ws0">03/30/2016<span class="fs1"> </span></div><div class="t m0 x10 h3 yce ff1 fs1 fc0 sc0 ls0 ws0">8.21 PROGRAM/ERASE SUSPEND & R<span class="_ _1"></span>ESUME <span class="_ _15"></span><span class="ls15">........................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">56<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ycf ff1 fs1 fc0 sc0 ls0 ws0">8.22 ENTER DEEP POWER DOW<span class="_ _1"></span>N (DP, B9h) <span class="_ _12"></span><span class="ls15">...........................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">58<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd0 ff1 fs1 fc0 sc0 ls0 ws0">8.23 RELEASE DEEP <span class="_ _1"></span>POWER DOWN (RDPD, ABh) <span class="_ _15"></span><span class="ls15">.................................................................................<span class="_ _5"></span><span class="ls0"> <span class="_ _15"></span><span class="ls18">59<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd1 ff1 fs1 fc0 sc0 ls0 ws0">8.24 SET READ PARAMETERS OPER<span class="_ _1"></span>ATION (SRPNV: 65h<span class="ls15">, SRPV: C0</span>h/63h) <span class="_ _11"></span><span class="ls15">........................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">60<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd2 ff1 fs1 fc0 sc0 ls0 ws0">8.25 SET EXTENDED RE<span class="_ _1"></span>AD PARAMETERS OPERATION (SER<span class="_ _1"></span>PNV: 85h, SERPV: 83h) <span class="_ _11"></span><span class="ls15">......................<span class="_ _5"></span><span class="ls0"> <span class="_ _15"></span><span class="ls18">62<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd3 ff1 fs1 fc0 sc0 ls0 ws0">8.26 READ READ PARAMETE<span class="_ _1"></span>RS OPERATION (RDRPNV, 61h)<span class="_ _1"></span> <span class="_ _13"></span><span class="ls15">..............................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">63<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 y26 ff1 fs1 fc0 sc0 ls0 ws0">8.27 READ EXTENDED REA<span class="_ _1"></span>D PARAMETERS OPERATION (RD<span class="_ _1"></span>ERPNV, 81h) <span class="_ _15"></span><span class="ls15">.......................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">64<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd4 ff1 fs1 fc0 sc0 ls0 ws0">8.28 READ PRODUCT IDENTIFI<span class="_ _1"></span>CATION (RDID, ABh) <span class="_ _11"></span><span class="ls15">..............................................................................<span class="_ _5"></span><span class="ls0"> <span class="_ _15"></span><span class="ls18">65<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd5 ff1 fs1 fc0 sc0 ls0 ws0">8.29 READ JEDEC ID OP<span class="_ _1"></span>ERATION (RDJDID, 9Fh; RDJDIDQ, A<span class="_ _1"></span>Fh) <span class="ls15">........................................................</span> <span class="_ _15"></span><span class="ls18">67<span class="ff5 fs6 ls0"> </span></span></div><div class="t m0 x10 h3 yd6 ff1 fs1 fc0 sc0 ls0 ws0">8.30 READ DEVICE MANUFAC<span class="_ _1"></span>TURER AND DEVICE I<span class="_ _1"></span>D OPERATION (RDMDID, 90h) <span class="_ _11"></span><span class="ls15">..........................<span class="ls0"> <span class="_ _15"></span><span class="ls18">68<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd7 ff1 fs1 fc0 sc0 ls0 ws0">8.31 READ UNIQUE ID N<span class="_ _1"></span>UMBER (RDUID, 4Bh) <span class="_ _18"></span><span class="ls15">........................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">69<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd8 ff1 fs1 fc0 sc0 ls0 ws0">8.32 READ SFDP OPERATION (<span class="_ _1"></span>RDSFDP, 5Ah) <span class="_ _18"></span><span class="ls15">........................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">70<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yd9 ff1 fs1 fc0 sc0 ls0 ws0">8.33 NO OPERATION (NO<span class="_ _1"></span>P, 00h) <span class="_ _11"></span><span class="ls15">...............................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">70<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yda ff1 fs1 fc0 sc0 ls0 ws0">8.34 SOFTWARE RESET (RESE<span class="_ _1"></span>T-ENABLE (RSTEN, 66h) AN<span class="_ _1"></span>D RESET (RST, 99h)) AND H<span class="_ _1"></span>ARDWARE </div><div class="t m0 x10 h3 ydb ff1 fs1 fc0 sc0 ls0 ws0">RESET <span class="_ _11"></span><span class="ls15">..........................................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">71<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ydc ff1 fs1 fc0 sc0 ls0 ws0">8.35 SECURITY INFORMATI<span class="_ _1"></span>ON ROW <span class="_ _17"></span><span class="ls15">........................................................................................................<span class="_ _5"></span><span class="ls0"> <span class="_ _15"></span><span class="ls18">72<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ydd ff1 fs1 fc0 sc0 ls0 ws0">8.36 INFORMATION ROW ERAS<span class="_ _1"></span>E OPERATION (IRER, 64h)<span class="_ _1"></span> <span class="_ _11"></span><span class="ls15">................................................................<span class="_ _5"></span>...<span class="ls0"> <span class="_ _15"></span><span class="ls18">73<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yde ff1 fs1 fc0 sc0 ls0 ws0">8.37 INFORMATION ROW PRO<span class="_ _1"></span>GRAM OPERATION (IRP, <span class="_ _1"></span>62h) <span class="_ _16"></span><span class="ls15">...............................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">74<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ydf ff1 fs1 fc0 sc0 ls0 ws0">8.38 INFORMATION ROW READ <span class="_ _1"></span>OPERATION (IRRD, 68h)<span class="_ _1"></span> <span class="_ _18"></span><span class="ls15">.....................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">75<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye0 ff1 fs1 fc0 sc0 ls0 ws0">8.39 FAST READ DTR MODE OPE<span class="_ _1"></span>RATION (FRDTR, 0Dh) <span class="_ _15"></span><span class="ls15">.......................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">76<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye1 ff1 fs1 fc0 sc0 ls0 ws0">8.40 FAST READ DUAL I<span class="_ _1"></span>O DTR MODE OPERATION (FRDDTR, B<span class="_ _1"></span>Dh) <span class="_ _18"></span><span class="ls15">....................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">78<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye2 ff1 fs1 fc0 sc0 ls0 ws0">8.41 FAST READ QUAD IO <span class="_ _1"></span>DTR MODE OPERATION (FRQDT<span class="_ _1"></span>R, EDh) <span class="_ _18"></span><span class="ls15">...................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">81<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye3 ff1 fs1 fc0 sc0 ls0 ws0">8.42 SECTOR LOCK/UNLOCK FU<span class="_ _1"></span>NCTIONS <span class="_ _12"></span><span class="ls15">................................<span class="_ _5"></span>..............................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">85<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye4 ff1 fs1 fc0 sc0 ls0 ws0">8.43 AUTOBOOT <span class="_ _15"></span><span class="ls15">..........................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">87<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 xf h3 ye5 ff1 fs1 fc0 sc0 ls18 ws0">9.<span class="ff5 fs6 ls0"> <span class="_ _14"> </span></span><span class="ls0">ELECTRICAL CHARACTERIS<span class="_ _1"></span>TICS <span class="_ _15"></span><span class="ls15">.............................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">91<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 x10 h3 ye6 ff1 fs1 fc0 sc0 ls0 ws0">9.1 ABSOLUTE MAXIM<span class="_ _1"></span>UM RATINGS </div><div class="t m0 x11 h16 ye7 ff1 fsb fc0 sc0 ls0 ws0">(1)</div><div class="t m0 x12 h3 ye6 ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _16"></span><span class="ls15">.....................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">91<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye8 ff1 fs1 fc0 sc0 ls0 ws0">9.2 OPERATING RANGE <span class="_ _12"></span><span class="ls15">.............................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">91<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 ye9 ff1 fs1 fc0 sc0 ls0 ws0">9.3 DC CHARACTERISTICS <span class="_ _15"></span><span class="ls15">........................................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">92<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yea ff1 fs1 fc0 sc0 ls0 ws0">9.4 AC MEASUREMENT CONDITI<span class="_ _1"></span>ONS <span class="_ _11"></span><span class="ls15">......................................................................................................<span class="_ _5"></span><span class="ls0"> <span class="_ _15"></span><span class="ls18">93<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yeb ff1 fs1 fc0 sc0 ls0 ws0">9.5 PIN CAPACITANCE (TA <span class="_ _1"></span>= 25°C, VCC=3V, 1MHz) <span class="_ _16"></span><span class="ls15">...............................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">93<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yec ff1 fs1 fc0 sc0 ls0 ws0">9.6 AC CHARACTERISTICS <span class="_ _12"></span><span class="ls15">........................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">94<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yed ff1 fs1 fc0 sc0 ls0 ws0">9.7 SERIAL INPUT/OUTPUT TIM<span class="_ _1"></span>ING <span class="_ _12"></span><span class="ls15">..........................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">96<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yee ff1 fs1 fc0 sc0 ls0 ws0">9.8 POWER-UP AND POWER-DOW<span class="_ _1"></span>N <span class="_ _18"></span><span class="ls15">........................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">98<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yef ff1 fs1 fc0 sc0 ls0 ws0">9.9 PROGRAM/ERASE <span class="_ _1"></span>PERFORMANCE <span class="_ _13"></span><span class="ls15">...................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">99<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yf0 ff1 fs1 fc0 sc0 ls18 ws0">9.<span class="ls0">10 RELIABILITY CHARACTERISTI<span class="_ _1"></span>CS <span class="_ _16"></span><span class="ls15">.....................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls18">99<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 xf h3 yf1 ff1 fs1 fc0 sc0 ls18 ws0">10.<span class="ff5 fs6 ls0"> <span class="_ _19"> </span></span><span class="ls0">PACKAGE TYPE INFORMAT<span class="_ _1"></span>ION <span class="_ _15"></span><span class="ls15">.........................................................................................................<span class="_ _5"></span><span class="ls0"> <span class="_ _15"></span><span class="ls18">100<span class="ff5 fs6 ls0"> </span></span></span></span></span></div><div class="t m0 x10 h3 yf2 ff1 fs1 fc0 sc0 ls0 ws0">10.1 8-Pin JEDEC 208mil Broad Small <span class="_ _1"></span>Outline Integrated Circuit (SOI<span class="_ _1"></span>C) Package (B) <span class="_ _11"></span><span class="ls15">............................<span class="ls0"> <span class="_ _15"></span><span class="ls18">10<span class="ls0">0<span class="ff5 fs6"> </span></span></span></span></span></div><div class="t m0 x10 h3 yf3 ff1 fs1 fc0 sc0 ls0 ws0">10.2 8-Contact Ultra-Thin Small Outline<span class="_ _1"></span> No-Lead (WSON) Package 6x<span class="_ _1"></span>5mm (K) <span class="ls15">.....................................</span> <span class="_ _15"></span><span class="ls18">101<span class="ff5 fs6 ls0"> </span></span></div><div class="t m0 x10 h3 yf4 ff1 fs1 fc0 sc0 ls0 ws0">10.3 8-Contact Ultra-Thin Small Outline<span class="_ _1"></span> No-Lead (WSON) Package 8x6mm <span class="_ _1"></span>(L) <span class="_ _13"></span><span class="ls15">......................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">102<span class="ff5 fs6 ls0"> </span></span></span></span></div><div class="t m0 x10 h3 yf5 ff1 fs1 fc0 sc0 ls0 ws0">10.4 8-Pin 208mil VSOP Pac<span class="_ _1"></span>kage (F) <span class="_ _18"></span><span class="ls15">........................................................................................................<span class="ls0"> <span class="_ _15"></span><span class="ls18">103<span class="ff5 fs6 ls0"> </span></span></span></span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div 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