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<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62508d496caf596192095040/bg3.jpg"><div class="t m0 x1 h2 y1 ff2 fs0 fc0 sc0 ls0 ws0">These materials are © 20<span class="_ _0"></span>17 J<span class="_ _1"></span>ohn W<span class="_ _0"></span>iley & Sons, Inc.<span class="_ _1"></span> <span class="_ _1"></span>Any dissemination, distribution, or unauthorized use is strictly pr<span class="_ _1"></span>ohibited.</div><div class="t m0 x2 h3 y2 ff3 fs1 fc1 sc0 ls1 ws1">FPGAs</div><div class="t m0 x3 h4 y3 ff3 fs2 fc2 sc0 ls0 ws0">2nd Intel</div><div class="t m0 x4 h4 y4 ff3 fs2 fc2 sc0 ls0 ws0">®</div><div class="t m0 x5 h4 y3 ff3 fs2 fc2 sc0 ls0 ws0"> Spec<span class="_ _2"></span>ial Edition</div><div class="t m0 x6 h5 y5 ff4 fs2 fc2 sc0 ls2 ws0">by Andr<span class="_ _2"></span>ew Moor<span class="_ _3"></span>e</div><div class="t m0 x7 h6 y6 ff4 fs3 fc2 sc0 ls0 ws0">with Ron Wilson, Editor<span class="_ _3"></span>-in-Chief, </div><div class="t m0 x8 h6 y7 ff4 fs3 fc2 sc0 ls0 ws0">Intel</div><div class="t m0 x9 h7 y8 ff4 fs4 fc2 sc0 ls0 ws0">®</div><div class="t m0 xa h6 y9 ff4 fs3 fc2 sc0 ls0 ws0"> Pr<span class="_ _2"></span>ogrammable </div><div class="t m0 xb h6 ya ff4 fs3 fc2 sc0 ls0 ws0">Solutions Gr<span class="_ _2"></span>oup</div></div><div class="pi" data-data='{"ctm":[2.217320,0.000000,0.000000,2.217320,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62508d496caf596192095040/bg4.jpg"><div class="t m0 x1 h2 y1 ff2 fs0 fc0 sc0 ls0 ws0">These materials are © 20<span class="_ _0"></span>17 J<span class="_ _1"></span>ohn W<span class="_ _0"></span>iley & Sons, Inc.<span class="_ _1"></span> <span class="_ _1"></span>Any dissemination, distribution, or unauthorized use is strictly pr<span class="_ _1"></span>ohibited.</div><div class="t m0 xc h8 yb ff4 fs5 fc2 sc0 ls0 ws0">FPGAs For Dummies</div><div class="t m0 xd h9 yc ff4 fs6 fc2 sc0 ls0 ws0">®</div><div class="t m0 xe h8 yb ff4 fs5 fc2 sc0 ls0 ws0">, 2nd Intel</div><div class="t m0 x8 h9 yc ff4 fs6 fc2 sc0 ls0 ws0">®</div><div class="t m0 xf h8 yb ff4 fs5 fc2 sc0 ls0 ws0"> Special Edition</div><div class="t m0 xc ha yd ff5 fs7 fc2 sc0 ls3 ws0">Published by<span class="ls0"> </span></div><div class="t m0 xc ha ye ff4 fs7 fc2 sc0 ls3 ws0">John Wiley & Sons, Inc.<span class="ff5 ls0"> </span></div><div class="t m0 xc ha yf ff5 fs7 fc2 sc0 ls3 ws0">111 River St.<span class="ls0"> </span></div><div class="t m0 xc ha y10 ff5 fs7 fc2 sc0 ls3 ws0">Hoboken, NJ 07030-5774<span class="ls0"> </span></div><div class="t m0 xc hb y11 ff6 fs7 fc2 sc0 ls3 ws2">www.wiley.com</div><div class="t m0 xc ha y12 ff5 fs7 fc2 sc0 ls3 ws0">Copyright © 2017 by John Wiley & Sons, Inc., Hoboken, New Jersey</div><div class="t m0 xc ha y13 ff5 fs7 fc2 sc0 ls4 ws0">No part of this publication may be reproduced, stor<span class="_ _0"></span>ed in a retrieval system or transmitted in any form </div><div class="t m0 xc ha y14 ff5 fs7 fc2 sc0 ls4 ws0">or by any means, electronic, mechanical, photocopying, r<span class="_ _1"></span>ecording, scanning or otherwise, except as </div><div class="t m0 xc ha y15 ff5 fs7 fc2 sc0 ls4 ws0">permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without the prior written </div><div class="t m0 xc ha y16 ff5 fs7 fc2 sc0 ls4 ws0">permission of the Publisher<span class="_ _0"></span>. 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62508d496caf596192095040/bg5.jpg"><div class="t m0 x1 h2 y1 ff2 fs0 fc0 sc0 ls0 ws0">These materials are © 20<span class="_ _0"></span>17 J<span class="_ _1"></span>ohn W<span class="_ _0"></span>iley & Sons, Inc.<span class="_ _1"></span> <span class="_ _1"></span>Any dissemination, distribution, or unauthorized use is strictly pr<span class="_ _1"></span>ohibited.</div><div class="t m2 x11 he y41 ff8 fs9 fc2 sc0 ls0 ws0">Table of Contents</div><div class="t m0 x12 hf y42 ff8 fs3 fc2 sc0 ls0 ws0">Introduction<span class="_ _5"> </span><span class="ls10 ws13"> ......................................<span class="_ _6"></span><span class="ls0 ws0">1</span></span></div><div class="t m0 xd h10 y43 ff9 fsa fc2 sc0 ls0 ws0">About This Book<span class="ws14"> ........................................................................<span class="_"> </span></span>1</div><div class="t m0 xd h10 y44 ff9 fsa fc2 sc0 ls0 ws0">Icons Used inThis Book<span class="ws15"> ............................................................<span class="_ _5"> </span></span>1</div><div class="t m0 xd h10 y45 ff9 fsa fc2 sc0 ls0 ws0">Beyond theBook<span class="ws16"> ........................................................................<span class="_ _5"> </span></span>2</div><div class="t m0 x12 hf y46 ff8 fs3 fc2 sc0 ls0 ws0">Chapter 1: FPGAs for Everyone<span class="ls10 ws17"> ......................<span class="_ _6"></span><span class="ls0 ws0">3</span></span></div><div class="t m0 xd h10 y47 ff9 fsa fc2 sc0 ls0 ws0">So Why Would You Need anFPGA, Anyway?<span class="ws18"> .........................<span class="_ _5"> </span></span>4</div><div class="t m0 xd h10 y48 ff9 fsa fc2 sc0 ls0 ws0">Examining anFPGA<span class="ws19"> ....................................................................<span class="_ _5"> </span></span>6</div><div class="t m0 x13 h10 y49 ff9 fsa fc2 sc0 ls0 ws0">The building blocks ofan FPGA<span class="ws1a"> .....................................<span class="_ _5"> </span></span>6</div><div class="t m0 x13 h10 y4a ff9 fsa fc2 sc0 ls0 ws0">Explaining FPGAs creatively<span class="ws1b"> ...........................................<span class="_ _5"> </span></span>8</div><div class="t m0 x13 h10 y4b ff9 fsa fc2 sc0 ls0 ws0">Building block toys<span class="ws1a"> ..........................................................<span class="_ _5"> </span></span>9</div><div class="t m0 xd h10 y4c ff9 fsa fc2 sc0 ls0 ws0">Comparing FPGAs and ASICs<span class="ws1c"> ..................................................<span class="_ _5"> </span></span>10</div><div class="t m0 x13 h10 y4d ff9 fsa fc2 sc0 ls0 ws0">Costs and flexibility<span class="ws1a"> .......................................................<span class="_ _5"> </span></span>10</div><div class="t m0 x13 h10 y4e ff9 fsa fc2 sc0 ls0 ws0">Design time risk reduction versusspeed<span class="ws1d"> ...................<span class="_ _5"> </span></span>10</div><div class="t m0 xd h10 y4f ff9 fsa fc2 sc0 ls0 ws0">FPGAs Are Surprisingly Easy toUse<span class="ws19"> ......................................<span class="_ _5"> </span></span>11</div><div class="t m0 x13 h10 y50 ff9 fsa fc2 sc0 ls0 ws0">Hard IP.............................................................................<span class="_ _5"> </span>11</div><div class="t m0 x13 h10 y51 ff9 fsa fc2 sc0 ls0 ws0">Parallel operation and order reduction<span class="ws1a"> ......................<span class="_ _5"> </span></span>12</div><div class="t m0 x12 hf y52 ff8 fs3 fc2 sc0 ls0 ws0">Chapter 2: What’s in an FPGA, Anyway?<span class="ls10 ws1e"> .............<span class="_ _6"></span><span class="ls0 ws0">13</span></span></div><div class="t m0 xd h10 y53 ff9 fsa fc2 sc0 ls0 ws0">The Basics — Programmable Fabric and I/O<span class="ws1f"> .......................<span class="_ _5"> </span></span>13</div><div class="t m0 xd h10 y54 ff9 fsa fc2 sc0 ls0 ws0">Scaling Upward<span class="ws20"> .........................................................................<span class="_ _5"> </span></span>16</div><div class="t m0 xd h10 y55 ff9 fsa fc2 sc0 ls0 ws0">Hard IP and Integrated CPUs<span class="ws18"> ..................................................<span class="_ _5"> </span></span>17</div><div class="t m0 xd h10 y56 ff9 fsa fc2 sc0 ls0 ws0">Modern Design Flow ofFPGAs<span class="ws21"> ...............................................<span class="_"> </span></span>17</div><div class="t m0 x13 h10 y57 ff9 fsa fc2 sc0 ls0 ws0">Creating a functional block diagram<span class="ws22"> ...........................<span class="_ _5"> </span></span>18</div><div class="t m0 x13 h10 y58 ff9 fsa fc2 sc0 ls0 ws0">Replacing functional blocks withexisting IP<span class="ws23"> ..............<span class="_ _5"> </span></span>20</div><div class="t m0 x13 h10 y59 ff9 fsa fc2 sc0 ls0 ws0">Coding themissing blocks <span class="ws1b"> ...........................................<span class="_ _5"> </span></span>21</div><div class="t m0 x13 h10 y5a ff9 fsa fc2 sc0 ls0 ws0">Verifying thesystem design<span class="ws24"> .........................................<span class="_ _5"> </span></span>23</div><div class="t m0 x13 h10 y5b ff9 fsa fc2 sc0 ls0 ws0">Mapping thesystem into FPGA hardware<span class="ws25"> ..................<span class="_ _5"> </span></span>23</div><div class="t m0 x13 h10 y5c ff9 fsa fc2 sc0 ls0 ws0">Trying outthe design inthe system<span class="ws23"> ............................<span class="_ _5"> </span></span>24</div><div class="t m0 x12 hf y5d ff8 fs3 fc2 sc0 ls0 ws0">Chapter 3: FPGAs as Systems<span class="_ _2"></span><span class="ls10 ws13"> ......................<span class="_ _6"></span><span class="ls0 ws0">25</span></span></div><div class="t m0 xd h10 y5e ff9 fsa fc2 sc0 ls0 ws0">FPGAs inSystem Design<span class="ws1c"> ..........................................................<span class="_ _5"> </span></span>25</div><div class="t m0 xd h10 y5f ff9 fsa fc2 sc0 ls0 ws0">Automotive Electronics Systems withFPGAs<span class="ws26"> ......................<span class="_ _5"> </span></span>27</div><div class="t m0 x13 h10 y60 ff9 fsa fc2 sc0 ls0 ws0">Drivetrain<span class="ws27"> ........................................................................<span class="_ _5"> </span></span>28</div><div class="t m0 x13 h10 y61 ff9 fsa fc2 sc0 ls0 ws0">Infotainment<span class="ws22"> ...................................................................<span class="_ _5"> </span></span>28</div><div class="t m0 x13 h10 y62 ff9 fsa fc2 sc0 ls0 ws0">Driver assistance<span class="ws1d"> ...........................................................<span class="_ _5"> </span></span>29</div><div class="t m0 x13 h10 y63 ff9 fsa fc2 sc0 ls0 ws0">Importance ofFPGAs<span class="ws1b"> .....................................................<span class="_ _5"> </span></span>29</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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