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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625d27afbe9ad24cfa7af37d/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">AXI Univ<span class="_ _0"></span>ersal Serial </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">Bus (USB) 2.0 Device </div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls2 ws2">v5.0</div><div class="t m0 x1 h3 y4 ff2 fs1 fc0 sc0 ls3 ws3">Lo<span class="_ _1"></span>g<span class="_ _1"></span>i<span class="_ _1"></span>CO<span class="_ _1"></span>R<span class="_ _1"></span>E<span class="_ _1"></span> I<span class="_ _1"></span>P<span class="_ _1"></span> P<span class="_ _1"></span>ro<span class="_ _1"></span>d<span class="_ _1"></span>u<span class="_ _1"></span>c<span class="_ _1"></span>t<span class="_ _1"></span> G<span class="_ _1"></span>u<span class="_ _1"></span>i<span class="_ _1"></span>d<span class="_ _2"></span>e</div><div class="t m0 x1 h4 y5 ff1 fs2 fc0 sc0 ls4 ws4">Vi<span class="_ _0"></span>v<span class="_ _3"></span>a<span class="_ _0"></span>d<span class="_ _3"></span>o<span class="_ _0"></span> D<span class="_ _0"></span>e<span class="_ _3"></span>s<span class="_ _0"></span>i<span class="_ _0"></span>g<span class="_ _0"></span>n<span class="_ _3"></span> S<span class="_ _0"></span>u<span class="_ _0"></span>i<span class="_ _0"></span>t<span class="_ _3"></span>e</div><div class="t m0 x1 h5 y6 ff1 fs3 fc0 sc0 ls5 ws5">PG137 Nov<span class="_ _0"></span>ember 18, 2015</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625d27afbe9ad24cfa7af37d/bg2.jpg"><div class="t m0 x2 h6 y7 ff3 fs4 fc0 sc0 ls6 ws6">AXI USB 2.0 Device v5.0<span class="_ _4"> </span><span class="ff4 fc1 ls7 ws2">www<span class="_ _3"></span>.xilinx.co<span class="_ _0"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls8">2</span></span></div><div class="t m0 x2 h7 y8 ff4 fs4 fc0 sc0 ls9 ws7">PG137 November 18, 2015</div><div class="t m0 x2 h8 y9 ff4 fs1 fc0 sc0 lsa ws8">T<span class="_ _6"></span>able of Con<span class="_ _0"></span>ten<span class="_ _0"></span>t<span class="_ _0"></span>s</div><div class="t m0 x3 h9 ya ff3 fs2 fc0 sc0 lsb ws9">IP Facts</div><div class="t m0 x3 h9 yb ff3 fs2 fc0 sc0 ls8 ws2">Chapter<span class="_"> </span>1:<span class="_ _7"> </span>Overview</div><div class="t m0 x4 h6 yc ff3 fs4 fc0 sc0 lsc wsa">Functional Description<span class="_ _1"></span>. . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . .<span class="lsd wsb"> . . <span class="_ _2"></span>. . . . . . . <span class="_ _8"> </span> 5</span></div><div class="t m0 x4 h6 yd ff3 fs4 fc0 sc0 lsc wsa">Applications<span class="_ _1"></span> . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . <span class="_ _8"> </span> 9</div><div class="t m0 x4 h6 ye ff3 fs4 fc0 sc0 lsc wsa">Unsupported Features<span class="_ _9"></span>. . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . .<span class="lsd wsb"> . . . . . <span class="_ _2"></span>. . . <span class="_ _8"> </span> 9</span></div><div class="t m0 x4 h6 yf ff3 fs4 fc0 sc0 lsc wsa">Licensing and Ordering Information<span class="_ _9"> </span>. <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _2"></span><span class="lse wsc"> . . . . <span class="_ _8"> </span> 9</span></div><div class="t m0 x3 h9 y10 ff3 fs2 fc0 sc0 lsf wsd">Chapter<span class="_"> </span>2:<span class="_ _7"> </span>Product Specification</div><div class="t m0 x4 h6 y11 ff3 fs4 fc0 sc0 ls10 wse">Standards<span class="_ _1"></span> . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>.<span class="ls11 wsf"> . . . . . . . . . . . . <span class="_ _8"> </span> 11</span></div><div class="t m0 x4 h6 y12 ff3 fs4 fc0 sc0 ls10 wse">Performance<span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . <span class="wsa">. . . . . . . . . . . <span class="_ _8"> </span> 11</span></div><div class="t m0 x4 h6 y13 ff3 fs4 fc0 sc0 ls10 wsa">Resource Utilization<span class="_ _1"></span>. . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="ls12 ws10"> . . . <span class="_ _2"></span>. . . . . . <span class="_"> </span> 13</span></div><div class="t m0 x4 h6 y14 ff3 fs4 fc0 sc0 ls10 ws10">Port Descriptions<span class="_ _2"></span> . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . .<span class="ls11 wsf"> . . . . . . . . . . <span class="_ _8"> </span> 13</span></div><div class="t m0 x4 h6 y15 ff3 fs4 fc0 sc0 lsc wsa">Register Space<span class="_ _a"> </span> . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . <span class="_ _8"> </span> 14</div><div class="t m0 x3 h9 y16 ff3 fs2 fc0 sc0 ls13 ws2">Chapter<span class="_"> </span>3:<span class="_ _7"> </span>Designin<span class="lsb ws11">g with the Core</span></div><div class="t m0 x4 h6 y17 ff3 fs4 fc0 sc0 lsc wse">Clocking. . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . .<span class="ls12"> . . . . . . . <span class="_ _2"></span>. . . . . . <span class="_"> </span> 32</span></div><div class="t m0 x4 h6 y18 ff3 fs4 fc0 sc0 lsc wsa">Reset<span class="_ _a"> </span>. . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . <span class="wse">. . . . . . . . . . . . <span class="_ _2"></span>. . <span class="_"> </span> 32</span></div><div class="t m0 x4 h6 y19 ff3 fs4 fc0 sc0 lsc wsa">Programming Sequence. . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . .<span class="ls12 ws10"> . . . . . . <span class="_ _8"> </span> 32</span></div><div class="t m0 x4 h6 y1a ff3 fs4 fc0 sc0 ls11 wsf">Protocol Description in ULPI Mode<span class="_ _2"></span>. . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . <span class="_ _2"></span><span class="lsc wsa">. . . . <span class="_ _8"> </span> 37</span></div><div class="t m0 x3 h9 y1b ff3 fs2 fc0 sc0 lsf ws12">Chapter<span class="_"> </span>4:<span class="_ _7"> </span>Design Flow Steps</div><div class="t m0 x4 h6 y1c ff3 fs4 fc0 sc0 lsc wsa">Customizing and Generating the Core<span class="_ _9"> </span> . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . .<span class="ls14 ws13"> . . <span class="_ _8"> </span> 45</span></div><div class="t m0 x4 h6 y1d ff3 fs4 fc0 sc0 ls10 wse">Output Generation. . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span><span class="wsa">. . . . . . . . . <span class="_ _8"> </span> 48</span></div><div class="t m0 x4 h6 y1e ff3 fs4 fc0 sc0 ls10 wsa">Constraining the Core<span class="_ _a"> </span> . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . .<span class="ls11 wsf"> . . . . . . . . <span class="_ _8"> </span> 48</span></div><div class="t m0 x4 h6 y1f ff3 fs4 fc0 sc0 lsc wsa">Simulation<span class="_ _8"> </span> . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . <span class="_ _8"> </span> 50</div><div class="t m0 x4 h6 y20 ff3 fs4 fc0 sc0 lsc wsa">Synthesis and Implementation<span class="_ _a"> </span>. <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. .<span class="lsd wsb"> . . . . <span class="_ _8"> </span> 50</span></div><div class="t m0 x3 h9 y21 ff3 fs2 fc0 sc0 ls15 ws14">Chapter<span class="_"> </span>5:<span class="_ _7"> </span>Example Design</div><div class="t m0 x4 h6 y22 ff3 fs4 fc0 sc0 ls10 wsa">Implementing the Example Design<span class="_ _9"></span>. . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span> 53</div><div class="t m0 x4 h6 y23 ff3 fs4 fc0 sc0 ls10 wse">Simulating the Example Design<span class="_ _2"></span>. . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . <span class="wsa">. . . . . <span class="_ _8"> </span> 54</span></div><div class="c x5 y24 w2 ha"><div class="t m1 x6 hb y25 ff5 fs5 fc2 sc0 ls8 ws2"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625d27afbe9ad24cfa7af37d/bg3.jpg"><div class="t m0 x2 h6 y7 ff3 fs4 fc0 sc0 ls6 ws6">AXI USB 2.0 Device v5.0<span class="_ _4"> </span><span class="ff4 fc1 ls7 ws2">www<span class="_ _3"></span>.xilinx.co<span class="_ _0"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls8">3</span></span></div><div class="t m0 x2 h7 y8 ff4 fs4 fc0 sc0 ls9 ws7">PG137 November 18, 2015</div><div class="t m0 x3 h9 y26 ff3 fs2 fc0 sc0 ls16 ws15">Chapter<span class="_"> </span>6:<span class="_ _7"> </span>Test Bench</div><div class="t m0 x3 h9 y27 ff3 fs2 fc0 sc0 ls17 ws16">Appendix<span class="_"> </span>A:<span class="_ _7"> </span>Migrating and Upgrading</div><div class="t m0 x4 h6 y28 ff3 fs4 fc0 sc0 lsc wsa">Migrating to the Vivado Design Suite<span class="_ _9"></span>. . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . .<span class="ls18 ws17"> . . . <span class="_ _8"> </span> 56</span></div><div class="t m0 x4 h6 y29 ff3 fs4 fc0 sc0 ls11 wsf">Upgrading in the Vivado Design Suite<span class="_"> </span> . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . <span class="lsc wsa">. . . <span class="_"> </span> 56</span></div><div class="t m0 x3 h9 y2a ff3 fs2 fc0 sc0 ls17 ws2">Appendix<span class="_"> </span>B:<span class="_ _7"> </span>Debugging</div><div class="t m0 x4 h6 y2b ff3 fs4 fc0 sc0 lsc wsa">Finding Help on Xilinx.com<span class="_ _9"> </span> <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . <span class="_ _8"> </span> 57</div><div class="t m0 x4 h6 y2c ff3 fs4 fc0 sc0 lsc wse">Debug Tools<span class="_ _9"></span> . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . .<span class="_ _2"></span><span class="ls11 wsf"> . . . . . . . . . . . <span class="_ _8"> </span> 58</span></div><div class="t m0 x4 h6 y2d ff3 fs4 fc0 sc0 ls10 wse">Hardware Debug<span class="_ _a"> </span> . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . <span class="wsa">. . . . . . . . . <span class="_ _8"> </span> 59</span></div><div class="t m0 x3 h9 y2e ff3 fs2 fc0 sc0 ls19 ws18">Appendix<span class="_"> </span>C:<span class="_ _7"> </span>Additional Reso<span class="lsb ws19">urces and Legal Notices</span></div><div class="t m0 x4 h6 y2f ff3 fs4 fc0 sc0 lsc wsa">Xilinx Resources<span class="_"> </span>. . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . .<span class="ls11 wsf"> . . . . . . . . . . <span class="_ _8"> </span> 60</span></div><div class="t m0 x4 h6 y30 ff3 fs4 fc0 sc0 lsc wsa">References<span class="_ _b"> </span> . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . <span class="_ _8"> </span> 60</div><div class="t m0 x4 h6 y31 ff3 fs4 fc0 sc0 lsc wsa">Revision History<span class="_"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . .<span class="ls11 wsf"> . . . . . . . . . . <span class="_ _8"> </span> 61</span></div><div class="t m0 x4 h6 y32 ff3 fs4 fc0 sc0 ls10 wse">Please Read: Important Legal Notices<span class="_ _b"> </span> . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _2"></span>. . . . . . . . . . <span class="wsa">. . . <span class="_ _8"> </span> 61</span></div><div class="c x5 y24 w2 ha"><div class="t m1 x6 hb y25 ff5 fs5 fc2 sc0 ls8 ws2"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625d27afbe9ad24cfa7af37d/bg4.jpg"><div class="t m0 x2 h6 y7 ff3 fs4 fc0 sc0 ls6 ws6">AXI USB 2.0 Device v5.0<span class="_ _4"> </span><span class="ff4 fc1 ls7 ws2">www<span class="_ _3"></span>.xilinx.co<span class="_ _0"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls8">4</span></span></div><div class="t m0 x2 h7 y8 ff4 fs4 fc0 sc0 ls1a ws1a">PG137 November 18, 2015<span class="_ _c"> </span>Product <span class="_ _0"></span>Specification</div><div class="t m0 x2 hc y33 ff3 fs6 fc0 sc0 ls1b ws2">Intr<span class="_ _0"></span>oduction</div><div class="t m0 x2 hd y34 ff6 fs7 fc0 sc0 ls1c ws1b">The AXI USB 2.0 Device core provides a USB </div><div class="t m0 x2 hd y35 ff6 fs7 fc0 sc0 ls1d ws1c">interface to a user design<span class="_ _2"></span>. This interface is </div><div class="t m0 x2 hd y36 ff6 fs7 fc0 sc0 ls1d ws1d">suitable for USB-centric, high-<span class="_ _0"></span>per<span class="_ _2"></span>formance </div><div class="t m0 x2 hd y37 ff6 fs7 fc0 sc0 ls1e ws1e">designs, bridges, and lega<span class="_ _2"></span>cy port replacement </div><div class="t m0 x2 hd y38 ff6 fs7 fc0 sc0 ls1d ws2">operations.</div><div class="t m0 x2 hc y39 ff3 fs6 fc0 sc0 ls1f ws2">Feat<span class="_ _2"></span>ur<span class="_ _2"></span>es</div><div class="t m0 x2 he y3a ff6 fs4 fc0 sc0 ls20 ws1f">•<span class="_ _d"> </span>AXI interface based on <span class="_ _0"></span>AXI4 specif<span class="_ _1"></span>ication.</div><div class="t m0 x2 he y3b ff6 fs4 fc0 sc0 ls21 ws20">•<span class="_ _d"> </span>Burst<span class="_ _2"></span> lengths o<span class="_ _0"></span>f 1 to 256 beats with INCR </div><div class="t m0 x7 he y3c ff6 fs4 fc0 sc0 ls21 ws20">type transfers.</div><div class="t m0 x2 he y3d ff6 fs4 fc0 sc0 ls22 ws21">•<span class="_ _d"> </span>Optional DMA mode to increase </div><div class="t m0 x7 he y3e ff6 fs4 fc0 sc0 ls23 ws22">throughput during the dat<span class="_ _0"></span>a transfers.</div><div class="t m0 x2 he y3f ff6 fs4 fc0 sc0 ls24 ws23">•<span class="_ _d"> </span>Optional feature suppor<span class="_ _2"></span>t for unaligned </div><div class="t m0 x7 he y40 ff6 fs4 fc0 sc0 ls25 ws24">transfers on the mas<span class="_ _2"></span>ter int<span class="_ _0"></span>er<span class="_ _2"></span>face.</div><div class="t m0 x2 he y41 ff6 fs4 fc0 sc0 ls26 ws25">•<span class="_ _d"> </span>Suppor<span class="_ _2"></span>ts High Speed and Full Speed USB </div><div class="t m0 x7 he y42 ff6 fs4 fc0 sc0 ls26 ws22">2.0 specif<span class="_ _1"></span>ication.</div><div class="t m0 x2 he y43 ff6 fs4 fc0 sc0 ls26 ws25">•<span class="_ _d"> </span>Suppor<span class="_ _2"></span>ts high speed, high bandwid<span class="_ _0"></span>th </div><div class="t m0 x7 he y44 ff6 fs4 fc0 sc0 ls27 ws26">isochronous transact<span class="_ _2"></span>ions.</div><div class="t m0 x2 he y45 ff6 fs4 fc0 sc0 ls28 ws27">•<span class="_ _d"> </span>Suppor<span class="_ _2"></span>ts up to eight end<span class="_ _0"></span>points, including </div><div class="t m0 x7 he y46 ff6 fs4 fc0 sc0 ls26 ws25">one control end<span class="_ _0"></span>point 0. Endpoint<span class="_ _0"></span>s 1 to 7 </div><div class="t m0 x7 he y47 ff6 fs4 fc0 sc0 ls29 ws28">can be bulk<span class="_ _2"></span>, interrupt, or isochronous. </div><div class="t m0 x7 he y48 ff6 fs4 fc0 sc0 ls2a ws29">Endpoint<span class="_ _0"></span>s are individually conf<span class="_ _2"></span>igurable.</div><div class="t m0 x2 he y49 ff6 fs4 fc0 sc0 ls26 ws25">•<span class="_ _d"> </span>T<span class="_ _0"></span>wo ping-<span class="_ _0"></span>pong buffers for each endpoint </div><div class="t m0 x7 he y4a ff6 fs4 fc0 sc0 ls26 ws22">except for endpoint 0.</div><div class="t m0 x2 he y4b ff6 fs4 fc0 sc0 ls24 ws2a">•<span class="_ _d"> </span>Optional USB error detection, updates err<span class="_ _0"></span>or </div><div class="t m0 x7 he y4c ff6 fs4 fc0 sc0 ls24 ws29">count, and generates error interrupt.</div><div class="t m0 x2 he y4d ff6 fs4 fc0 sc0 ls2b ws2b">•<span class="_ _d"> </span>Suppor<span class="_ _2"></span>ts ULPI (Universal T<span class="_ _3"></span>ransceiver </div><div class="t m0 x7 he y4e ff6 fs4 fc0 sc0 ls2c ws2c">Macrocel<span class="_ _0"></span>l Interface (UTMI) + Low Pin </div><div class="t m0 x7 he y4f ff6 fs4 fc0 sc0 ls29 ws28">Interface) to an external USB PHY<span class="_ _e"></span>.</div><div class="t m0 x2 he y50 ff6 fs4 fc0 sc0 ls25 ws13">•<span class="_ _d"> </span>Access to ULPI PHY registers an<span class="_ _2"></span>d </div><div class="t m0 x7 he y51 ff6 fs4 fc0 sc0 ls29 ws28">paramet<span class="_ _0"></span>erized ULPI PHY reset.</div><div class="t m0 x2 he y52 ff6 fs4 fc0 sc0 ls2a ws29">•<span class="_ _d"> </span>R<span class="_ _0"></span>esume and reset detection in low-power </div><div class="t m0 x7 he y53 ff6 fs4 fc0 sc0 ls28 ws2">mode.</div><div class="t m0 x2 he y54 ff6 fs4 fc0 sc0 ls28 ws2d">•<span class="_ _d"> </span>R<span class="_ _0"></span>esuming of host from low-<span class="_ _0"></span>power mode </div><div class="t m0 x7 he y55 ff6 fs4 fc0 sc0 ls2d ws2e">with remot<span class="_ _0"></span>e wake-up <span class="_ _0"></span>signaling.</div><div class="t m0 x8 hf y56 ff3 fs8 fc0 sc0 ls8 ws2f">IP F<span class="_ _0"></span>act<span class="_ _0"></span>s</div><div class="t m0 x9 h6 y57 ff3 fs4 fc0 sc0 ls2e ws30">LogiCOR<span class="_ _0"></span>E IP F<span class="_ _0"></span>acts T<span class="_ _3"></span>able</div><div class="t m0 xa h6 y58 ff3 fs4 fc0 sc0 ls2f ws31">Core Specifics</div><div class="t m0 xb h10 y59 ff6 fs9 fc0 sc0 ls30 ws2">Suppor<span class="_ _2"></span>ted </div><div class="t m0 xb h10 y5a ff6 fs9 fc0 sc0 ls31 ws32">Device F<span class="_ _0"></span>amily</div><div class="t m0 xc h11 y5b ff6 fsa fc1 sc0 ls32 ws2">(1)</div><div class="t m0 xd h10 y5c ff6 fs9 fc0 sc0 ls33 ws33">UltraScale+™ F<span class="_ _0"></span>amilie<span class="_ _0"></span>s,</div><div class="t m0 xe h10 y5d ff6 fs9 fc0 sc0 ls34 ws2">UltraScale</div><div class="t m0 xf h12 y5e ff6 fsb fc0 sc0 ls8 ws2">™<span class="fs9 ls35 ws34"> Architectur<span class="_ _0"></span>e, Zynq®-7000 All</span></div><div class="t m0 x10 h10 y5f ff6 fs9 fc0 sc0 ls35 ws34">Programmable SoC</div><div class="t m0 x11 h12 y60 ff6 fsb fc0 sc0 ls36 ws2">, <span class="fs9 ls37 ws35">V<span class="_ _2"></span>ir<span class="_ _2"></span>tex®-7, Kintex®-7,</span></div><div class="t m0 x12 h10 y61 ff6 fs9 fc0 sc0 ls38 ws2">Ar<span class="_ _2"></span>tix®-7</div><div class="t m0 xb h10 y62 ff6 fs9 fc0 sc0 ls39 ws36">Suppor<span class="_ _2"></span>ted User </div><div class="t m0 xb h10 y63 ff6 fs9 fc0 sc0 ls3a ws2">Inter<span class="_ _2"></span>faces</div><div class="t m0 x13 h10 y64 ff6 fs9 fc0 sc0 ls35 ws37">AXI4, ULPI</div><div class="t m0 xb h10 y65 ff6 fs9 fc0 sc0 ls3b ws2">Re<span class="_ _2"></span>so<span class="_ _2"></span>u<span class="_ _2"></span>rc<span class="_ _2"></span>e<span class="_ _2"></span>s<span class="_ _f"> </span><span class="fc1 ls3c ws38">P<span class="_ _0"></span>er<span class="_ _2"></span>formance and Resour<span class="_ _0"></span>ce Utilizati<span class="_ _2"></span>on</span></div><div class="t m0 x13 h10 y66 ff6 fs9 fc0 sc0 ls3d ws38"> web page</div><div class="t m0 x14 h6 y67 ff3 fs4 fc0 sc0 ls3e ws39">Provided with Cor<span class="_ _0"></span>e</div><div class="t m0 xb h10 y68 ff6 fs9 fc0 sc0 ls3f ws3a">Design F<span class="_ _2"></span>iles<span class="_ _10"> </span>E<span class="_ _0"></span>nc<span class="_ _0"></span>rypt<span class="_ _0"></span>e<span class="_ _0"></span>d <span class="_ _0"></span>R<span class="_ _0"></span>T<span class="_ _0"></span>L</div><div class="t m0 xb h10 y69 ff6 fs9 fc0 sc0 ls40 ws3b">Ex<span class="_ _2"></span>am<span class="_ _2"></span>p<span class="_ _2"></span>le<span class="_ _2"></span> De<span class="_ _2"></span>si<span class="_ _2"></span>gn<span class="_ _11"> </span>V<span class="_ _0"></span>eril<span class="_ _0"></span>og and VHDL</div><div class="t m0 xb h10 y6a ff6 fs9 fc0 sc0 ls41 ws3c">Te<span class="_ _1"></span>s<span class="_ _9"> </span>t<span class="_ _1"></span> B<span class="_ _9"></span>e<span class="_ _1"></span>n<span class="_ _1"></span>c<span class="_ _9"> </span>h<span class="_ _12"> </span>P<span class="_ _2"></span>r<span class="_ _1"></span>o<span class="_ _2"></span>v<span class="_ _1"></span>i<span class="_ _1"></span>d<span class="_ _1"></span>e<span class="_ _1"></span>d</div><div class="t m0 xb h10 y6b ff6 fs9 fc0 sc0 ls42 ws3d">Co<span class="_ _2"></span>n<span class="_ _2"></span>s<span class="_ _2"></span>tr<span class="_ _2"></span>a<span class="_ _2"></span>i<span class="_ _2"></span>nt<span class="_ _2"></span>s <span class="_ _2"></span>F<span class="_ _2"></span>i<span class="_ _2"></span>le<span class="_ _13"> </span>X<span class="_ _2"></span>ilinx Design Constr<span class="_ _2"></span>aints (XDC)</div><div class="t m0 xb h10 y6c ff6 fs9 fc0 sc0 ls43 ws2">Simulation </div><div class="t m0 xb h10 y6d ff6 fs9 fc0 sc0 ls44 ws2">Model</div><div class="t m0 x15 h10 y6e ff6 fs9 fc0 sc0 ls45 ws3e">Not Provided</div><div class="t m0 xb h10 y6f ff6 fs9 fc0 sc0 ls30 ws2">Suppor<span class="_ _2"></span>ted </div><div class="t m0 xb h10 y70 ff6 fs9 fc0 sc0 ls46 ws3f">S/W Driver</div><div class="t m0 x16 h11 y71 ff6 fsa fc1 sc0 ls32 ws2">(2)</div><div class="t m0 x17 h10 y72 ff6 fs9 fc0 sc0 ls47 ws40">S<span class="_ _0"></span>tandalone and Linux</div><div class="t m0 x18 h6 y73 ff3 fs4 fc0 sc0 ls48 ws41">T<span class="_ _3"></span>es<span class="_ _0"></span>ted De<span class="_ _0"></span>sign Flows</div><div class="t m0 x19 h11 y74 ff6 fsa fc1 sc0 ls32 ws2">(3)</div><div class="t m0 xb h10 y75 ff6 fs9 fc0 sc0 ls49 ws42">De<span class="_ _2"></span>s<span class="_ _2"></span>ig<span class="_ _2"></span>n E<span class="_ _2"></span>nt<span class="_ _2"></span>r<span class="_ _2"></span>y<span class="_ _14"> </span>V<span class="_ _2"></span>iv<span class="_ _0"></span>ado® <span class="_ _0"></span>Design <span class="_ _0"></span>Suite</div><div class="t m0 xb h10 y76 ff6 fs9 fc0 sc0 ls46 ws2">Simulation</div><div class="t m0 x1a h10 y77 ff6 fs9 fc0 sc0 ls4a ws3f">For s<span class="_ _2"></span>uppo<span class="_ _2"></span>rted<span class="_ _2"></span> simula<span class="_ _2"></span>tors, s<span class="_ _2"></span>ee the</div><div class="t m0 x1b h10 y78 ff6 fs9 fc1 sc0 ls8 ws2">X</div><div class="t m0 x1c h10 y79 ff6 fs9 fc1 sc0 ls4b ws43">ilinx Design T<span class="_ _3"></span>ool<span class="_ _2"></span>s: R<span class="_ _0"></span>elease Notes Gu<span class="_ _2"></span>ide<span class="fc0 ls8 ws2">.</span></div><div class="t m0 xb h10 y7a ff6 fs9 fc0 sc0 ls4c ws44">Syn<span class="_ _2"></span>th<span class="_ _2"></span>es<span class="_ _2"></span>is<span class="_ _15"> </span>V<span class="_ _2"></span>iv<span class="_ _0"></span>ado S<span class="_ _0"></span>ynthe<span class="_ _0"></span>sis</div><div class="t m0 x1d h6 y7b ff3 fs4 fc0 sc0 ls4d ws2">Support</div><div class="t m0 x1e h10 y7c ff6 fs9 fc0 sc0 ls4e ws45">Provided by X<span class="_ _2"></span>ilinx at the <span class="fc1 ls4f ws46">Xi<span class="_ _0"></span>l<span class="_ _0"></span>i<span class="_ _0"></span>n<span class="_ _0"></span>x S<span class="_ _0"></span>u<span class="_ _0"></span>p<span class="_ _0"></span>p<span class="_ _0"></span>o<span class="_ _0"></span>rt<span class="_ _0"></span> w<span class="_ _0"></span>e<span class="_ _0"></span>b p<span class="_ _3"></span>ag<span class="_ _0"></span>e</span></div><div class="t m0 x1f h13 y7d ff1 fsc fc0 sc0 ls50 ws2">Notes: </div><div class="t m0 x1f h10 y7e ff6 fs9 fc0 sc0 ls51 ws47">1.<span class="_ _16"> </span>For a complet<span class="_ _0"></span>e list of supported devices,<span class="_ _0"></span> see the V<span class="_ _2"></span>iv<span class="_ _0"></span>ado IP </div><div class="t m0 x20 h10 y7f ff6 fs9 fc0 sc0 ls52 ws2">cata<span class="_ _0"></span>log.</div><div class="t m0 x1f h14 y80 ff6 fsd fc0 sc0 ls53 ws2">2.<span class="_ _17"> </span><span class="fs9 ls54 ws48">S<span class="_ _0"></span>tandalone dr<span class="_ _2"></span>iver details can be found in the SDK director<span class="_ _2"></span>y<span class="_ _2"></span> </span></div><div class="t m0 x20 h15 y81 ff6 fs9 fc0 sc0 ls30 ws2">(<<span class="ff7 ls55">install_dir<span class="_ _0"></span>ectory<span class="ff6 ls56 ws49">>/doc/usengli<span class="_ _2"></span>sh/xilinx_driver<span class="_ _2"></span>s.htm). Linux </span></span></div><div class="t m0 x20 h10 y82 ff6 fs9 fc0 sc0 ls57 ws4a">OS and driver support information is available fr<span class="_ _0"></span>om </div><div class="t m0 x12 h14 y83 ff6 fsd fc0 sc0 ls58 ws2">the </div><div class="t m0 x20 h14 y84 ff6 fsd fc1 sc0 ls59 ws4b">X<span class="_ _2"></span>ilinx W<span class="_ _2"></span>iki p<span class="_ _0"></span>age</div><div class="t m0 x21 h14 y85 ff6 fsd fc0 sc0 ls8 ws2">.</div><div class="t m0 x1f h10 y86 ff6 fs9 fc0 sc0 ls5a ws4c">3.<span class="_ _16"> </span>For the sup<span class="_ _2"></span>ported ver<span class="_ _2"></span>sions of the tools, see the</div><div class="t m0 x20 h10 y87 ff6 fs9 fc1 sc0 ls8 ws2">X</div><div class="t m0 x22 h10 y88 ff6 fs9 fc1 sc0 ls5b ws4d">ilinx Design T<span class="_ _3"></span>ool<span class="_ _2"></span>s: R<span class="_ _0"></span>elease Notes Gui<span class="_ _2"></span>de<span class="fc0 ls8 ws2">.</span></div><div class="c x23 y89 w3 h16"><div class="t m3 x24 h17 y8a ff5 fse fc2 sc0 ls8 ws2"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625d27afbe9ad24cfa7af37d/bg5.jpg"><div class="t m0 x2 h6 y7 ff3 fs4 fc0 sc0 ls6 ws6">AXI USB 2.0 Device v5.0<span class="_ _4"> </span><span class="ff4 fc1 ls7 ws2">www<span class="_ _3"></span>.xilinx.co<span class="_ _0"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls8">5</span></span></div><div class="t m0 x2 h7 y8 ff4 fs4 fc0 sc0 ls9 ws7">PG137 November 18, 2015</div><div class="t m0 xd h18 y8b ff8 fs8 fc0 sc0 ls5c ws2">Chapt<span class="_ _0"></span>er<span class="_"> </span>1</div><div class="t m0 x2 h8 y8c ff4 fs1 fc0 sc0 ls5d ws2">Ov<span class="_ _0"></span>er<span class="_ _2"></span>view</div><div class="t m0 x3 he y8d ff6 fs4 fc0 sc0 ls5e ws25">The USB 2.0 protocol <span class="_ _0"></span>multiplexes many devices over a single, half<span class="_ _0"></span>-duplex, serial bus. The </div><div class="t m0 x3 he y8e ff6 fs4 fc0 sc0 ls2a ws4e">bus runs at 480 Mb/s (High Speed) or at 12 <span class="ls23 ws22">Mb/s (Full Speed) and is designed to be </span></div><div class="t m0 x3 he y8f ff6 fs4 fc0 sc0 ls29 ws4f">plug-and-play<span class="_ _3"></span>. The host always controls the bu<span class="ls2a ws50">s and sends tok<span class="_ _0"></span>ens to each device specif<span class="_ _2"></span>ying </span></div><div class="t m0 x3 he y90 ff6 fs4 fc0 sc0 ls5f ws51">the requir<span class="_ _0"></span>ed action. Each device has an address on the USB 2.0 bus and ha<span class="_ _0"></span>s one or more </div><div class="t m0 x3 he y91 ff6 fs4 fc0 sc0 ls26 ws25">endpoint<span class="_ _0"></span>s that are sources or sinks o<span class="_ _0"></span>f dat<span class="_ _0"></span>a. All devices have the sys<span class="_ _2"></span>tem contr<span class="_ _0"></span>ol endpoint </div><div class="t m0 x3 he y92 ff6 fs4 fc0 sc0 ls60 ws52">(endpo<span class="_ _0"></span>int 0).</div><div class="t m0 x3 h19 y93 ff3 fsf fc0 sc0 ls61 ws1c">Functional Description</div><div class="t m0 x3 he y94 ff6 fs4 fc0 sc0 ls28 ws27">The AXI USB 2.0 Device has eight endpoint<span class="_ _0"></span>s: one control end<span class="_ _0"></span>point (endpoint 0) and seven </div><div class="t m0 x3 he y95 ff6 fs4 fc0 sc0 ls62 ws53">user endpoint<span class="_ _0"></span>s. End<span class="_ _0"></span>point 0 has different r<span class="_ _0"></span>equirements comp<span class="_ _0"></span>ared t<span class="_ _0"></span>o the seven user </div><div class="t m0 x3 he y96 ff6 fs4 fc0 sc0 ls62 ws54">endpoint<span class="_ _0"></span>s. Endpoint 0 handles control transactio<span class="ls22 ws55">ns only<span class="_ _3"></span>, which star<span class="_ _2"></span>t with an 8-byt<span class="_ _0"></span>e setup </span></div><div class="t m0 x3 he y97 ff6 fs4 fc0 sc0 ls28 ws27">pack<span class="_ _0"></span>et and are then followed by zero or mor<span class="_ _0"></span>e data p<span class="_ _0"></span>acket<span class="_ _0"></span>s. The setup packet is always </div><div class="t m0 x3 he y98 ff6 fs4 fc0 sc0 ls63 ws56">stored in a dedi<span class="_ _0"></span>cated location in the Dual P<span class="_ _0"></span>ort Random Access Memor<span class="_ _2"></span>y (DPRAM) at an </div><div class="t m0 x3 he y99 ff6 fs4 fc0 sc0 ls2a ws4e">address o<span class="_ _0"></span>ffset of 0x80. When a setup p<span class="_ _0"></span>acket is r<span class="_ _0"></span>eceived, the SETUPPkt bit o<span class="_ _0"></span>f the <span class="fc1 ls64 ws2">Int<span class="_ _0"></span>errupt </span></div><div class="t m0 x3 he y9a ff6 fs4 fc1 sc0 ls27 ws57">S<span class="_ _0"></span>tatus R<span class="_ _0"></span>egister (I<span class="_ _2"></span>SR)<span class="fc0 ls65 ws58"> is set. Data pack<span class="_ _0"></span>ets ar<span class="_ _0"></span>e a maximum of <span class="_ _0"></span>64 bytes. These data pack<span class="_ _0"></span>ets ar<span class="_ _0"></span>e </span></div><div class="t m0 x3 he y9b ff6 fs4 fc0 sc0 ls62 ws59">stored in a single bidi<span class="_ _0"></span>rectional dat<span class="_ _0"></span>a buffer se<span class="ls2a ws5a">t up by the conf<span class="_ _1"></span>iguration memor<span class="_ _2"></span>y of End<span class="_ _0"></span>point </span></div><div class="t m0 x3 he y9c ff6 fs4 fc0 sc0 ls5e ws2d">0, located at the addr<span class="_ _0"></span>ess offset 0x0 in the DP<span class="ls2a ws4e">RAM. When a dat<span class="_ _0"></span>a pack<span class="_ _0"></span>et is transmitted or </span></div><div class="t m0 x3 he y9d ff6 fs4 fc0 sc0 ls66 ws5b">received successfully<span class="_ _0"></span>, the FIFOBufFree and FIFOBufRdy bit<span class="_ _0"></span>s of the <span class="fc1 ls26 ws5c">Interrupt St<span class="_ _0"></span>atus R<span class="_ _0"></span>egis<span class="_ _2"></span>ter </span></div><div class="t m0 x3 he y9e ff6 fs4 fc1 sc0 ls29 ws2">(ISR)<span class="fc0 ws1f"> are set r<span class="_ _0"></span>espectively<span class="_ _3"></span>.</span></div><div class="t m0 x3 he y9f ff6 fs4 fc0 sc0 ls2a ws5d">The seven user endpoint<span class="_ _0"></span>s of the AXI USB 2.0 Device can be conf<span class="_ _1"></span>igured as bulk<span class="_ _2"></span>, interrupt, or </div><div class="t m0 x3 he ya0 ff6 fs4 fc0 sc0 ls20 ws1f">isochronous. In ad<span class="_ _0"></span>dition, endpoint<span class="_ _0"></span>s can be conf<span class="_ _1"></span>igured as INPUT (t<span class="_ _0"></span>o the host) or OUTPUT </div><div class="t m0 x3 he ya1 ff6 fs4 fc0 sc0 ls2a ws29">(from the host). Each of these endpoint<span class="_ _0"></span>s has two ping-p<span class="_ _0"></span>ong buffer<span class="_ _2"></span>s o<span class="_ _0"></span>f the same size <span class="_ _2"></span>for </div><div class="t m0 x3 he ya2 ff6 fs4 fc0 sc0 ls26 ws25">endpoint dat<span class="_ _0"></span>a. The user endpoint<span class="_ _0"></span>s data buffers are unidir<span class="_ _0"></span>ectional, and are conf<span class="_ _2"></span>igu<span class="_ _2"></span>r<span class="_ _0"></span>ed by </div><div class="t m0 x3 he ya3 ff6 fs4 fc0 sc0 ls26 ws25">the Endpoint <span class="_ _0"></span>Conf<span class="_ _1"></span>iguration and St<span class="_ _0"></span>atus register of<span class="_ _0"></span> the respective endpoint. The size o<span class="_ _0"></span>f the </div><div class="t m0 x3 he ya4 ff6 fs4 fc0 sc0 ls5f ws51">buffers can be conf<span class="_ _1"></span>igured from 0 to 512 bytes for bulk<span class="_ _2"></span>, 64 bytes for interrupt, and up to </div><div class="t m0 x3 he ya5 ff6 fs4 fc0 sc0 ls5f ws51">1,024 bytes for isochronous end<span class="_ _0"></span>points.</div><div class="t m0 x3 he ya6 ff6 fs4 fc0 sc0 ls5e ws2d">The AXI USB 2.0 Device core with the AXI and ULPI interfaces is shown in <span class="fc1 ls67 ws2">Fig<span class="_ _0"></span>u<span class="_ _0"></span>r<span class="_ _0"></span>e<span class="_ _18"> </span>1<span class="_ _0"></span>-1<span class="_ _0"></span><span class="fc0 ls8">.</span></span></div><div class="c x5 y24 w2 ha"><div class="t m1 x6 hb y25 ff5 fs5 fc2 sc0 ls8 ws2"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>