PCI_Express_3_0.rar_pcie_PCI express_文章/文档下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6250f8e96caf5961923005a2/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250f8e96caf5961923005a2/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _0"> </span> </div><div class="t m0 x2 h3 y2 ff2 fs1 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y3 ff2 fs1 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y4 ff2 fs1 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y5 ff2 fs1 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y6 ff2 fs1 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y7 ff2 fs1 fc1 sc0 ls0 ws0"> </div><div class="t m0 x3 h3 y8 ff2 fs1 fc1 sc0 ls1 ws1">PCI Expr<span class="_ _1"></span>ess</div><div class="t m0 x4 h4 y9 ff2 fs2 fc1 sc0 ls0 ws0">®</div><div class="t m0 x5 h3 ya ff2 fs1 fc1 sc0 ls2 ws0"> </div><div class="t m0 x6 h3 yb ff2 fs1 fc1 sc0 ls3 ws2">Base Specifica<span class="_ _2"></span>tion </div><div class="t m0 x7 h3 yc ff2 fs1 fc1 sc0 ls4 ws3">R<span class="_ _3"></span>e<span class="_ _3"></span>vision 3.0 </div><div class="t m0 x8 h5 yd ff1 fs3 fc1 sc0 ls5 ws4">November 10, 2010 </div><div class="t m0 x9 h6 ye ff1 fs4 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h6 yf ff1 fs4 fc1 sc0 ls0 ws0"> </div><div class="t m0 xa h7 y10 ff1 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h7 y11 ff1 fs5 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h8 y12 ff3 fs5 fc1 sc0 ls0 ws0"> </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250f8e96caf5961923005a2/bg2.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _4"></span><span class="ls6">2 </span></div><div class="t m0 xb h9 y13 ff4 fs6 fc1 sc0 ls7 ws5">Revision Revision <span class="_ _5"></span>History <span class="_ _6"> </span>DATE </div><div class="t m0 xb ha y14 ff1 fs7 fc1 sc0 ls8 ws6">1.0 Initial <span class="_ _7"></span>release. <span class="_ _8"> </span><span class="ls9 ws0">07/22/2002 </span></div><div class="t m0 xb ha y15 ff1 fs7 fc1 sc0 ls9 ws7">1.0a <span class="_ _9"> </span>Incorporated Erra<span class="_ _2"></span>ta C1-C66 and E1-E4.17. <span class="_ _a"> </span>04/15/2003 </div><div class="t m0 xb ha y16 ff1 fs7 fc1 sc0 ls9 ws7">1.1 <span class="_ _b"> </span>Incorporated approv<span class="_ _2"></span>ed Errata and ECNs. <span class="_ _c"> </span>03/28/2005 </div><div class="t m0 xb ha y17 ff1 fs7 fc1 sc0 lsa ws8">2.0 <span class="_ _b"> </span>Added 5.0 GT/s data rate a<span class="_ _2"></span>nd incorpor<span class="lsb ws7">ated approved Erra<span class="_ _2"></span>ta and ECNs. <span class="_ _d"> </span>12/20/2006 </span></div><div class="t m0 xb hb y18 ff1 fs7 fc1 sc0 lsc ws9">2.1 Incorporated <span class="_ _7"></span><span class="ff5 lsd wsa">Errata for<span class="_ _2"></span> the PCI Express Ba<span class="lse wsb">se Spe<span class="_ _2"></span>cification, Rev. 2.0<span class="ff1 lsf ws0"> </span></span></span></div><div class="t m0 xc ha y19 ff1 fs7 fc1 sc0 ls10 wsc">(February 27, 2009), a<span class="_ _2"></span>nd added the following ECNs: </div><div class="t m0 xd hc y1a ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls11 wsd"> <span class="_ _e"> </span>Internal Error Reporting<span class="_ _2"></span> ECN (April 24, 2008) </span></div><div class="t m0 xd hc y1b ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 lsa ws8"> <span class="_ _e"> </span>Multicast ECN (December 14, 2<span class="_ _2"></span>007, approved by PWG May 8, 2008) </span></div><div class="t m0 xd hc y1c ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls12 wse"> <span class="_ _e"> </span>Atomic Operations ECN (January<span class="_ _2"></span> 15, 2008, approved by PWG April 17, 200<span class="_ _2"></span>8) </span></div><div class="t m0 xd hc y1d ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls12 wse"> <span class="_ _e"> </span>Resizable BAR Capability<span class="_ _2"></span> ECN (January 22, 2008, updated and approv<span class="_ _2"></span>ed by </span></div><div class="t m0 xe ha y1e ff1 fs7 fc1 sc0 ls13 wsf">PWG April 24, 2008) </div><div class="t m0 xd hc y1f ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 lsa ws8"> <span class="_ _e"> </span>Dynamic Power Allocation <span class="_ _2"></span>ECN (May 24, 2008) </span></div><div class="t m0 xd hc y20 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls12 wse"> <span class="_ _e"> </span>ID-Based Ordering ECN (Janu<span class="_ _2"></span>ary 16, 2008, updated 29 May<span class="_ _2"></span> 2008) </span></div><div class="t m0 xd hc y21 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 lsd wsa"> <span class="_ _e"> </span>Latency Tolerance <span class="_ _2"></span>Reporting ECN (22 January 2008, up<span class="_ _2"></span>dated 14 August 2008) </span></div><div class="t m0 xd hc y22 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls8 ws10"> Alternative <span class="_ _f"></span>Routing-ID <span class="_ _f"></span>Interpretation <span class="_ _f"></span><span class="ls14 ws11">(ARI) ECN (Augu<span class="_ _2"></span>st 7,<span class="ls15 ws12"> 2006, last updated </span></span></span></div><div class="t m0 xe ha y23 ff1 fs7 fc1 sc0 ls9 ws13">June 4, 2007) </div><div class="t m0 xd hc y24 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls11 wsd"> <span class="_ _e"> </span>Extended Tag Enable Defa<span class="_ _2"></span>ult ECN (September 5, 2008) </span></div><div class="t m0 xd hc y25 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls11 wsd"> <span class="_ _e"> </span>TLP Processing Hints ECN (<span class="_ _2"></span>September 11, 2008) </span></div><div class="t m0 xd hc y26 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls16 ws14"> <span class="_ _e"> </span>TLP Prefix ECN (December 15, 200<span class="_ _2"></span>8) </span></div><div class="t m0 xf ha y27 ff1 fs7 fc1 sc0 ls9 ws0">03/04/2009 </div><div class="t m0 xb ha y28 ff1 fs7 fc1 sc0 ls13 wsf">3.0 <span class="_ _b"> </span>Added 8.0 GT/s data rate, la<span class="_ _2"></span>test approved Errata, and the follow<span class="_ _2"></span>ing ECNs: </div><div class="t m0 xd hc y29 ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls16 ws14"> <span class="_ _e"> </span>Optimized Buffer Flush/Fill<span class="_ _2"></span> ECN <span class="ls0 ws15">(8 February 2008, update<span class="_ _2"></span>d 30 April 2009) </span></span></div><div class="t m0 xd hc y2a ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 lsb ws7"> <span class="_ _e"> </span>ASPM Optionality ECN (June<span class="_ _2"></span> 19, 2009, a<span class="ls15 ws12">pprov<span class="_ _2"></span>ed by the PWG August 20, 2009) </span></span></div><div class="t m0 xd hc y2b ff6 fs7 fc1 sc0 ls0 ws0">•<span class="ff1 ls12 wse"> <span class="_ _e"> </span>Incorporated End-End TLP Cha<span class="_ _2"></span>nges for RCs ECN (26 May<span class="_ _2"></span> 2010) and Protocol </span></div><div class="t m0 xe ha y2c ff1 fs7 fc1 sc0 ls17 ws16">Multiplexing ECN (17 June 2010) </div><div class="t m0 xf ha y28 ff1 fs7 fc1 sc0 ls9 ws0">11/10/2010 </div><div class="t m0 x9 hd y2d ff1 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 hd y2e ff1 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 he y2f ff3 fs4 fc1 sc0 ls18 ws0">PCI-SIG</div><div class="t m0 x10 hf y30 ff3 fs8 fc1 sc0 ls0 ws0">®</div><div class="t m0 x11 he y2f ff3 fs4 fc1 sc0 ls19 ws17"> disclaims all warranties an<span class="_ _2"></span>d liability for the use of th<span class="ls0 ws18">is document and th<span class="_ _2"></span>e information contained herein and </span></div><div class="t m0 x9 he y31 ff3 fs4 fc1 sc0 ls1a ws19">assumes no responsibility for any errors th<span class="ls1b ws1a">at may app<span class="_ _2"></span>ear in this document, nor <span class="ws1b">does PCI-SIG make a commitment to </span></span></div><div class="t m0 x9 he y32 ff3 fs4 fc1 sc0 ls1b ws1a">update the information contai<span class="_ _2"></span>ned herein. </div><div class="t m0 x9 he y33 ff3 fs4 fc1 sc0 ls1c ws1c">Contact the PCI-SIG offi<span class="_ _2"></span>ce to obtain the la<span class="ls1a ws19">test revision of this specification. </span></div><div class="t m0 x9 he y34 ff3 fs4 fc1 sc0 ls1d ws1d">Questions regarding the PCI Express Base Specifi<span class="_ _2"></span>cation <span class="ls1e ws1e">or membership in PCI-SIG may be forwa<span class="_ _2"></span>rded to: </span></div><div class="t m0 x12 he y35 ff7 fs4 fc1 sc0 ls1f ws1f">Membership Services<span class="ff3 ls0 ws0"> </span></div><div class="t m0 x12 he y36 ff3 fs4 fc1 sc0 ls19 ws0">www.pcisig.com </div><div class="t m0 x12 he y37 ff3 fs4 fc1 sc0 ls20 ws20">E-mail: <span class="_ _10"> </span>administration@pcisig.co<span class="_ _2"></span>m </div><div class="t m0 x12 he y38 ff3 fs4 fc1 sc0 ls21 ws21">Phone: <span class="_ _11"> </span>503-619-0569 </div><div class="t m0 x12 he y39 ff3 fs4 fc1 sc0 ls22 ws22">Fax: <span class="_ _12"> </span>503-644-6708 </div><div class="t m0 x12 he y3a ff3 fs4 fc1 sc0 ls0 ws0"> </div><div class="t m0 x12 he y3b ff7 fs4 fc1 sc0 ls23 ws23">Technical Support<span class="ff3 ls0 ws0"> </span></div><div class="t m0 x12 he y3c ff3 fs4 fc1 sc0 ls19 ws0">techsupp@pcisig.com </div><div class="t m0 x2 h10 y3d ff7 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h10 y3e ff7 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x13 he y3f ff7 fs4 fc1 sc0 ls1f ws0">DISCLAIMER </div><div class="t m0 x14 he y40 ff3 fs4 fc1 sc0 ls19 ws17">This PCI Express Base Specification is<span class="_ _2"></span><span class="ls24 ws24"> provided “as is” with no warranties <span class="ls25 ws25">whatsoever, including any warranty of </span></span></div><div class="t m0 x14 he y41 ff3 fs4 fc1 sc0 ls18 ws26">merchantability, noninfringement, fitness <span class="ls0 ws18">for any parti<span class="_ _2"></span>cular purpose, or any <span class="ls18 ws26">warranty otherwise arising out of an<span class="_ _2"></span>y </span></span></div><div class="t m0 x14 he y42 ff3 fs4 fc1 sc0 ls19 ws27">proposal, specification, or sample. PCI-<span class="ls1b ws1a">SIG disclaims all liability for infrin<span class="_ _2"></span>gement of proprietary rights, relating to </span></div><div class="t m0 x14 he y43 ff3 fs4 fc1 sc0 ls19 ws1a">use of information in this specification. <span class="_ _2"></span><span class="ls18 ws26"> No license, express or im<span class="ls26 ws28">plied, by estoppel or othe</span>rwise, <span class="_ _2"></span>to any intellectual </span></div><div class="t m0 x14 he y44 ff3 fs4 fc1 sc0 ls1c ws1c">property rights is granted h<span class="_ _2"></span>erein. </div><div class="t m0 x9 h10 y45 ff3 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h10 y46 ff3 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 he y47 ff3 fs4 fc1 sc0 ls27 ws29">PCI, PCI Expr<span class="_ _2"></span>ess, PCIe, and PCI-SIG are tradema<span class="_ _2"></span>rks or registered trademarks of PCI-SI<span class="_ _2"></span>G. </div><div class="t m0 x9 he y48 ff3 fs4 fc1 sc0 ls28 ws2a">All other product nam<span class="_ _2"></span>es are trademarks, re<span class="_ _2"></span>gistered trademark<span class="_ _2"></span>s, or servicemarks of their re<span class="_ _2"></span>spective owners. </div><div class="t m0 x9 hd y49 ff1 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 hd y4a ff1 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x2 h10 y4b ff3 fs6 fc1 sc0 ls0 ws0"> </div><div class="t m0 x15 he y4c ff3 fs4 fc1 sc0 ls1a ws19">Copyright © 2002-2010 PCI-SIG </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250f8e96caf5961923005a2/bg3.jpg"><div class="t m0 x16 h2 y4d ff8 fs0 fc0 sc0 ls29 ws2b">PCI EXPRESS BASE SPECIFICATION, REV. 3.0 </div><div class="t m0 x9 h2 y4e ff8 fs0 fc0 sc0 ls0 ws0"> <span class="_ _13"> </span><span class="ls6">3 </span></div><div class="t m0 x2 h11 y4f ff9 fs9 fc1 sc0 ls0 ws0"> </div><div class="t m0 x9 h12 y50 ffa fs3 fc1 sc0 ls2a ws0">Contents </div><div class="t m0 x9 h13 y51 ffb fs9 fc1 sc0 ls2b ws2c">OBJECTIVE OF THE SPECIFICATION<span class="_ _14"></span>....................................................................................<span class="_ _15"> </span>27 </div><div class="t m0 x9 h13 y52 ffb fs9 fc1 sc0 ls2b ws2d">DOCUMENT ORGANIZATION<span class="_"> </span>................................................................................................<span class="_ _15"> </span>27 </div><div class="t m0 x9 h13 y53 ffb fs9 fc1 sc0 ls2c ws2e">DOCUMENTATION CONVENTIONS<span class="_ _16"></span>......................................................................................<span class="_ _15"> </span>28 </div><div class="t m0 x9 h13 y54 ffb fs9 fc1 sc0 ls0 ws0">TERMS AND ACRONYMS<span class="_ _17"></span>........................................................................................................<span class="_ _15"> </span>29 </div><div class="t m0 x9 h13 y55 ffb fs9 fc1 sc0 ls2b ws2d">REFERENCE DOCUMENTS<span class="_ _14"></span>......................................................................................................<span class="_ _15"> </span>36 </div><div class="t m0 x9 h13 y56 ffb fs9 fc1 sc0 ls0 ws2f">1. INTRODUCTION<span class="_ _15"> </span>................................................................................................................<span class="_ _15"> </span><span class="ws0">37 </span></div><div class="t m0 x17 h13 y57 ffb fs9 fc1 sc0 ls0 ws30">1.1. A<span class="fsa ws0"> <span class="fs9">T</span><span class="ls2d">HIRD </span><span class="fs9">G</span><span class="ls2e">ENER<span class="_ _2"></span>ATION<span class="_ _2"></span> <span class="fs9 ls2f">I/O</span><span class="ls0"> <span class="fs9">I</span><span class="ls30">NTERCONNECT<span class="_"> </span></span><span class="fs9">...................................................................<span class="_ _15"> </span>37 </span></span></span></span></div><div class="t m0 x17 h13 y58 ffb fs9 fc1 sc0 ls31 ws31">1.2. PCI<span class="fsa ls0 ws0"> <span class="fs9">E</span><span class="ls32">XPRESS </span><span class="fs9">L</span><span class="ls33">INK<span class="_ _1"></span></span><span class="fs9">.........................................................................................................<span class="_ _15"> </span>39 </span></span></div><div class="t m0 x17 h13 y59 ffb fs9 fc1 sc0 ls31 ws31">1.3. PCI<span class="fsa ls0 ws0"> <span class="fs9">E</span><span class="ls32">XPRESS </span><span class="fs9">F</span><span class="ls34">ABRIC <span class="_ _1"></span></span><span class="fs9">T</span><span class="ls35">OPOLOGY<span class="_"> </span></span><span class="fs9">..................................................................................<span class="_"> </span>41 </span></span></div><div class="t m0 x18 h13 y5a ffc fs9 fc1 sc0 ls0 ws0">1.3.1.<span class="ffb"> <span class="_ _18"> </span></span>Root Complex<span class="_ _14"></span>........................................................................................................<span class="_ _15"> </span>41<span class="ffb"> </span></div><div class="t m0 x18 h13 y5b ffc fs9 fc1 sc0 ls0 ws0">1.3.2.<span class="ffb"> <span class="_ _18"> </span></span>Endpoints<span class="_ _15"> </span>..............................................................................................................<span class="_ _15"> </span>42<span class="ffb"> </span></div><div class="t m0 x18 h13 y5c ffc fs9 fc1 sc0 ls0 ws0">1.3.3.<span class="ffb"> <span class="_ _18"> </span></span>Switch<span class="_ _17"></span>....................................................................................................................<span class="_ _15"> </span>45<span class="ffb"> </span></div><div class="t m0 x18 h13 y5d ffc fs9 fc1 sc0 ls0 ws0">1.3.4.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Root Complex Event Collector..............................................................................<span class="_ _15"> </span>46</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y5e ffc fs9 fc1 sc0 ls0 ws0">1.3.5.<span class="ffb"> <span class="_ _18"> </span></span>PCI Express to PCI/PCI-X Bridge<span class="_ _1"></span>........................................................................<span class="_ _15"> </span>46<span class="ffb"> </span></div><div class="t m0 x17 h13 y5f ffb fs9 fc1 sc0 ls31 ws31">1.4. PCI<span class="fsa ls0 ws0"> <span class="fs9">E</span><span class="ls32">XPRESS </span><span class="fs9">F</span><span class="ls34">ABRIC <span class="_ _1"></span></span><span class="fs9">T</span>OPOLOGY <span class="fs9">C</span><span class="ls37">ONFIGURATION<span class="_ _16"></span></span><span class="fs9">.......................................................<span class="_ _15"> </span>46 </span></span></div><div class="t m0 x17 h13 y60 ffb fs9 fc1 sc0 ls31 ws31">1.5. PCI<span class="fsa ls0 ws0"> <span class="fs9">E</span><span class="ls32">XPRESS </span><span class="fs9">L</span>AYERING <span class="fs9">O</span><span class="ls38">VERVIEW<span class="_ _14"></span></span><span class="fs9">..............................................................................<span class="_ _15"> </span>47 </span></span></div><div class="t m0 x18 h13 y61 ffc fs9 fc1 sc0 ls0 ws0">1.5.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws33">Transaction Layer<span class="_ _17"></span>.................................................................................................<span class="_ _15"> </span>48</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y62 ffc fs9 fc1 sc0 ls0 ws0">1.5.2.<span class="ffb"> <span class="_ _18"> </span></span>Data Link Layer<span class="_ _16"></span>....................................................................................................<span class="_ _15"> </span>48<span class="ffb"> </span></div><div class="t m0 x18 h13 y63 ffc fs9 fc1 sc0 ls0 ws0">1.5.3.<span class="ffb"> <span class="_ _18"> </span></span>Physical Layer<span class="_ _15"> </span>......................................................................................................<span class="_ _15"> </span>49<span class="ffb"> </span></div><div class="t m0 x18 h13 y64 ffc fs9 fc1 sc0 ls0 ws0">1.5.4.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Layer Functions and Services<span class="_ _17"></span>...............................................................................<span class="_ _15"> </span>49</span><span class="ffb"> </span></div><div class="t m0 x9 h13 y65 ffb fs9 fc1 sc0 ls2b ws2d">2. <span class="_ _19"> </span>TRANSACTION LAYER SPECIFICATION<span class="_ _15"> </span>.....................................................................<span class="_ _15"> </span>53 </div><div class="t m0 x17 h13 y66 ffb fs9 fc1 sc0 ls0 ws30">2.1. T</div><div class="t m0 x19 h13 y67 ffb fsa fc1 sc0 ls2d ws0">RANSACTION <span class="fs9 ls0">L</span><span class="ls39">AYER <span class="fs9 ls0">O</span><span class="ls38">VERVIEW<span class="_ _1"></span><span class="fs9 ls0">..................................................................................<span class="_ _15"> </span>53 </span></span></span></div><div class="t m0 x18 h13 y68 ffc fs9 fc1 sc0 ls0 ws0">2.1.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ws34">Address Spaces, Transaction Types, and Usage<span class="_ _1"></span>...................................................<span class="_ _15"> </span>54</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y69 ffc fs9 fc1 sc0 ls0 ws0">2.1.2.<span class="ffb"> <span class="_ _18"> </span></span>Packet Format Overview<span class="_ _15"> </span>......................................................................................<span class="_ _15"> </span>56<span class="ffb"> </span></div><div class="t m0 x17 h13 y6a ffb fs9 fc1 sc0 ls0 ws30">2.2. T<span class="fsa ls2d ws0">RANSACTION </span><span class="ws0">L<span class="fsa ls39">AYER </span>P<span class="fsa ls3a">ROT<span class="_ _1"></span>OCOL </span>-<span class="fsa"> </span>P<span class="fsa ls3b">ACKET </span>D<span class="fsa ls3c">EFINITION<span class="_ _14"></span></span>...............................................<span class="_"> </span>58 </span></div><div class="t m0 x18 h13 y6b ffc fs9 fc1 sc0 ls0 ws0">2.2.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws35">Common Packet Header Fields<span class="_ _1a"> </span>............................................................................<span class="_ _15"> </span>58</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y6c ffc fs9 fc1 sc0 ls0 ws0">2.2.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">TLPs with Data Payloads - Rules<span class="_ _16"></span>.........................................................................<span class="_ _15"> </span>61</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y6d ffc fs9 fc1 sc0 ls0 ws0">2.2.3.<span class="ffb"> <span class="_ _18"> </span></span>TLP Digest Rules<span class="_ _15"> </span>..................................................................................................<span class="_ _15"> </span>65<span class="ffb"> </span></div><div class="t m0 x18 h13 y6e ffc fs9 fc1 sc0 ls0 ws0">2.2.4.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws35">Routing and Addressing Rules<span class="_ _16"></span>..............................................................................<span class="_ _15"> </span>65</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y6f ffc fs9 fc1 sc0 ls0 ws0">2.2.5.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">First/Last DW Byte Enables Rules<span class="_ _1"></span>........................................................................<span class="_ _15"> </span>69</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y70 ffc fs9 fc1 sc0 ls0 ws0">2.2.6.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws33">Transaction Descriptor<span class="_ _14"></span>.........................................................................................<span class="_"> </span>71</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y71 ffc fs9 fc1 sc0 ls0 ws0">2.2.7.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Memory, I/O, and Configuration Request Rules<span class="_ _1"></span>...................................................<span class="_ _15"> </span>77</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y72 ffc fs9 fc1 sc0 ls0 ws0">2.2.8.<span class="ffb"> <span class="_ _18"> </span></span>Message Request Rules<span class="_ _16"></span>.........................................................................................<span class="_ _15"> </span>83<span class="ffb"> </span></div><div class="t m0 x18 h13 y73 ffc fs9 fc1 sc0 ls0 ws0">2.2.9.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws33">Completion Rules<span class="_ _16"></span>..................................................................................................<span class="_ _15"> </span>97</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y74 ffc fs9 fc1 sc0 ls0 ws0">2.2.10.<span class="ffb"> <span class="_ _19"> </span></span><span class="ws36">TLP Prefix Rules<span class="_ _16"></span>.................................................................................................<span class="_ _15"> </span>100</span><span class="ffb"> </span></div><div class="t m0 x17 h13 y75 ffb fs9 fc1 sc0 ls0 ws30">2.3. H</div><div class="t m0 x1a h13 y76 ffb fsa fc1 sc0 ls3d ws37">ANDLING OF <span class="fs9 ls0 ws0">R<span class="fsa ls3c">ECEIVED </span><span class="ls3e">TLP</span><span class="fsa">S<span class="_ _1"></span></span>....................................................................................<span class="_ _15"> </span>104 </span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250f8e96caf5961923005a2/bg4.jpg"><div class="t m0 x16 h2 y4d ff8 fs0 fc0 sc0 ls29 ws2b">PCI EXPRESS BASE SPECIFICATION, REV. 3.0 </div><div class="t m0 x2 h2 y77 ff8 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x9 h2 y4e ff8 fs0 fc0 sc0 ls6 ws0">4 </div><div class="t m0 x18 h13 y78 ffc fs9 fc1 sc0 ls0 ws0">2.3.1.<span class="ffb"> <span class="_ _18"> </span></span>Request Handling Rules<span class="_ _17"></span>......................................................................................<span class="_ _15"> </span>107<span class="ffb"> </span></div><div class="t m0 x18 h13 y79 ffc fs9 fc1 sc0 ls0 ws0">2.3.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws38">Completion Handling Rules<span class="_ _17"></span>................................................................................<span class="_ _15"> </span>120</span><span class="ffb"> </span></div><div class="t m0 x17 h13 y7a ffb fs9 fc1 sc0 ls0 ws30">2.4. T<span class="fsa ls2d ws0">RANSACTION </span><span class="ws0">O<span class="fsa ls3f">RDERING<span class="_ _17"></span></span>............................................................................................<span class="_"> </span>122 </span></div><div class="t m0 x18 h13 y7b ffc fs9 fc1 sc0 ls0 ws0">2.4.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws38">Transaction Ordering Rules<span class="_ _15"> </span>...............................................................................<span class="_ _15"> </span>122</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y7c ffc fs9 fc1 sc0 ls0 ws0">2.4.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Update Ordering and Granularity Observed by a Read Transaction<span class="_ _16"></span>................<span class="_ _15"> </span>126</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y7d ffc fs9 fc1 sc0 ls0 ws0">2.4.3.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Update Ordering and Granularity Provided by a Write Transaction<span class="_ _16"></span>................<span class="_ _15"> </span>127</span><span class="ffb"> </span></div><div class="t m0 x17 h13 y7e ffb fs9 fc1 sc0 ls0 ws30">2.5. V<span class="fsa ls38 ws0">IRTUAL </span><span class="ws0">C<span class="fsa ls40">HANNEL </span><span class="ls41">(VC)</span><span class="fsa"> </span>M<span class="fsa ls3d">ECHANISM<span class="_ _1"></span></span>........................................................................<span class="_ _15"> </span>128 </span></div><div class="t m0 x18 h13 y7f ffc fs9 fc1 sc0 ls0 ws0">2.5.1.<span class="ffb"> <span class="_ _18"> </span></span>Virtual Channel Identification (VC ID)<span class="_ _16"></span>..............................................................<span class="_ _15"> </span>130<span class="ffb"> </span></div><div class="t m0 x18 h13 y80 ffc fs9 fc1 sc0 ls0 ws0">2.5.2.<span class="ffb"> <span class="_ _18"> </span></span>TC to VC Mapping<span class="_ _16"></span>..............................................................................................<span class="_ _15"> </span>131<span class="ffb"> </span></div><div class="t m0 x18 h13 y81 ffc fs9 fc1 sc0 ls0 ws0">2.5.3.<span class="ffb"> <span class="_ _18"> </span></span><span class="ws39">VC and TC Rules<span class="_ _1"></span>.................................................................................................<span class="_ _15"> </span>132</span><span class="ffb"> </span></div><div class="t m0 x17 h13 y82 ffb fs9 fc1 sc0 ls0 ws30">2.6. O<span class="fsa ls42 ws3a">RDERING AND </span><span class="ws0">R<span class="fsa ls30">ECEIVE </span>B<span class="fsa ls43">UFFER </span>F<span class="fsa ls44">LOW </span>C<span class="fsa ls2d">ONTROL<span class="_"> </span></span>.....................................................<span class="_ _15"> </span>133 </span></div><div class="t m0 x18 h13 y83 ffc fs9 fc1 sc0 ls0 ws0">2.6.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Flow Control Rules<span class="_ _16"></span>.............................................................................................<span class="_ _15"> </span>134<span class="_ _2"></span><span class="ffb ls0 ws0"> </span></span></div><div class="t m0 x17 h13 y84 ffb fs9 fc1 sc0 ls0 ws30">2.7. D<span class="fsa ls45 ws0">ATA </span><span class="ws0">I<span class="fsa ls46">NTEGRITY<span class="_ _1a"> </span></span>.........................................................................................................<span class="_ _15"> </span>145 </span></div><div class="t m0 x18 h13 y85 ffc fs9 fc1 sc0 ls0 ws0">2.7.1.<span class="ffb"> <span class="_ _18"> </span></span>ECRC Rules<span class="_ _15"> </span>........................................................................................................<span class="_ _15"> </span>145<span class="ffb"> </span></div><div class="t m0 x18 h13 y86 ffc fs9 fc1 sc0 ls0 ws0">2.7.2.<span class="ffb"> <span class="_ _18"> </span></span>Error Forwarding<span class="_ _16"></span>...............................................................................................<span class="_ _15"> </span>149<span class="ffb"> </span></div><div class="t m0 x17 h13 y87 ffb fs9 fc1 sc0 ls0 ws30">2.8. C<span class="fsa ls47 ws0">OMPLETION </span><span class="ws0">T<span class="fsa ls3c">IMEOUT </span>M<span class="fsa ls32">ECHANISM<span class="_ _1a"> </span></span>...........................................................................<span class="_ _15"> </span>151 </span></div><div class="t m0 x17 h13 y88 ffb fs9 fc1 sc0 ls0 ws30">2.9. L<span class="fsa ls32 ws0">INK </span><span class="ws0">S<span class="fsa ls48">TATUS </span>D<span class="fsa ls40">EPENDENCIES<span class="_"> </span></span>......................................................................................<span class="_ _15"> </span>151 </span></div><div class="t m0 x18 h13 y89 ffc fs9 fc1 sc0 ls0 ws0">2.9.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws3b">Transaction Layer Behavior in DL_Down Status<span class="_ _1"></span>...............................................<span class="_ _15"> </span>151</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y8a ffc fs9 fc1 sc0 ls0 ws0">2.9.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws3b">Transaction Layer Behavior in DL_Up Status<span class="_ _15"> </span>...................................................<span class="_ _15"> </span>153</span><span class="ffb"> </span></div><div class="t m0 x9 h13 y8b ffb fs9 fc1 sc0 ls2b ws2c">3. <span class="_ _19"> </span>DATA LINK LAYER SPECIFICATION<span class="_ _16"></span>..........................................................................<span class="_ _15"> </span>155 </div><div class="t m0 x17 h13 y8c ffb fs9 fc1 sc0 ls0 ws30">3.1. D<span class="fsa ls45 ws0">ATA </span><span class="ws0">L<span class="fsa ls32">INK </span>L<span class="fsa ls39">AYER </span>O<span class="fsa ls38">VERVIEW<span class="_ _1a"> </span></span>....................................................................................<span class="_ _15"> </span>155 </span></div><div class="t m0 x17 h13 y8d ffb fs9 fc1 sc0 ls0 ws30">3.2. D<span class="fsa ls45 ws0">ATA </span><span class="ws0">L<span class="fsa ls32">INK </span>C<span class="fsa ls38 ws3c">ONTROL AND </span>M<span class="fsa ls43">ANAGEMENT </span>S<span class="fsa ls49">TATE </span>M<span class="fsa ls4a">ACHINE<span class="_ _1b"> </span></span>......................................<span class="_ _15"> </span>157 </span></div><div class="t m0 x18 h13 y8e ffc fs9 fc1 sc0 ls0 ws0">3.2.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls4b ws3d">Data Link Control and Management State Machine Rules<span class="_ _1a"> </span>................................<span class="_ _15"> </span>158</span><span class="ffb"> </span></div><div class="t m0 x17 h13 y8f ffb fs9 fc1 sc0 ls0 ws30">3.3. F<span class="fsa ls4c ws0">LOW </span><span class="ws0">C<span class="fsa ls4d">ONTROL </span>I<span class="fsa ls33">NITIALIZATION </span>P<span class="fsa ls4e">ROTOCOL<span class="_"> </span></span>...............................................................<span class="_ _15"> </span>160 </span></div><div class="t m0 x18 h13 y90 ffc fs9 fc1 sc0 ls0 ws0">3.3.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Flow Control Initializati</span>on State Machine Rules<span class="_ _15"> </span>...............................................<span class="_ _15"> </span>160<span class="ffb"> </span></div><div class="t m0 x17 h13 y91 ffb fs9 fc1 sc0 ls0 ws30">3.4. D<span class="fsa ls45 ws0">ATA </span><span class="ws0">L<span class="fsa ls32">INK </span>L<span class="fsa ls39">AYER </span>P<span class="fsa ls4f">ACKETS </span><span class="ls31">(DLLP</span><span class="fsa">S</span>)<span class="_ _17"></span>........................................................................<span class="_ _15"> </span>164 </span></div><div class="t m0 x18 h13 y92 ffc fs9 fc1 sc0 ls0 ws0">3.4.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws3e">Data Link Layer Packet Rules<span class="_ _15"> </span>............................................................................<span class="_ _15"> </span>164</span><span class="ffb"> </span></div><div class="t m0 x17 h13 y93 ffb fs9 fc1 sc0 ls0 ws30">3.5. D<span class="fsa ls45 ws0">ATA </span><span class="ws0">I<span class="fsa ls46">NTEGRITY<span class="_ _1a"> </span></span>.........................................................................................................<span class="_ _15"> </span>169 </span></div><div class="t m0 x18 h13 y94 ffc fs9 fc1 sc0 ls0 ws0">3.5.1.<span class="ffb"> <span class="_ _18"> </span></span>Introduction.........................................................................................................<span class="_ _15"> </span>169<span class="ffb"> </span></div><div class="t m0 x18 h13 y95 ffc fs9 fc1 sc0 ls0 ws0">3.5.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls50 ws3f">LCRC, Sequence Number, and Retry <span class="ls4b ws40">Management (TLP Transmitter)..............<span class="_ _15"> </span>169</span></span><span class="ffb"> </span></div><div class="t m0 x18 h13 y96 ffc fs9 fc1 sc0 ls0 ws0">3.5.3.<span class="ffb"> <span class="_ _18"> </span></span><span class="ws41">LCRC and Sequence Number (TLP Receiver)<span class="_ _16"></span>....................................................<span class="_ _15"> </span>182</span><span class="ffb"> </span></div><div class="t m0 x9 h13 y97 ffb fs9 fc1 sc0 ls2b ws2d">4. <span class="_ _19"> </span>PHYSICAL LAYER SPECIFICATION<span class="_ _16"></span>............................................................................<span class="_ _15"> </span>191 </div><div class="t m0 x17 h13 y98 ffb fs9 fc1 sc0 ls0 ws30">4.1. I</div><div class="t m0 x1b h13 y99 ffb fsa fc1 sc0 ls35 ws0">NTRODUCTION<span class="_"> </span><span class="fs9 ls0">............................................................................................................<span class="_ _15"> </span>191 </span></div><div class="t m0 x17 h13 y9a ffb fs9 fc1 sc0 ls0 ws30">4.2. L<span class="fsa ls37 ws0">OGICAL </span><span class="ws0">S<span class="fsa ls51">UB</span>-<span class="fsa ls3a">BLOCK<span class="_ _1"></span></span>...................................................................................................<span class="_ _15"> </span>191 </span></div><div class="t m0 x18 h13 y9b ffc fs9 fc1 sc0 ls0 ws0">4.2.1.<span class="ffb"> <span class="_ _18"> </span></span>Encoding for 2.5 GT/s and 5.0 GT/s Data Rates<span class="_ _16"></span>................................................<span class="_ _15"> </span>192<span class="ffb"> </span></div><div class="t m0 x18 h13 y9c ffc fs9 fc1 sc0 ls0 ws0">4.2.2.<span class="ffb"> <span class="_ _18"> </span></span>Encoding for 8.0 GT/s and Higher Data Rates...................................................<span class="_ _15"> </span>200<span class="ffb"> </span></div><div class="t m0 x18 h13 y9d ffc fs9 fc1 sc0 ls0 ws0">4.2.3.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws42">Link Equalization Procedure for 8.0 GT/s Data Rate<span class="_ _15"> </span>........................................<span class="_ _15"> </span>218</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y9e ffc fs9 fc1 sc0 ls0 ws0">4.2.4.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Link Initialization and Training<span class="_ _1"></span>..........................................................................<span class="_ _15"> </span>226</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y9f ffc fs9 fc1 sc0 ls0 ws0">4.2.5.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls50 ws3f">Link Training and Status State </span><span class="ws43">Machine (LTSSM) Descriptions<span class="_ _1"></span>........................<span class="_ _15"> </span>244</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya0 ffc fs9 fc1 sc0 ls0 ws0">4.2.6.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Link Training and Status State Rules<span class="_ _1"></span>..................................................................<span class="_ _15"> </span>247</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya1 ffc fs9 fc1 sc0 ls0 ws0">4.2.7.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Clock Tolerance Compensation<span class="_ _17"></span>..........................................................................<span class="_ _15"> </span>314</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya2 ffc fs9 fc1 sc0 ls0 ws0">4.2.8.<span class="ffb"> <span class="_ _18"> </span></span><span class="ws36">Compliance Pattern in 8b/10b Encoding<span class="_ _1"></span>............................................................<span class="_ _15"> </span>317</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya3 ffc fs9 fc1 sc0 ls0 ws0">4.2.9.<span class="ffb"> <span class="_ _18"> </span></span><span class="ws34">Modified Compliance Pattern in 8b/10b Encoding<span class="_ _1a"> </span>............................................<span class="_ _15"> </span>318</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya4 ffc fs9 fc1 sc0 ls0 ws0">4.2.10.<span class="ffb"> <span class="_ _19"> </span></span><span class="ls36 ws38">Compliance Pattern in 128b/130b Encoding<span class="_ _1"></span>......................................................<span class="_ _15"> </span>320</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya5 ffc fs9 fc1 sc0 ls0 ws0">4.2.11.<span class="ffb"> <span class="_ _19"> </span></span><span class="ls4b ws40">Modified Compliance Pattern<span class="ls2b ws44"> in 128b/130b Encoding<span class="_ _1a"> </span>......................................<span class="_ _15"> </span>322</span></span><span class="ffb"> </span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6250f8e96caf5961923005a2/bg5.jpg"><div class="t m0 x16 h2 y4d ff8 fs0 fc0 sc0 ls29 ws2b">PCI EXPRESS BASE SPECIFICATION, REV. 3.0 </div><div class="t m0 x9 h2 y4e ff8 fs0 fc0 sc0 ls0 ws0"> <span class="_ _13"> </span><span class="ls6">5 </span></div><div class="t m0 x17 h13 ya6 ffb fs9 fc1 sc0 ls0 ws30">4.3. E<span class="fsa ls52 ws0">LECTRICAL </span><span class="ws0">S<span class="fsa ls53">UB</span>-<span class="fsa ls54">BLOCK<span class="_"> </span></span>.............................................................................................<span class="_ _15"> </span>323 </span></div><div class="t m0 x18 h13 y79 ffc fs9 fc1 sc0 ls0 ws0">4.3.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws38">Electrical Specification Organization.................................................................<span class="_ _15"> </span>323</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya7 ffc fs9 fc1 sc0 ls0 ws0">4.3.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls55 ws45">Interoperability Criteria fo<span class="ls36 ws3d">r 2.5, 5.0, and 8.0 GT/s Devices<span class="_ _1a"> </span>..............................<span class="_ _15"> </span>323</span></span><span class="ffb"> </span></div><div class="t m0 x18 h13 y7b ffc fs9 fc1 sc0 ls0 ws0">4.3.3.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws33">Transmitter Specification<span class="_ _1"></span>....................................................................................<span class="_"> </span>325</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y7c ffc fs9 fc1 sc0 ls0 ws0">4.3.4.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Receiver Specifications<span class="_ _16"></span>.......................................................................................<span class="_ _15"> </span>359</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y7d ffc fs9 fc1 sc0 ls0 ws0">4.3.5.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Low Frequency and Miscellaneous Signaling Requirements<span class="_ _16"></span>.............................<span class="_ _15"> </span>382</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya8 ffc fs9 fc1 sc0 ls0 ws0">4.3.6.<span class="ffb"> <span class="_ _18"> </span></span>Channel Specification<span class="_ _16"></span>.........................................................................................<span class="_ _15"> </span>387<span class="ffb"> </span></div><div class="t m0 x18 h13 y7f ffc fs9 fc1 sc0 ls0 ws0">4.3.7.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Refclk Specifications<span class="_ _16"></span>...........................................................................................<span class="_ _15"> </span>400</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y80 ffc fs9 fc1 sc0 ls0 ws0">4.3.8.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws38">Refclk Specifications for 8.0 GT/s<span class="_ _1"></span>.......................................................................<span class="_ _15"> </span>408</span><span class="ffb"> </span></div><div class="t m0 x9 h13 ya9 ffb fs9 fc1 sc0 ls2b ws46">5. POWER <span class="_ _1c"></span>MANAGEMENT<span class="_ _1"></span>.................................................................................................<span class="_ _15"> </span>413 </div><div class="t m0 x17 h13 yaa ffb fs9 fc1 sc0 ls0 ws30">5.1. O<span class="fsa ls38 ws0">VERVIEW<span class="_ _16"> </span></span><span class="ws0">...................................................................................................................<span class="_ _15"> </span>413 </span></div><div class="t m0 x18 h13 yab ffc fs9 fc1 sc0 ls0 ws0">5.1.1.<span class="ffb"> <span class="_ _18"> </span></span>Statement of Requirements<span class="_ _1"></span>..................................................................................<span class="_ _15"> </span>414<span class="ffb"> </span></div><div class="t m0 x17 h13 yac ffb fs9 fc1 sc0 ls0 ws30">5.2. L<span class="fsa ls32 ws0">INK </span><span class="ws0">S<span class="fsa ls30">TATE </span>P<span class="fsa ls43">OWER </span>M<span class="fsa ls43">ANAGEMENT<span class="_ _1"></span></span>.............................................................................<span class="_ _15"> </span>414 </span></div><div class="t m0 x17 h13 yad ffb fs9 fc1 sc0 ls0 ws30">5.3. PCI-PM</div><div class="t m0 x1c h13 yae ffb fsa fc1 sc0 ls0 ws0"> <span class="fs9">S</span><span class="ls4a">OFTWARE </span><span class="fs9">C</span><span class="ls46">OMPATIBLE </span><span class="fs9">M</span><span class="ls56">ECHANISMS<span class="_ _14"></span></span><span class="fs9">.........................................................<span class="_ _15"> </span>419 </span></div><div class="t m0 x18 h13 yaf ffc fs9 fc1 sc0 ls0 ws0">5.3.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls50 ws3f">Device Power Management States (D-States) of a Function..............................<span class="_ _15"> </span>419</span><span class="ffb"> </span></div><div class="t m0 x18 h13 yb0 ffc fs9 fc1 sc0 ls0 ws0">5.3.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls4b ws47">PM Software Control of the Li</span>nk Power Management State<span class="_ _1"></span>..............................<span class="_ _15"> </span>424<span class="ffb"> </span></div><div class="t m0 x18 h13 yb1 ffc fs9 fc1 sc0 ls0 ws0">5.3.3.<span class="ffb"> <span class="_ _18"> </span></span>Power Management Event Mechanisms<span class="_ _1a"></span>.............................................................<span class="_ _15"> </span>429<span class="_ _2"></span><span class="ffb"> </span></div><div class="t m0 x17 h13 yb2 ffb fs9 fc1 sc0 ls0 ws30">5.4. N</div><div class="t m0 x1a h13 yb3 ffb fsa fc1 sc0 ls57 ws0">ATIVE <span class="fs9 ls58">PCI</span><span class="ls0"> <span class="fs9">E</span><span class="ls3d">XPRESS </span><span class="fs9">P</span><span class="ls59">OWER </span><span class="fs9">M</span><span class="ls3b">ANAGEMENT </span><span class="fs9">M</span></span>ECHANISMS<span class="_ _17"></span><span class="fs9 ls0">.......................................<span class="_ _15"> </span>436 </span></div><div class="t m0 x18 h13 yb4 ffc fs9 fc1 sc0 ls0 ws0">5.4.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws3e">Active State Power Management (ASPM)<span class="_ _15"> </span>..........................................................<span class="_ _15"> </span>436</span><span class="ffb"> </span></div><div class="t m0 x17 h13 yb5 ffb fs9 fc1 sc0 ls0 ws30">5.5. A<span class="fsa ls5a ws0">UXILIARY </span><span class="ws0">P<span class="fsa ls39">OWER </span>S<span class="fsa ls5b">UPPORT<span class="_ _17"></span></span>.......................................................................................<span class="_ _15"> </span>455 </span></div><div class="t m0 x18 h13 yb6 ffc fs9 fc1 sc0 ls0 ws0">5.5.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls4b ws40">Auxiliary Power Enabling...................................................................................<span class="_ _15"> </span>455<span class="_ _2"></span><span class="ffb ls0 ws0"> </span></span></div><div class="t m0 x17 h13 y8d ffb fs9 fc1 sc0 ls0 ws30">5.6. P<span class="fsa ls43 ws0">OWER </span><span class="ws0">M<span class="fsa ls45">ANAGEMENT </span>S<span class="fsa ls46">YSTEM </span>M<span class="fsa ls3d ws37">ESSAGES AND </span><span class="ls5c">DLLP</span><span class="fsa">S<span class="_ _1"></span></span>.............................................<span class="_ _15"> </span>456 </span></div><div class="t m0 x9 h13 yb7 ffb fs9 fc1 sc0 ls2b ws46">6. SYSTEM <span class="_ _1c"></span>ARCHITECTURE<span class="_ _15"> </span>.............................................................................................<span class="_ _15"> </span>459 </div><div class="t m0 x17 h13 yb8 ffb fs9 fc1 sc0 ls0 ws30">6.1. I<span class="fsa ls5d ws48">NTERRUPT AND </span><span class="ls2c ws0">PME<span class="fsa ls0"> <span class="fs9">S</span><span class="ls5b">UPPORT<span class="_ _16"> </span></span><span class="fs9">...................................................................................<span class="_ _15"> </span>459 </span></span></span></div><div class="t m0 x18 h13 yb9 ffc fs9 fc1 sc0 ls0 ws0">6.1.1.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls5e ws49">Rationale for PCI Expre</span><span class="ws36">ss Interrupt Model........................................................<span class="_ _15"> </span>459</span><span class="ffb"> </span></div><div class="t m0 x18 h13 yba ffc fs9 fc1 sc0 ls0 ws0">6.1.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ws4a">PCI Compatible INTx Emulation<span class="_ _14"></span>........................................................................<span class="_ _15"> </span>460</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ybb ffc fs9 fc1 sc0 ls0 ws0">6.1.3.<span class="ffb"> <span class="_ _18"> </span></span>INTx Emulation Software Model<span class="_ _15"> </span>........................................................................<span class="_ _15"> </span>460<span class="ffb"> </span></div><div class="t m0 x18 h13 ybc ffc fs9 fc1 sc0 ls0 ws0">6.1.4.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls4b ws40">Message Signaled Interrupt (MSI/MSI-X) Support.............................................<span class="_ _15"> </span>460</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ybd ffc fs9 fc1 sc0 ls0 ws0">6.1.5.<span class="ffb"> <span class="_ _18"> </span></span>PME Support<span class="_ _1"></span>.......................................................................................................<span class="_ _15"> </span>462<span class="ffb"> </span></div><div class="t m0 x18 h13 ybe ffc fs9 fc1 sc0 ls0 ws0">6.1.6.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Native PME Software Model<span class="_ _15"> </span>..............................................................................<span class="_ _15"> </span>462</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ybf ffc fs9 fc1 sc0 ls0 ws0">6.1.7.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws35">Legacy PME Software Model<span class="_ _15"> </span>.............................................................................<span class="_ _15"> </span>463</span><span class="ffb"> </span></div><div class="t m0 x18 h13 yc0 ffc fs9 fc1 sc0 ls0 ws0">6.1.8.<span class="ffb"> <span class="_ _18"> </span></span>Operating System Power Management Notification...........................................<span class="_ _15"> </span>463<span class="ffb"> </span></div><div class="t m0 x18 h13 yc1 ffc fs9 fc1 sc0 ls0 ws0">6.1.9.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls4b ws3d">PME Routing Between PCI Express and PCI Hierarchies<span class="_ _15"> </span>................................<span class="_ _15"> </span>463</span><span class="ffb"> </span></div><div class="t m0 x17 h13 yc2 ffb fs9 fc1 sc0 ls0 ws30">6.2. E</div><div class="t m0 x19 h13 y9a ffb fsa fc1 sc0 ls4e ws0">RROR <span class="fs9 ls0">S</span><span class="ls45 ws4b">IGNALING AND <span class="_ _1"></span></span><span class="fs9 ls0">L</span><span class="ls32">OGGING<span class="fs9 ls0">................................................................................<span class="_ _15"> </span>464 </span></span></div><div class="t m0 x18 h13 y9b ffc fs9 fc1 sc0 ls0 ws0">6.2.1.<span class="ffb"> <span class="_ _18"> </span></span>Scope<span class="_ _16"></span>...................................................................................................................<span class="_ _15"> </span>464<span class="ffb"> </span></div><div class="t m0 x18 h13 y9c ffc fs9 fc1 sc0 ls0 ws0">6.2.2.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Error Classification<span class="_ _1a"></span>............................................................................................<span class="_ _15"> </span>464</span><span class="ffb"> </span></div><div class="t m0 x18 h13 y9d ffc fs9 fc1 sc0 ls0 ws0">6.2.3.<span class="ffb"> <span class="_ _18"> </span></span>Error Signaling<span class="_ _16"></span>...................................................................................................<span class="_ _15"> </span>466<span class="ffb"> </span></div><div class="t m0 x18 h13 y9e ffc fs9 fc1 sc0 ls0 ws0">6.2.4.<span class="ffb"> <span class="_ _18"> </span></span>Error Logging<span class="_ _16"></span>.....................................................................................................<span class="_ _15"> </span>474<span class="ffb"> </span></div><div class="t m0 x18 h13 y9f ffc fs9 fc1 sc0 ls0 ws0">6.2.5.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls50 ws44">Sequence of Device Error Signa<span class="ls36 ws35">ling and Logging Operations<span class="_ _15"> </span>..........................<span class="_ _15"> </span>478</span></span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya0 ffc fs9 fc1 sc0 ls0 ws0">6.2.6.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws32">Error Message Controls<span class="_ _15"> </span>.....................................................................................<span class="_ _15"> </span>480</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya1 ffc fs9 fc1 sc0 ls0 ws0">6.2.7.<span class="ffb"> <span class="_ _18"> </span></span>Error Listing and Rules<span class="_ _15"> </span>......................................................................................<span class="_ _15"> </span>481<span class="ffb"> </span></div><div class="t m0 x18 h13 ya2 ffc fs9 fc1 sc0 ls0 ws0">6.2.8.<span class="ffb"> <span class="_ _18"> </span></span><span class="ls36 ws3e">Virtual PCI Bridge Error Handling<span class="_ _1"></span>....................................................................<span class="_ _15"> </span>486</span><span class="ffb"> </span></div><div class="t m0 x18 h13 ya3 ffc fs9 fc1 sc0 ls0 ws0">6.2.9.<span class="ffb"> <span class="_ _18"> </span></span>Internal Errors<span class="_ _16"></span>....................................................................................................<span class="_ _15"> </span>488<span class="ffb"> </span></div><div class="t m0 x17 h13 yc3 ffb fs9 fc1 sc0 ls0 ws30">6.3. V<span class="fsa ls38 ws0">IRTUAL </span><span class="ws0">C<span class="fsa ls40">HANNEL </span>S<span class="fsa ls5f">UPPORT<span class="_ _1d"> </span></span>......................................................................................<span class="_ _15"> </span>489 </span></div><div class="t m0 x18 h13 ya5 ffc fs9 fc1 sc0 ls0 ws0">6.3.1.<span class="ffb"> <span class="_ _18"> </span></span>Introduction and Scope<span class="_ _16"></span>.......................................................................................<span class="_ _15"> </span>489<span class="ffb"> </span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>