Jetson_TX2_TX2i_Module_DataSheet_v01.rar

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英伟达 jetson TX2 数据文档说明
Jetson_TX2_TX2i_Module_DataSheet_v01.rar
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">JETSON | TX2/TX2i | DATASHEET | 1.0 <span class="ls1">| </span>SU<span class="_ _0"></span>BJECT TO CHANGE <span class="ls1">| </span>COPYRIGHT &#169; 2<span class="_ _0"></span>014 <span class="ff2">&#8211;</span> <span class="ls2">201</span>8 NVIDIA CORPORATION. ALL RIGHTS RESERVE<span class="_ _1"></span>D. <span class="_ _2"> </span>1<span class="ff3"> </span></div><div class="c x2 y2 w2 h3"><div class="t m0 x3 h4 y3 ff4 fs1 fc0 sc0 ls0 ws0">DATA SHEET </div><div class="t m0 x3 h5 y4 ff4 fs2 fc1 sc0 ls0 ws0">NVIDIA<span class="_ _3"></span> Jetson <span class="_ _1"></span>T<span class="_ _1"></span>X2 <span class="ls3">/ <span class="_ _1"></span><span class="ls0">TX2i System-<span class="ls4">on</span>-Module<span class="_ _1"></span> </span></span></div><div class="t m0 x3 h6 y5 ff4 fs3 fc1 sc0 ls0 ws0">Pascal GPU + <span class="_ _4"></span>ARMv8 + 8GB LPDD<span class="_ _0"></span>R4 + 32GB eMMC<span class="_ _0"></span><span class="ff5"> </span></div></div><div class="t m0 x1 h7 y6 ff5 fs4 fc0 sc0 ls0 ws0">NVIDIA Jetson Modules: TX2, TX2i </div><div class="t m0 x4 h7 y7 ff5 fs4 fc0 sc0 ls0 ws0">References to T<span class="ls5">X2</span> include (can be read as) TX2i except where explicitly noted. </div><div class="t m0 x1 h8 y8 ff4 fs5 fc0 sc0 ls0 ws0">Description </div><div class="t m0 x1 h9 y9 ff1 fs4 fc0 sc0 ls0 ws0">The NVIDIA</div><div class="t m0 x5 ha ya ff1 fs0 fc0 sc0 ls0 ws0">&#174;</div><div class="t m0 x6 h9 y9 ff1 fs4 fc0 sc0 ls0 ws0"> Jetson TX2 series System-<span class="ls6">on</span>-Module (SOM) redefines possibility; a combination of performance, power </div><div class="t m0 x1 h9 yb ff1 fs4 fc0 sc0 ls0 ws0">efficiency, integrated deep learning ca<span class="_ _0"></span>pabilities <span class="ls6">and </span>rich I/O r<span class="_ _1"></span>emove the barriers to a new generation of products. The Jetson </div><div class="t m0 x1 h9 yc ff1 fs4 fc0 sc0 ls0 ws0">TX2 is ideal for many applications including<span class="_ _0"></span> (but not limited to): Intelligent Video Analytics (<span class="_ _1"></span>IVA), Drones, Robotics, Gaming </div><div class="t m0 x1 h9 yd ff1 fs4 fc0 sc0 ls0 ws0">Devices, Virtual Reality (VR), Augmented Reality (AR) and Portable Medical Devices.<span class="_ _0"></span> Superior performance, robust design </div><div class="t m0 x1 h9 ye ff1 fs4 fc0 sc0 ls0 ws0">and reduced complexity in system integration results in more advanced products getting to ma<span class="_ _0"></span>rket faster. </div><div class="t m0 x1 h9 yf ff1 fs4 fc0 sc0 ls0 ws0">T<span class="ls6">he </span>Jetson TX2 series module integrates: </div><div class="t m0 x7 hb y10 ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">256 core NVIDIA<span class="_ _4"></span> Pascal GPU<span class="ff1">. Fully supports all <span class="_ _1"></span>modern graphi<span class="_ _1"></span>cs APIs, unified<span class="_ _1"></span> shaders and i<span class="_ _1"></span>s GPU compu<span class="_ _1"></span>te capable. The G<span class="_ _4"></span>PU</span></span></div><div class="t m0 x8 hc y11 ff1 fs6 fc0 sc0 ls0 ws0">supports all the <span class="_ _1"></span>same featur<span class="_ _1"></span>es as discrete NVIDIA G<span class="_ _1"></span>PUs, including<span class="_ _1"></span> ex<span class="_ _1"></span>tensive compute API<span class="_ _1"></span>s and libraries in<span class="_ _1"></span>cluding CUD<span class="_ _1"></span>A. Highly</div><div class="t m0 x8 hc y12 ff1 fs6 fc0 sc0 ls0 ws0">power opti<span class="_ _1"></span>mized for best perfor<span class="_ _4"></span>m<span class="_ _0"></span>ance in e<span class="_ _4"></span>m<span class="_ _0"></span>bedded use <span class="_ _1"></span>cases.</div><div class="t m0 x7 hb y13 ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>RMv8 (64-bit) Multi-Processor <span class="_ _1"></span>CPU Complex<span class="ff1">. Tw<span class="_ _4"></span>o <span class="_ _0"></span>CPU cluster<span class="_ _4"></span>s connected by a high-perfor<span class="_ _4"></span>m<span class="_ _0"></span>ance coherent inter<span class="_ _1"></span>connect fabric</span></span></div><div class="t m0 x8 hc y14 ff1 fs6 fc0 sc0 ls0 ws0">designed by NV<span class="_ _1"></span>IDIA; enables<span class="_ _1"></span> simultaneou<span class="_ _1"></span>s operation of<span class="_ _1"></span> both CPU c<span class="_ _1"></span>lusters for a <span class="_ _1"></span>true heterogen<span class="_ _1"></span>eous multi-processing (HM<span class="_ _1"></span>P)</div><div class="t m0 x8 hb y15 ff1 fs6 fc0 sc0 ls0 ws0">environment. The<span class="_ _1"></span> <span class="ff3">Denver 2 (Dua<span class="_ _1"></span>l-Core)<span class="ff1"> CPU <span class="_ _1"></span>clusters is optimize<span class="_ _1"></span>d for<span class="_ _1"></span> higher single-thread perfor<span class="_ _4"></span>mance; the ARM <span class="ff3">Cortex-A<span class="_ _1"></span>57</span></span></span></div><div class="t m0 x8 hb y16 ff3 fs6 fc0 sc0 ls0 ws0">MPCore (Quad-Core<span class="_ _1"></span>)<span class="ff1"> CPU <span class="_ _1"></span>clusters is better <span class="_ _1"></span>suited for mul<span class="_ _1"></span>ti-threaded applica<span class="_ _1"></span>tions and lighter<span class="_ _1"></span> loads.</span></div><div class="t m0 x7 hb y17 ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>dvanced HD Video Encoder<span class="ff1">. R<span class="_ _4"></span>ec<span class="_ _0"></span>ording of 4K<span class="_ _1"></span> ultra-high-definition<span class="_ _1"></span> video at 60fps<span class="_ _1"></span>. Supports H.265 a<span class="_ _4"></span>nd H.264 BP/MP/HP/MVC,</span></span></div><div class="t m0 x8 hc y18 ff1 fs6 fc0 sc0 ls0 ws0">VP9 and VP8 en<span class="_ _4"></span>c<span class="_ _0"></span>oding.</div><div class="t m0 x7 hb y19 ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>dvanced HD Video Decoder<span class="ff1">. <span class="_ _1"></span>Playback of 4<span class="_ _1"></span>K ultra-high-de<span class="_ _1"></span>finition video at 60<span class="_ _1"></span>fps with up to<span class="_ _1"></span> 12-bit pixels. Suppor<span class="_ _1"></span>ts H.265, H<span class="_ _1"></span>.264,</span></span></div><div class="t m0 x8 hc y1a ff1 fs6 fc0 sc0 ls0 ws0">VP9, VP8 VC-1, MP<span class="_ _4"></span>E<span class="_ _0"></span>G-2, and M<span class="_ _1"></span>PEG-4 video standa<span class="_ _1"></span>rds.</div><div class="t m0 x7 hb y1b ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">Display<span class="_ _1"></span> Controller Subsy<span class="_ _4"></span>stem<span class="ff1">.<span class="_ _0"></span> Two multi-mode (eDP<span class="_ _1"></span>/DP/HDM<span class="_ _1"></span>I) outputs and<span class="_ _1"></span> up to 8-lanes of M<span class="_ _1"></span>IPI-DSI output<span class="_ _1"></span>. Multiple line<span class="_ _1"></span> pixel</span></span></div><div class="t m0 x8 hc y1c ff1 fs6 fc0 sc0 ls0 ws0">storage allows <span class="_ _1"></span>more memory-<span class="_ _1"></span>efficient scaling<span class="_ _1"></span> operations and<span class="_ _1"></span> pixel fe<span class="_ _1"></span>tching. Hardw<span class="_ _4"></span>are display surface rotation is<span class="_ _1"></span> also provide<span class="_ _1"></span>d for</div><div class="t m0 x8 hc y1d ff1 fs6 fc0 sc0 ls0 ws0">bandw<span class="_ _1"></span>idth reduction in mobile app<span class="_ _4"></span>lic<span class="_ _0"></span>ations.</div><div class="t m0 x7 hb y1e ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6 ls7">128<span class="ls0">-bit Memory<span class="_ _4"></span> Controll<span class="_ _0"></span>er<span class="ff1">.128-bit DRAM<span class="_ _1"></span> interfa<span class="_ _1"></span>ce providing high ba<span class="_ _1"></span>ndwidth<span class="_ _1"></span> LPDDR4 and ECC (<span class="ff3">TX2i<span class="_ _1"></span> only<span class="ff1 ls8">) <span class="ls0">support.</span></span></span></span></span></span></div><div class="t m0 x7 hb y1f ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">8GB LPDDR4 an<span class="_ _1"></span>d 32 GB e<span class="_ _1"></span>MMC memory<span class="_ _4"></span> <span class="_ _0"></span><span class="ff1">integrated on the mod<span class="_ _1"></span>ule</span></span></div><div class="t m0 x7 hb y20 ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">1.4Gpix/s A<span class="_ _4"></span>dvanced image signal processing<span class="_ _1"></span><span class="ff1">: Hardw<span class="_ _1"></span>are accelerated<span class="_ _1"></span> still-image and video <span class="_ _1"></span>capture <span class="_ _1"></span>path, with adva<span class="_ _1"></span>nced ISP.</span></span></div><div class="t m0 x7 hb y21 ff6 fs4 fc0 sc0 ls0 ws0">&#9642;<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>udio Processing Engine<span class="ff1">. Audio<span class="_ _4"></span> s<span class="_ _0"></span>ubsyste<span class="_ _1"></span>m enables full har<span class="_ _1"></span>dwar<span class="_ _1"></span>e support for multi-channel aud<span class="_ _1"></span>io over<span class="_ _1"></span> multiple interface<span class="_ _1"></span>s.</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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