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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">JETSON | TX2/TX2i | DATASHEET | 1.0 <span class="ls1">| </span>SU<span class="_ _0"></span>BJECT TO CHANGE <span class="ls1">| </span>COPYRIGHT © 2<span class="_ _0"></span>014 <span class="ff2">–</span> <span class="ls2">201</span>8 NVIDIA CORPORATION. ALL RIGHTS RESERVE<span class="_ _1"></span>D. <span class="_ _2"> </span>1<span class="ff3"> </span></div><div class="c x2 y2 w2 h3"><div class="t m0 x3 h4 y3 ff4 fs1 fc0 sc0 ls0 ws0">DATA SHEET </div><div class="t m0 x3 h5 y4 ff4 fs2 fc1 sc0 ls0 ws0">NVIDIA<span class="_ _3"></span> Jetson <span class="_ _1"></span>T<span class="_ _1"></span>X2 <span class="ls3">/ <span class="_ _1"></span><span class="ls0">TX2i System-<span class="ls4">on</span>-Module<span class="_ _1"></span> </span></span></div><div class="t m0 x3 h6 y5 ff4 fs3 fc1 sc0 ls0 ws0">Pascal GPU + <span class="_ _4"></span>ARMv8 + 8GB LPDD<span class="_ _0"></span>R4 + 32GB eMMC<span class="_ _0"></span><span class="ff5"> </span></div></div><div class="t m0 x1 h7 y6 ff5 fs4 fc0 sc0 ls0 ws0">NVIDIA Jetson Modules: TX2, TX2i </div><div class="t m0 x4 h7 y7 ff5 fs4 fc0 sc0 ls0 ws0">References to T<span class="ls5">X2</span> include (can be read as) TX2i except where explicitly noted. </div><div class="t m0 x1 h8 y8 ff4 fs5 fc0 sc0 ls0 ws0">Description </div><div class="t m0 x1 h9 y9 ff1 fs4 fc0 sc0 ls0 ws0">The NVIDIA</div><div class="t m0 x5 ha ya ff1 fs0 fc0 sc0 ls0 ws0">®</div><div class="t m0 x6 h9 y9 ff1 fs4 fc0 sc0 ls0 ws0"> Jetson TX2 series System-<span class="ls6">on</span>-Module (SOM) redefines possibility; a combination of performance, power </div><div class="t m0 x1 h9 yb ff1 fs4 fc0 sc0 ls0 ws0">efficiency, integrated deep learning ca<span class="_ _0"></span>pabilities <span class="ls6">and </span>rich I/O r<span class="_ _1"></span>emove the barriers to a new generation of products. The Jetson </div><div class="t m0 x1 h9 yc ff1 fs4 fc0 sc0 ls0 ws0">TX2 is ideal for many applications including<span class="_ _0"></span> (but not limited to): Intelligent Video Analytics (<span class="_ _1"></span>IVA), Drones, Robotics, Gaming </div><div class="t m0 x1 h9 yd ff1 fs4 fc0 sc0 ls0 ws0">Devices, Virtual Reality (VR), Augmented Reality (AR) and Portable Medical Devices.<span class="_ _0"></span> Superior performance, robust design </div><div class="t m0 x1 h9 ye ff1 fs4 fc0 sc0 ls0 ws0">and reduced complexity in system integration results in more advanced products getting to ma<span class="_ _0"></span>rket faster. </div><div class="t m0 x1 h9 yf ff1 fs4 fc0 sc0 ls0 ws0">T<span class="ls6">he </span>Jetson TX2 series module integrates: </div><div class="t m0 x7 hb y10 ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">256 core NVIDIA<span class="_ _4"></span> Pascal GPU<span class="ff1">. Fully supports all <span class="_ _1"></span>modern graphi<span class="_ _1"></span>cs APIs, unified<span class="_ _1"></span> shaders and i<span class="_ _1"></span>s GPU compu<span class="_ _1"></span>te capable. The G<span class="_ _4"></span>PU</span></span></div><div class="t m0 x8 hc y11 ff1 fs6 fc0 sc0 ls0 ws0">supports all the <span class="_ _1"></span>same featur<span class="_ _1"></span>es as discrete NVIDIA G<span class="_ _1"></span>PUs, including<span class="_ _1"></span> ex<span class="_ _1"></span>tensive compute API<span class="_ _1"></span>s and libraries in<span class="_ _1"></span>cluding CUD<span class="_ _1"></span>A. Highly</div><div class="t m0 x8 hc y12 ff1 fs6 fc0 sc0 ls0 ws0">power opti<span class="_ _1"></span>mized for best perfor<span class="_ _4"></span>m<span class="_ _0"></span>ance in e<span class="_ _4"></span>m<span class="_ _0"></span>bedded use <span class="_ _1"></span>cases.</div><div class="t m0 x7 hb y13 ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>RMv8 (64-bit) Multi-Processor <span class="_ _1"></span>CPU Complex<span class="ff1">. Tw<span class="_ _4"></span>o <span class="_ _0"></span>CPU cluster<span class="_ _4"></span>s connected by a high-perfor<span class="_ _4"></span>m<span class="_ _0"></span>ance coherent inter<span class="_ _1"></span>connect fabric</span></span></div><div class="t m0 x8 hc y14 ff1 fs6 fc0 sc0 ls0 ws0">designed by NV<span class="_ _1"></span>IDIA; enables<span class="_ _1"></span> simultaneou<span class="_ _1"></span>s operation of<span class="_ _1"></span> both CPU c<span class="_ _1"></span>lusters for a <span class="_ _1"></span>true heterogen<span class="_ _1"></span>eous multi-processing (HM<span class="_ _1"></span>P)</div><div class="t m0 x8 hb y15 ff1 fs6 fc0 sc0 ls0 ws0">environment. The<span class="_ _1"></span> <span class="ff3">Denver 2 (Dua<span class="_ _1"></span>l-Core)<span class="ff1"> CPU <span class="_ _1"></span>clusters is optimize<span class="_ _1"></span>d for<span class="_ _1"></span> higher single-thread perfor<span class="_ _4"></span>mance; the ARM <span class="ff3">Cortex-A<span class="_ _1"></span>57</span></span></span></div><div class="t m0 x8 hb y16 ff3 fs6 fc0 sc0 ls0 ws0">MPCore (Quad-Core<span class="_ _1"></span>)<span class="ff1"> CPU <span class="_ _1"></span>clusters is better <span class="_ _1"></span>suited for mul<span class="_ _1"></span>ti-threaded applica<span class="_ _1"></span>tions and lighter<span class="_ _1"></span> loads.</span></div><div class="t m0 x7 hb y17 ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>dvanced HD Video Encoder<span class="ff1">. R<span class="_ _4"></span>ec<span class="_ _0"></span>ording of 4K<span class="_ _1"></span> ultra-high-definition<span class="_ _1"></span> video at 60fps<span class="_ _1"></span>. Supports H.265 a<span class="_ _4"></span>nd H.264 BP/MP/HP/MVC,</span></span></div><div class="t m0 x8 hc y18 ff1 fs6 fc0 sc0 ls0 ws0">VP9 and VP8 en<span class="_ _4"></span>c<span class="_ _0"></span>oding.</div><div class="t m0 x7 hb y19 ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>dvanced HD Video Decoder<span class="ff1">. <span class="_ _1"></span>Playback of 4<span class="_ _1"></span>K ultra-high-de<span class="_ _1"></span>finition video at 60<span class="_ _1"></span>fps with up to<span class="_ _1"></span> 12-bit pixels. Suppor<span class="_ _1"></span>ts H.265, H<span class="_ _1"></span>.264,</span></span></div><div class="t m0 x8 hc y1a ff1 fs6 fc0 sc0 ls0 ws0">VP9, VP8 VC-1, MP<span class="_ _4"></span>E<span class="_ _0"></span>G-2, and M<span class="_ _1"></span>PEG-4 video standa<span class="_ _1"></span>rds.</div><div class="t m0 x7 hb y1b ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">Display<span class="_ _1"></span> Controller Subsy<span class="_ _4"></span>stem<span class="ff1">.<span class="_ _0"></span> Two multi-mode (eDP<span class="_ _1"></span>/DP/HDM<span class="_ _1"></span>I) outputs and<span class="_ _1"></span> up to 8-lanes of M<span class="_ _1"></span>IPI-DSI output<span class="_ _1"></span>. Multiple line<span class="_ _1"></span> pixel</span></span></div><div class="t m0 x8 hc y1c ff1 fs6 fc0 sc0 ls0 ws0">storage allows <span class="_ _1"></span>more memory-<span class="_ _1"></span>efficient scaling<span class="_ _1"></span> operations and<span class="_ _1"></span> pixel fe<span class="_ _1"></span>tching. Hardw<span class="_ _4"></span>are display surface rotation is<span class="_ _1"></span> also provide<span class="_ _1"></span>d for</div><div class="t m0 x8 hc y1d ff1 fs6 fc0 sc0 ls0 ws0">bandw<span class="_ _1"></span>idth reduction in mobile app<span class="_ _4"></span>lic<span class="_ _0"></span>ations.</div><div class="t m0 x7 hb y1e ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6 ls7">128<span class="ls0">-bit Memory<span class="_ _4"></span> Controll<span class="_ _0"></span>er<span class="ff1">.128-bit DRAM<span class="_ _1"></span> interfa<span class="_ _1"></span>ce providing high ba<span class="_ _1"></span>ndwidth<span class="_ _1"></span> LPDDR4 and ECC (<span class="ff3">TX2i<span class="_ _1"></span> only<span class="ff1 ls8">) <span class="ls0">support.</span></span></span></span></span></span></div><div class="t m0 x7 hb y1f ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">8GB LPDDR4 an<span class="_ _1"></span>d 32 GB e<span class="_ _1"></span>MMC memory<span class="_ _4"></span> <span class="_ _0"></span><span class="ff1">integrated on the mod<span class="_ _1"></span>ule</span></span></div><div class="t m0 x7 hb y20 ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">1.4Gpix/s A<span class="_ _4"></span>dvanced image signal processing<span class="_ _1"></span><span class="ff1">: Hardw<span class="_ _1"></span>are accelerated<span class="_ _1"></span> still-image and video <span class="_ _1"></span>capture <span class="_ _1"></span>path, with adva<span class="_ _1"></span>nced ISP.</span></span></div><div class="t m0 x7 hb y21 ff6 fs4 fc0 sc0 ls0 ws0">▪<span class="_ _5"> </span><span class="ff3 fs6">A<span class="_ _1"></span>udio Processing Engine<span class="ff1">. Audio<span class="_ _4"></span> s<span class="_ _0"></span>ubsyste<span class="_ _1"></span>m enables full har<span class="_ _1"></span>dwar<span class="_ _1"></span>e support for multi-channel aud<span class="_ _1"></span>io over<span class="_ _1"></span> multiple interface<span class="_ _1"></span>s.</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/bg2.jpg"><div class="c x0 y22 w3 h0"><div class="t m0 x9 hd y23 ff1 fs7 fc0 sc0 ls0 ws0">Jetson TX2 / T<span class="_ _0"></span>X2i System-<span class="ls9">on</span>-Module </div><div class="t m0 xa hd y24 ff1 fs7 fc0 sc0 ls0 ws0">Pascal GPU + AR<span class="_ _0"></span>Mv8 + 8GB LPD<span class="_ _0"></span>DR4 + 32GB eMMC<span class="_ _0"></span> + W<span class="_ _0"></span>LAN/BT </div><div class="t m0 x1 ha y1 ff1 fs0 fc0 sc0 ls0 ws0">JETSON | TX2/TX2i | DATASHEET | 1.0 <span class="ls1">| </span>SU<span class="_ _0"></span>BJECT TO CHANGE <span class="ls1">| </span>COPYRIGHT © 2<span class="_ _0"></span>014 <span class="ff2">–</span> <span class="ls2">201</span>8 NVIDIA CORPORATION. ALL RIGHTS RESERVE<span class="_ _1"></span>D. <span class="_ _2"> </span>2 </div></div><div class="c xb y25 w4 he"><div class="t m0 xc hf y26 ff1 fs0 fc0 sc0 ls0 ws0"><span class="fc2 sc0">></span><span class="fc2 sc0"> </span><span class="_ _6"> </span><span class="ff3 fs7">Description<span class="_ _0"></span> </span></div></div><div class="c xd y27 w5 h10"><div class="t m0 xe hf y28 ff3 fs7 fc0 sc0 ls0 ws0">Jetson TX2 Serie<span class="_ _0"></span>s System-<span class="lsa">on</span>-Module<span class="ff7 fs4">*<span class="_ _0"></span></span> </div></div><div class="c xd y25 w6 h10"><div class="t m0 xf hf y29 ff3 fs7 fc0 sc0 ls0 ws0">TX2 </div></div><div class="c x10 y25 w7 h10"><div class="t m0 x11 hf y29 ff3 fs7 fc0 sc0 ls0 ws0">TX2i </div></div><div class="c xb y2a w8 h11"><div class="t m0 x12 hf y2b ff3 fs7 fc0 sc0 ls0 ws0">Pascal GPU </div><div class="t m0 x13 h12 y2c ff8 fs0 fc0 sc0 ls0 ws0">◊</div><div class="t m0 x14 hf y2b ff3 fs7 fc0 sc0 ls0 ws0"> </div></div><div class="c xb y2d w8 h13"><div class="t m0 x12 ha y2e ff1 fs0 fc0 sc0 ls2 ws0">256<span class="ls0">-core GPU | End-<span class="lsb">to</span>-end lossless compression | Tile Caching | OpenGL</span></div><div class="t m0 x15 h14 y2f ff1 fs8 fc0 sc0 ls0 ws0">®</div><div class="t m0 x16 ha y2e ff1 fs0 fc0 sc0 ls0 ws0"> <span class="ls2">4.</span>6 | OpenGL</div><div class="t m0 x17 h14 y2f ff1 fs8 fc0 sc0 ls0 ws0">®</div><div class="t m0 x18 ha y2e ff1 fs0 fc0 sc0 ls0 ws0"> <span class="lsc">ES</span> 3.2 | Vulkan</div><div class="t m0 x19 h14 y2f ff1 fs8 fc0 sc0 ls0 ws0">®</div><div class="t m0 x1a ha y2e ff1 fs0 fc0 sc0 ls0 ws0"> 1.0 | CUDA</div><div class="t m0 x1b h14 y2f ff1 fs8 fc0 sc0 lsd ws0">® </div><div class="t m0 x1c ha y2e ff1 fs0 fc0 sc0 ls0 ws0">9.0 </div></div><div class="c xb y30 w4 h15"><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">Maximum Operating Frequency </div></div><div class="c xd y30 w5 h15"><div class="t m0 x1d ha y31 ff1 fs0 fc0 sc0 ls0 ws0">1.12GHz </div></div><div class="c xb y32 w8 h13"><div class="t m0 x12 hf y33 ff3 fs7 fc0 sc0 ls0 ws0">CPU Complex </div><div class="t m0 x1e h16 y34 ff2 fs0 fc0 sc0 ls0 ws0">‡</div><div class="t m0 x1f ha y33 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c xb y35 w8 h17"><div class="t m0 x12 h9 y36 ff1 fs0 fc0 sc0 ls0 ws0">ARMv8 (64-bit) heterogeneous multi-processing (HMP) CPU architecture;<span class="fs4"> </span>two CPU clusters (6 pro<span class="_ _0"></span>cessor cores) connected by a high-perform<span class="_ _1"></span>ance coherent interconnect fabri<span class="_ _0"></span>c. </div><div class="t m0 x20 ha y37 ff1 fs0 fc0 sc0 ls0 ws0">NVIDIA Denver 2 (Dual-Core) Processor: L1 Cache: 128KB L1 instruction cache (I-cache) per core; 64KB L1 data cache (D-cache) per core | L2 Unified Cache: 2MB </div><div class="t m0 x20 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">ARM</div><div class="t m0 x21 h14 y39 ff1 fs8 fc0 sc0 lsd ws0">® </div><div class="t m0 x22 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">Cortex</div><div class="t m0 x23 h14 y39 ff1 fs8 fc0 sc0 ls0 ws0">®</div><div class="t m0 x1 ha y38 ff1 fs0 fc0 sc0 ls0 ws0"> -A57 MPCore (Quad-Core) Processor:<span class="_ _0"></span> L1 Cache: 48KB L1 instruction cache (I-cache) per core; 32KB L1 data cache (D-cache) per core | L2 Unified Cache: 2MB </div></div><div class="c xb y3a w4 h18"><div class="t m0 x12 ha y3b ff1 fs0 fc0 sc0 ls0 ws0">Maximum Operating Frequency per Core </div><div class="t m0 x20 ha y3c ff1 fs0 fc0 sc0 ls0 ws0">NVIDIA Denver 2 </div><div class="t m0 x20 ha y3d ff1 fs0 fc0 sc0 ls0 ws0">ARM Cortex-A57 </div></div><div class="c xd y3a w6 h18"><div class="t m0 x24 ha y3e ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x25 ha y3f ff1 fs0 fc0 sc0 ls0 ws0">2.0GHz </div><div class="t m0 x25 ha y40 ff1 fs0 fc0 sc0 ls0 ws0">2.0GHz </div></div><div class="c x10 y3a w7 h18"><div class="t m0 x24 ha y41 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x26 ha y42 ff1 fs0 fc0 sc0 ls0 ws0">1.95GHz </div><div class="t m0 x26 ha y33 ff1 fs0 fc0 sc0 ls0 ws0">1.92GHz </div></div><div class="c xb y43 w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">HD Video & JPEG <span class="_ _0"></span> </div></div><div class="c xb y45 w4 h1a"><div class="t m0 x12 h2 y46 ff3 fs0 fc0 sc0 ls0 ws0">Video Decode(Number of Streams Supported): </div><div class="t m0 x20 ha y47 ff1 fs0 fc0 sc0 ls0 ws0">H.265 </div><div class="t m0 x22 h1b y48 ff3 fs9 fc0 sc0 ls0 ws0">(<span class="ff8">†</span>)</div><div class="t m0 x27 ha y47 ff1 fs0 fc0 sc0 ls0 ws0">: Main 10, Main 8 </div><div class="t m0 x20 ha y49 ff1 fs0 fc0 sc0 ls0 ws0">H.265 </div><div class="t m0 x22 h1b y4a ff3 fs9 fc0 sc0 ls0 ws0">(<span class="ff8">†</span>)</div><div class="t m0 x27 ha y49 ff1 fs0 fc0 sc0 ls0 ws0">: Main 444 </div><div class="t m0 x20 ha y4b ff1 fs0 fc0 sc0 ls0 ws0">H.264 </div><div class="t m0 x22 h1b y4c ff3 fs9 fc0 sc0 ls0 ws0">(<span class="ff8">†</span>)</div><div class="t m0 x27 ha y4b ff1 fs0 fc0 sc0 lsb ws0">: <span class="ls0">Baseline, Main, High </span></div><div class="t m0 x20 ha y4d ff1 fs0 fc0 sc0 ls0 ws0">H.264 </div><div class="t m0 x22 h1b y4e ff3 fs9 fc0 sc0 ls0 ws0">(<span class="ff8">†</span>)</div><div class="t m0 x27 ha y4d ff1 fs0 fc0 sc0 lsb ws0">: <span class="ls0">MVC Stereo (per view) </span></div><div class="t m0 x20 ha y4f ff1 fs0 fc0 sc0 lsc ws0">VP9<span class="ls0"> </span></div><div class="t m0 x21 h1b y50 ff3 fs9 fc0 sc0 ls0 ws0">(<span class="ff8">†</span>)</div><div class="t m0 x28 ha y4f ff1 fs0 fc0 sc0 lsb ws0">: <span class="ls0">Profile 0 (8-bit) and 2 (10 and 12-bit) </span></div><div class="t m0 x20 ha y51 ff1 fs0 fc0 sc0 lsc ws0">VP8<span class="ls0">: All </span></div><div class="t m0 x20 ha y52 ff1 fs0 fc0 sc0 ls0 ws0">MPEG1/2: Main </div><div class="t m0 x20 ha y53 ff1 fs0 fc0 sc0 ls0 ws0">MPEG4: SP/AP </div><div class="t m0 x20 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">VC1: SP/MP/AP </div></div><div class="c xd y45 w5 h1a"><div class="t m0 x29 ha y46 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2a ha y55 ff1 fs0 fc0 sc0 ls0 ws0">(2x) 2160p60 | (4x) 2160p30 | (7x) 1080p60 | (14x) 1080p30</div><div class="t m0 x18 h14 y56 ff1 fs8 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2b ha y57 ff1 fs0 fc0 sc0 ls0 ws0">2160p60 | (2x) 2160p30 | (3x) 1080p60 | (7x) 1080p30 </div><div class="t m0 x2a ha y58 ff1 fs0 fc0 sc0 ls0 ws0">(2x) 2160p60 | (4x) 2160p30 | (7x) 1080p60 | (14x) 1080p30 </div><div class="t m0 x2c ha y59 ff1 fs0 fc0 sc0 ls2 ws0">2160p60 | <span class="ls0">2160p30 |<span class="_ _1"></span> 1080p60 <span class="ls1">| <span class="ls2">1080p30</span></span> </span></div><div class="t m0 x2a ha y5a ff1 fs0 fc0 sc0 ls0 ws0">(2x) 2160p60 | (4x) 2160p30 | (7x) 1080p60 | (14x) 1080p30 </div><div class="t m0 x2b ha y5b ff1 fs0 fc0 sc0 ls2 ws0">2160p60 | (2x<span class="_ _1"></span>) 2160p30 |<span class="_ _1"></span> (4x) 1080p6<span class="ls0">0 |<span class="_ _4"></span> (<span class="_ _0"></span>8x) 1080p30 </span></div><div class="t m0 x2b ha y5c ff1 fs0 fc0 sc0 ls2 ws0">2160p60 | (2x<span class="_ _1"></span>) 2160p30 |<span class="_ _1"></span> (4x) 1080p60<span class="_ _1"></span> | (8<span class="ls0">x<span class="_ _1"></span>) 1080p30 </span></div><div class="t m0 x2d ha y5d ff1 fs0 fc0 sc0 ls0 ws0">(4x) 1080p60 | (8x) 1080p30 </div><div class="t m0 x2d ha y5e ff1 fs0 fc0 sc0 ls0 ws0">(2x) 1080p60 | (4x) 1080p30 </div></div><div class="c xb y5f w4 h1c"><div class="t m0 x12 h2 y60 ff3 fs0 fc0 sc0 ls0 ws0">Video Encode (Number of Streams Supported): </div><div class="t m0 x20 ha y51 ff1 fs0 fc0 sc0 ls0 ws0">H.265 </div><div class="t m0 x20 ha y52 ff1 fs0 fc0 sc0 ls0 ws0">H.264: Baseline, Main, High </div><div class="t m0 x20 ha y53 ff1 fs0 fc0 sc0 ls0 ws0">WEBM VP9 </div><div class="t m0 x20 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">WEBM VP8 </div></div><div class="c xd y5f w5 h1c"><div class="t m0 x29 ha y60 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2b ha y51 ff1 fs0 fc0 sc0 ls2 ws0">2160p60 | (3x<span class="_ _1"></span>) 2160p30 |<span class="_ _1"></span> (4x)1<span class="ls0">080p60 | (8x) 1080P30 </span></div><div class="t m0 x2e ha y52 ff1 fs0 fc0 sc0 ls2 ws0">2160p60 | (3x<span class="_ _1"></span>) 2160p30 |<span class="_ _1"></span> (7x) 1080p60<span class="_ _1"></span> | (14<span class="ls0">x<span class="_ _1"></span>) 1080p30 </span></div><div class="t m0 x2f ha y53 ff1 fs0 fc0 sc0 ls2 ws0">2160p30 | (3x<span class="_ _1"></span>) 1080p60 |<span class="_ _1"></span> (7<span class="ls0">x) 1080p30 </span></div><div class="t m0 x2f ha y54 ff1 fs0 fc0 sc0 ls2 ws0">2160p30 | (3<span class="ls0">x<span class="_ _1"></span>) 1080p60 | (6x) 1080p30 </span></div></div><div class="c xb y61 w4 h15"><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">JPEG (Decode & Encode) </div></div><div class="c xd y61 w5 h15"><div class="t m0 x30 ha y31 ff1 fs0 fc0 sc0 ls2 ws0">600<span class="ls0"> MP/sec </span></div></div><div class="c xb y62 w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Audio Subs<span class="_ _0"></span>ystem </div></div><div class="c xb y63 w8 h1d"><div class="t m0 x12 ha y64 ff1 fs0 fc0 sc0 ls0 ws0">Industry-standard High Definition Audio (HDA) controller provides a multi-chan<span class="_ _0"></span>nel audio path to the HDMI interface | 4 x I2S | DM<span class="_ _1"></span>IC | DSPK <span class="ls1">| <span class="_ _0"></span><span class="ls2">2 </span>x </span>I <span class="_ _0"></span>and Q baseband data channels | </div><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">PDM in/out </div></div><div class="c xb y65 w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Display Controller<span class="_ _0"></span> Subsystem<span class="_ _0"></span> </div></div><div class="c xb y66 w8 h15"><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">Support for DSI, HDMI, DP and eDP | Two multi-mode eDP/DP/HDMI outputs. </div></div><div class="c xb y67 w8 h1e"><div class="t m0 x12 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">Captive Panel </div></div><div class="c xb y69 w9 h1e"><div class="t m0 x12 ha y68 ff1 fs0 fc0 sc0 lsb ws0"> <span class="ls0">MIPI-DSI (1.5Gbps/lane) </span></div></div><div class="c x31 y69 wa h1e"><div class="t m0 x23 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">Max Resolution </div></div><div class="c xd y69 w5 h1e"><div class="t m0 x32 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">Support for Single x4 or Dual x4 links | 2560x<span class="ls2">160</span>0 at 60<span class="lse">Hz</span> </div></div><div class="c xb y6a w9 h1f"><div class="t m0 x12 ha y38 ff1 fs0 fc0 sc0 lsb ws0"> <span class="ls0">eDP 1.4 (HBR2 5.4Gbps) </span></div></div><div class="c x31 y6a wa h1f"><div class="t m0 x23 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">Max Resolution </div></div><div class="c xd y6a w5 h1f"><div class="t m0 x33 ha y38 ff1 fs0 fc0 sc0 ls2 ws0">3840<span class="ls0">x2160 at 60Hz </span></div></div><div class="c xb y6b w8 h1f"><div class="t m0 x12 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">External Display </div></div><div class="c xb y6c w9 h1f"><div class="t m0 x12 ha y38 ff1 fs0 fc0 sc0 lsb ws0"> <span class="ls0">HDMI 2.0a/b (6Gbps) </span></div></div><div class="c x31 y6c wa h1f"><div class="t m0 x23 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">Max Resolution </div></div><div class="c xd y6c w5 h1f"><div class="t m0 x33 ha y38 ff1 fs0 fc0 sc0 ls2 ws0">3840<span class="ls0">x2160 at 60<span class="lse">Hz</span> </span></div></div><div class="c xb y6d w9 h1e"><div class="t m0 x12 ha y68 ff1 fs0 fc0 sc0 lsb ws0"> <span class="ls0">DP 1.2a (HBR2 5.4 Gbps) </span></div></div><div class="c x31 y6d wa h1e"><div class="t m0 x23 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">Max Resolution </div></div><div class="c xd y6d w5 h1e"><div class="t m0 x33 ha y68 ff1 fs0 fc0 sc0 ls2 ws0">3840<span class="ls0">x2160 at 60<span class="lse">Hz</span> </span></div></div><div class="c xb y6e w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Imaging System<span class="_ _0"></span><span class="ff1"> </span></div></div><div class="c xb y6f w8 h20"><div class="t m0 x12 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">Dedicated RAW to YUV processing engine process up to 1.4Gpix/s |<span class="_ _1"></span> <span class="_ _0"></span>MIPI CSI 2.0 up to 2.5Gbps (per lane) <span class="ls1">| <span class="_ _0"></span></span>Support for x4 and x2 configurations (up to 3 x4-l<span class="_ _0"></span>ane or 6 x2-lane cameras) </div></div><div class="c xb y70 w8 h21"><div class="t m0 x12 hf y71 ff3 fs7 fc0 sc0 ls0 ws0">Clocks </div></div><div class="c xb y72 w8 h22"><div class="t m0 x12 ha y44 ff1 fs0 fc0 sc0 ls0 ws0">System clock: 38.4 MHz | Sleep clock: 32.768 KHz | Dynamic clock scaling and clock source selection </div></div><div class="c xb y73 w8 h21"><div class="t m0 x12 hf y71 ff3 fs7 fc0 sc0 ls0 ws0">Boot Sources<span class="_ _0"></span> </div></div><div class="c xb y74 w8 h23"><div class="t m0 x12 ha y44 ff1 fs0 fc0 sc0 ls0 ws0">Internal eMMC and USB (recovery mode) </div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/bg3.jpg"><div class="c x0 y22 w3 h0"><div class="t m0 x9 hd y23 ff1 fs7 fc0 sc0 ls0 ws0">Jetson TX2 / T<span class="_ _0"></span>X2i System-<span class="ls9">on</span>-Module </div><div class="t m0 xa hd y24 ff1 fs7 fc0 sc0 ls0 ws0">Pascal GPU + AR<span class="_ _0"></span>Mv8 + 8GB LPD<span class="_ _0"></span>DR4 + 32GB eMMC<span class="_ _0"></span> + W<span class="_ _0"></span>LAN/BT </div><div class="t m0 x1 ha y1 ff1 fs0 fc0 sc0 ls0 ws0">JETSON | TX2/TX2i | DATASHEET | 1.0 <span class="ls1">| </span>SU<span class="_ _0"></span>BJECT TO CHANGE <span class="ls1">| </span>COPYRIGHT © 2<span class="_ _0"></span>014 <span class="ff2">–</span> <span class="ls2">201</span>8 NVIDIA CORPORATION. ALL RIGHTS RESERVE<span class="_ _1"></span>D. <span class="_ _2"> </span>3 </div></div><div class="c xb y25 w4 he"><div class="t m0 xc hf y26 ff1 fs0 fc0 sc0 ls0 ws0"><span class="fc2 sc0">></span><span class="fc2 sc0"> </span><span class="_ _6"> </span><span class="ff3 fs7">Description<span class="_ _0"></span> </span></div></div><div class="c xd y27 w5 h10"><div class="t m0 xe hf y28 ff3 fs7 fc0 sc0 ls0 ws0">Jetson TX2 Serie<span class="_ _0"></span>s System-<span class="lsa">on</span>-Module<span class="ff7 fs4">*<span class="_ _0"></span></span> </div></div><div class="c xd y25 w6 h10"><div class="t m0 xf hf y29 ff3 fs7 fc0 sc0 ls0 ws0">TX2 </div></div><div class="c x10 y25 w7 h10"><div class="t m0 x11 hf y29 ff3 fs7 fc0 sc0 ls0 ws0">TX2i </div></div><div class="c xb y75 w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Security </div></div><div class="c xb y76 w8 h24"><div class="t m0 x12 ha y77 ff1 fs0 fc0 sc0 ls0 ws0">Secure memory with video protection region for protection of interm<span class="_ _1"></span>ediate results | Configurable secur<span class="_ _7"></span>e DRAM regions for code and data protection |<span class="_ _1"></span> Hardware acceleration for AES </div><div class="t m0 x12 ha y78 ff1 fs0 fc0 sc0 ls0 ws0">128/192/256 encryption and decryption to be used for secure boot and m<span class="_ _1"></span>ultimedia Digital Rights Management (DRM) | Hardware ac<span class="_ _0"></span>ce<span class="_ _0"></span>leration for AES CMAC, SHA-1<span class="lsb">, </span>SHA-<span class="ls2">256</span>, SHA-</div><div class="t m0 x12 ha y37 ff1 fs0 fc0 sc0 ls2 ws0">384,<span class="ls0"> </span>and <span class="ls0">S<span class="lse">HA</span>-512 algorithm<span class="_ _1"></span>s | 2048-bit RSA HW for PKC boot| HW Random number generator (RNG) SP800<span class="_ _0"></span>-90 | TrustZone technology support for DRAM, peripherals <span class="ls1">| </span>SE/TSEC with </span></div><div class="t m0 x12 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">side channel counter-measures for AES | R<span class="lsf">SA</span>-3096 and ECC-512/521 supported via PKA </div></div><div class="c xb y79 w8 h25"><div class="t m0 x12 hf y71 ff3 fs7 fc0 sc0 ls0 ws0">Memory </div><div class="t m0 x34 h26 y7a ff8 fs9 fc0 sc0 ls0 ws0">††</div><div class="t m0 x35 hf y71 ff3 fs7 fc0 sc0 ls0 ws0"> </div></div><div class="c xb y7b w8 h1f"><div class="t m0 x12 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">1<span class="ls2">28</span>-bit DRAM interface | Secure External Memory Access Using TrustZone Technology | System<span class="_ _4"></span> <span class="_ _0"></span>MMU<span class="_ _0"></span> | ECC (enabled by software for TX2i only) </div></div><div class="c xb y7c w4 h1f"><div class="t m0 x12 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">Memory Type </div></div><div class="c xd y7c w5 h1f"><div class="t m0 x36 ha y38 ff1 fs0 fc0 sc0 ls0 ws0">4ch x 32-bit LP<span class="lse">DDR</span>4 </div></div><div class="c xb y7d w4 h1e"><div class="t m0 x12 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">Maximum Memory Bus Frequency (up to) </div></div><div class="c xd y7d w6 h1e"><div class="t m0 x7 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">1<span class="ls2">866</span>MHz </div></div><div class="c x10 y7d w7 h1e"><div class="t m0 x7 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">1600MHz </div></div><div class="c xb y7e w4 h1e"><div class="t m0 x12 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">Memory Capacity </div></div><div class="c xd y7e w5 h1e"><div class="t m0 x37 ha y68 ff1 fs0 fc0 sc0 ls0 ws0">8GB </div></div><div class="c xb y7f w8 h27"><div class="t m0 x12 hf y80 ff3 fs7 fc0 sc0 ls0 ws0">Storage </div></div><div class="c xb y81 w8 h28"><div class="t m0 x12 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">eMMC 5.1 Flash Storage </div></div><div class="c xb y83 w4 h28"><div class="t m0 x20 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Bus Width </div></div><div class="c xd y83 w5 h28"><div class="t m0 x37 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">8-bit </div></div><div class="c xb y84 w4 h28"><div class="t m0 x20 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Maximum Bus Frequency </div></div><div class="c xd y84 w5 h28"><div class="t m0 x38 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">200MHz (HS400) </div></div><div class="c xb y85 w4 h29"><div class="t m0 x20 ha y86 ff1 fs0 fc0 sc0 ls0 ws0">Storage Capacity </div></div><div class="c xd y85 w5 h29"><div class="t m0 x39 ha y86 ff1 fs0 fc0 sc0 ls0 ws0">32GB </div></div><div class="c xb y87 w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Connectivity (TX<span class="_ _0"></span>2 only) </div></div><div class="c xb y88 w8 h29"><div class="t m0 x12 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">WLAN </div></div><div class="c xb y89 w4 h29"><div class="t m0 x20 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Radio type </div></div><div class="c xd y89 w6 h29"><div class="t m0 x3a ha y82 ff1 fs0 fc0 sc0 ls0 ws0">IEEE 802.11a/b/g/n/ac dual-band 2x2 MIMO </div></div><div class="c x10 y89 w7 h29"><div class="t m0 x32 ha y82 ff2 fs0 fc0 sc0 ls0 ws0">–<span class="ff1"> </span></div></div><div class="c xb y8a w4 h29"><div class="t m0 x20 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Maximum transfer rate </div></div><div class="c xd y8a w6 h29"><div class="t m0 x3b ha y82 ff1 fs0 fc0 sc0 ls0 ws0">866.7Mbps </div></div><div class="c x10 y8a w7 h29"><div class="t m0 x32 ha y82 ff2 fs0 fc0 sc0 ls0 ws0">–<span class="ff1"> </span></div></div><div class="c xb y8b w8 h29"><div class="t m0 x12 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Bluetooth </div></div><div class="c xb y8c w4 h28"><div class="t m0 x20 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Version level </div></div><div class="c xd y8c w6 h28"><div class="t m0 x3c ha y82 ff1 fs0 fc0 sc0 ls0 ws0">4.1 </div></div><div class="c x10 y8c w7 h28"><div class="t m0 x32 ha y82 ff2 fs0 fc0 sc0 ls0 ws0">–<span class="ff1"> </span></div></div><div class="c xb y8d w4 h28"><div class="t m0 x20 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">Maximum transfer rate </div></div><div class="c xd y8d w6 h28"><div class="t m0 x3d ha y82 ff1 fs0 fc0 sc0 ls0 ws0">3MB/s </div></div><div class="c x10 y8d w7 h28"><div class="t m0 x32 ha y82 ff2 fs0 fc0 sc0 ls0 ws0">–<span class="ff1"> </span></div></div><div class="c xb y8e w8 h27"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Networking<span class="_ _0"></span> </div></div><div class="c xb y8f w8 h29"><div class="t m0 x12 ha y82 ff1 fs0 fc0 sc0 ls0 ws0">10/100/1000 BASE-T Ethernet | IEEE 802.3u Media Access Controller (MAC) <span class="ls1">| </span>E<span class="_ _0"></span>mbedded memory </div></div><div class="c xb y90 w8 h2a"><div class="t m0 x12 hf y91 ff3 fs7 fc0 sc0 ls0 ws0">Peripheral Interfac<span class="_ _0"></span>es </div><div class="t m0 x3d h2b y92 ff9 fs9 fc0 sc0 ls0 ws0">∆</div><div class="t m0 x3e hf y91 ff3 fs7 fc0 sc0 ls0 ws0"> </div></div><div class="c xb y93 w8 h2c"><div class="t m0 x12 ha y94 ff1 fs0 fc0 sc0 ls0 ws0">XHCI host controller with integrated PHY<span class="lsb">: </span>(up to) 3 x USB 3.0<span class="lsb">, </span>3 x USB 2.0 <span class="ls1">| </span>USB 3.0 devi<span class="_ _0"></span>ce controller with integrated PHY | 5-lane PCIe: two x1 and one x4 controllers | SATA (1 port) | </div><div class="t m0 x12 h2 y37 ff1 fs0 fc0 sc0 ls0 ws0">SD/MMC controller (supporting eMMC 5.1, SD 4.0, SDHOST 4.0 and SDIO 3.0)<span class="lsb">: </span><span class="ff3">1 x SD/SDIO at connector (TX2)</span>,<span class="ff3"> 2 x SD/SDIO at connector (TX2i)</span> <span class="_ _0"></span><span class="ls1">| </span>5 x UART | 3 x SPI | 8 x I</div><div class="t m0 x3f h14 y95 ff1 fs8 fc0 sc0 ls0 ws0">2</div><div class="t m0 x40 ha y37 ff1 fs0 fc0 sc0 ls0 ws0">C | </div><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">2 x CAN | 4 x I2S: support I</div><div class="t m0 x11 h14 y92 ff1 fs8 fc0 sc0 ls0 ws0">2</div><div class="t m0 x3e ha y31 ff1 fs0 fc0 sc0 ls0 ws0">S, RJM, LJM, PCM, TDM (multi-slot mode) | GPIOs </div></div><div class="c xb y96 w8 h2d"><div class="t m0 x12 hf y97 ff3 fs7 fc0 sc0 ls0 ws0">Operating Req<span class="_ _0"></span>uirements </div><div class="t m0 x41 h2e y98 ff6 fs9 fc0 sc1 ls0 ws0"></div><div class="t m0 x2e hf y97 ff3 fs7 fc0 sc0 ls0 ws0"> </div></div><div class="c xb y99 w4 h15"><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">Temperature Range </div></div><div class="c xd y99 w6 h15"><div class="t m0 x3b ha y31 ff1 fs0 fc0 sc0 ls0 ws0">-25C <span class="ff2">–</span> 80C </div></div><div class="c x10 y99 w7 h15"><div class="t m0 x42 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">-40C to 85C </div></div><div class="c xb y9a w4 h15"><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">Module Power </div></div><div class="c xd y9a w6 h15"><div class="t m0 x43 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">7.5W (Max-Q) / 15W (Max-<span class="lsc">P)</span> </div></div><div class="c x10 y9a w7 h15"><div class="t m0 x13 ha y31 ff1 fs0 fc0 sc0 ls2 ws0">10<span class="ls0">W (Max-Q) / </span>20<span class="ls0">W (Max-<span class="lsc">P)</span> </span></div></div><div class="c xb y9b w4 h20"><div class="t m0 x12 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">Power Input </div></div><div class="c xd y9b w6 h20"><div class="t m0 x44 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">5.5V <span class="ff2">–</span> 19.6V </div></div><div class="c x10 y9b w7 h20"><div class="t m0 x44 ha y54 ff1 fs0 fc0 sc0 ls0 ws0">9.0V <span class="ff2">–</span> <span class="ls2">19.</span>6V </div></div><div class="c xb y9c w8 h19"><div class="t m0 x12 hf y44 ff3 fs7 fc0 sc0 ls0 ws0">Applications<span class="_ _0"></span> </div></div><div class="c xb y9d w8 h2f"><div class="t m0 x12 ha y31 ff1 fs0 fc0 sc0 ls0 ws0">Intelligent Video Analytics, Drones, Robotics, Industrial automation, Gaming, and more. </div></div><div class="c x0 y22 w3 h0"><div class="t m0 x1 h30 y9e ff5 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3e h31 y9f ffa fs7 fc0 sc0 ls0 ws0">*</div><div class="t m0 x32 h32 ya0 ff1 fs9 fc0 sc0 ls0 ws0"> </div><div class="t m0 x8 ha y9f ff1 fs0 fc0 sc0 ls0 ws0">Refer to the software release feature list for current software support. </div><div class="t m0 x3e h12 ya1 ff8 fs0 fc0 sc0 ls0 ws0">◊</div><div class="t m0 x32 h2b ya2 ff4 fs9 fc0 sc0 ls0 ws0"> </div><div class="t m0 x8 ha ya1 ff1 fs0 fc0 sc0 ls0 ws0">GPU Maximum Operating Frequency: 1.3GHz supported in boost mode for Jetson TX2 and 1.23GHz for Jetson TX2i </div><div class="t m0 x45 ha ya3 ff1 fs0 fc0 sc0 ls0 ws0">Product is based on a published Khronos Specification and is expected to pass the Khronos Conform<span class="_ _4"></span>a<span class="_ _0"></span>nce Process. Current con<span class="_ _7"></span>formance status can be found at </div><div class="t m0 x45 ha ya4 ff1 fs0 fc0 sc0 ls0 ws0">www.khronos.org/conformance. </div><div class="t m0 x3e h30 ya5 ff9 fs0 fc0 sc0 ls0 ws0">‡</div><div class="t m0 x46 h2b ya6 ff4 fs9 fc0 sc0 ls0 ws0"> </div><div class="t m0 x8 ha ya5 ff1 fs0 fc0 sc0 ls0 ws0">CPU Maximum Operating Frequency: 1-4 core = up to 2.0GHz; greater than 4-core = up to 1.4GHz </div><div class="t m0 x3e ha ya7 ff9 fs0 fc0 sc0 ls0 ws0">(†)<span class="ff1"> <span class="_ _8"> </span>For max supported number of instances<span class="lsb">: </span>bitrate not to exceed 15 Mbps per HD stream (i.e., <span class="ls2">1080p30</span>), overall effective bitrate is less than or equal to 240 Mbps </span></div><div class="t m0 x3e h33 ya8 ff9 fs0 fc0 sc0 ls2 ws0">††<span class="ff1 ls0"> <span class="_ _9"> </span>Dependent on-board layout. Refer to <span class="ffb">Jetson TX2/TX2i OEM Product Design Guide</span> for layout guidelines. </span></div><div class="t m0 x3e h33 ya9 ff9 fs0 fc0 sc0 ls0 ws0">∆<span class="ff1"> <span class="_ _a"> </span>Refer to <span class="ffb">Jetson TX2/TX2i OEM Product Design Guide</span> <span class="ls2">and </span><span class="ffb">Parker Series SoC Technical Reference Manual</span> to determine which peripheral interface options can be simultaneously </span></div><div class="t m0 x45 ha yaa ff1 fs0 fc0 sc0 ls0 ws0">exposed. </div><div class="t m0 x3e h33 yab ff6 fs0 fc0 sc1 ls0 ws0"><span class="ff7 sc0"> <span class="_ _b"> </span><span class="ff1">Refer to the <span class="ffb">Jetson TX2/TX2i OEM Product Design Guide</span> <span class="ls2">and </span>the appropriate version of the Thermal Design Guide (either Jetson TX2 or TX2i) for evaluating product p<span class="_ _0"></span>ower and </span></span></div><div class="t m0 x45 ha yac ff1 fs0 fc0 sc0 ls0 ws0">thermal solution requirements. See the software documentation for information on changing the default pow<span class="_ _1"></span>er mode (default: Max<span class="_ _0"></span>-P). </div><div class="t m0 x1 ha yad ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 yae ff3 fs0 fc0 sc0 ls0 ws0"> <span class="_ _c"> </span> </div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/bg4.jpg"><div class="c x0 y22 w3 h0"><div class="t m0 x9 hd y23 ff1 fs7 fc0 sc0 ls0 ws0">Jetson TX2 / T<span class="_ _0"></span>X2i System-<span class="ls9">on</span>-Module </div><div class="t m0 xa hd y24 ff1 fs7 fc0 sc0 ls0 ws0">Pascal GPU + AR<span class="_ _0"></span>Mv8 + 8GB LPD<span class="_ _0"></span>DR4 + 32GB eMMC<span class="_ _0"></span> + W<span class="_ _0"></span>LAN/BT </div><div class="t m0 x1 ha y1 ff1 fs0 fc0 sc0 ls0 ws0">JETSON | TX2/TX2i | DATASHEET | 1.0 <span class="ls1">| </span>SU<span class="_ _0"></span>BJECT TO CHANGE <span class="ls1">| </span>COPYRIGHT © 2<span class="_ _0"></span>014 <span class="ff2">–</span> <span class="ls2">201</span>8 NVIDIA CORPORATION. ALL RIGHTS RESERVE<span class="_ _1"></span>D. <span class="_ _2"> </span>4 </div><div class="t m0 x1 h8 yaf ff4 fs5 fc0 sc0 ls0 ws0">Revision History<span class="_ _0"></span> </div></div><div class="c x1 yb0 wb h23"><div class="t m0 x47 hc yb1 ff1 fs6 fc0 sc0 ls0 ws0">Version </div></div><div class="c x48 yb0 wc h23"><div class="t m0 x47 hc yb1 ff1 fs6 fc0 sc0 ls0 ws0">Date </div></div><div class="c x49 yb0 wd h23"><div class="t m0 x47 hc yb1 ff1 fs6 fc0 sc0 ls0 ws0">Description </div></div><div class="c x1 yb2 wb h24"><div class="t m0 x47 ha yb3 ff1 fs0 fc0 sc0 ls0 ws0">1.0 </div></div><div class="c x48 yb2 wc h24"><div class="t m0 x47 ha yb3 ff1 fs0 fc0 sc0 ls0 ws0">MAR <span class="ls2">201</span>8 </div></div><div class="c x49 yb2 wd h24"><div class="t m0 x47 ha yb4 ff1 fs0 fc0 sc0 ls0 ws0">Initial Release </div><div class="t m0 x47 ha yb5 ff1 fs0 fc0 sc0 ls0 ws0">This document is being maintained as a separate instance from the Jetson TX2 Data Sheet. It supports both Jetson TX2 </div><div class="t m0 x47 ha y3f ff1 fs0 fc0 sc0 ls0 ws0">and Jetson TX2i modules. It is constructed so that those familiar with Jetson TX2 can easily locate any functional </div><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0">differences between the TX2 and TX2i modules </div></div><div class="c x1 yb6 wb h34"><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c x48 yb6 wc h34"><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c x49 yb6 wd h34"><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c x1 yb7 wb h34"><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c x48 yb7 wc h34"><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c x49 yb7 wd h34"><div class="t m0 x47 ha y86 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="c x0 y22 w3 h0"><div class="t m0 x1 h9 yb8 ff1 fs4 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h9 yb9 ff1 fs4 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h8 yba ff4 fs5 fc0 sc0 ls0 ws0"> <span class="_ _d"> </span> </div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6252105c6caf596192580b4c/bg5.jpg"><div class="c x0 y22 w3 h0"><div class="t m0 x9 hd y23 ff1 fs7 fc0 sc0 ls0 ws0">Jetson TX2 / T<span class="_ _0"></span>X2i System-<span class="ls9">on</span>-Module </div><div class="t m0 xa hd y24 ff1 fs7 fc0 sc0 ls0 ws0">Pascal GPU + AR<span class="_ _0"></span>Mv8 + 8GB LPD<span class="_ _0"></span>DR4 + 32GB eMMC<span class="_ _0"></span> + W<span class="_ _0"></span>LAN/BT </div><div class="t m0 x1 ha y1 ff1 fs0 fc0 sc0 ls0 ws0">JETSON | TX2/TX2i | DATASHEET | 1.0 <span class="ls1">| </span>SU<span class="_ _0"></span>BJECT TO CHANGE <span class="ls1">| </span>COPYRIGHT © 2<span class="_ _0"></span>014 <span class="ff2">–</span> <span class="ls2">201</span>8 NVIDIA CORPORATION. ALL RIGHTS RESERVE<span class="_ _1"></span>D. <span class="_ _2"> </span>5 </div><div class="t m0 x1 h8 ybb ff4 fs5 fc0 sc0 ls0 ws0">Table of Contents<span class="ff1 fs4"> </span></div><div class="t m0 x1 h35 ybc ff3 fs1 fc0 sc0 ls0 ws0">1.0 Physical Description <span class="_ _e"> </span>7<span class="ffc fsa"> </span></div><div class="t m0 x4a h36 ybd ff1 fsb fc0 sc0 ls0 ws0"> Connectivit<span class="_ _0"></span>y (TX2 onl<span class="_ _0"></span>y<span class="_ _4"></span>)<span class="_ _7"></span> <span class="_ _1"></span><span class="ls10">...............................................................................................................................<span class="ls0"> <span class="_ _f"></span>8<span class="ffc fsa"> </span></span></span></div><div class="t m0 x4a h36 ybe ff1 fsb fc0 sc0 ls0 ws0"> W<span class="_ _0"></span>LAN / BT Antenna Connectors<span class="_ _0"></span> (TX2 only)<span class="_ _0"></span> <span class="_ _10"></span><span class="ls10">...............................................................................................<span class="ls0"> <span class="_ _f"></span>8<span class="ffc fsa"> </span></span></span></div><div class="t m0 x4a h36 ybf ff1 fsb fc0 sc0 ls0 ws0"> Therm<span class="_ _0"></span>al Characteristics<span class="_ _0"></span> <span class="_ _f"></span><span class="ls10">...............................................................................................................................<span class="ls0"> <span class="_ _f"></span>9<span class="ffc fsa"> </span></span></span></div><div class="t m0 x1 h35 yc0 ff3 fs1 fc0 sc0 ls0 ws0">2.0 Functional Overview <span class="_ _11"> </span>9<span class="ffc fsa"> </span></div><div class="t m0 x4a h36 yc1 ff1 fsb fc0 sc0 ls0 ws0"> Pascal GPU<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">.................................................................................................................................................<span class="ls0"> <span class="_ _f"></span>9<span class="ffc fsa"> </span></span></span></div><div class="t m0 x4a h36 yc2 ff1 fsb fc0 sc0 ls0 ws0"> CPU Com<span class="_ _0"></span>plex <span class="_ _10"></span><span class="ls10">............................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">10<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yc3 ff1 fsb fc0 sc0 ls0 ws0">2.2.1 NVIDIA Denver <span class="_ _0"></span>2 (Dual-Core) <span class="_ _0"></span>Processor<span class="_ _0"></span> <span class="_ _4"></span><span class="ls10">....................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">10<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yc4 ff1 fsb fc0 sc0 ls0 ws0">2.2.2 ARM Cortex<span class="_ _0"></span>-A57 MPCor<span class="_ _0"></span>e (Quad-Core)<span class="_ _0"></span> Processor<span class="_ _0"></span> <span class="_ _10"></span><span class="ls10">.....................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">11<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yc5 ff1 fsb fc0 sc0 ls0 ws0"> Mem<span class="_ _0"></span>ory Controller <span class="_ _3"></span><span class="ls10">.....................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">11<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yc6 ff1 fsb fc0 sc0 ls0 ws0"> Image Signal<span class="_ _0"></span> Processor (ISP)<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">...................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">12<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yc7 ff1 fsb fc0 sc0 ls0 ws0"> Display Contr<span class="_ _0"></span>oller <span class="_ _4"></span><span class="ls10">......................................................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">13<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yc8 ff1 fsb fc0 sc0 ls0 ws0"> High Defin<span class="_ _0"></span>ition (HD) Audio/Vide<span class="_ _0"></span>o Subsystem<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">...........................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">13<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yc9 ff1 fsb fc0 sc0 ls0 ws0">2.6.1 Multi-Standard<span class="_ _0"></span> Video Decoder<span class="_ _0"></span> <span class="_ _13"></span><span class="ls10">.....................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">13<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yca ff1 fsb fc0 sc0 ls0 ws0">2.6.2 Multi-Standard<span class="_ _0"></span> Video Encoder<span class="_ _0"></span> <span class="_ _10"></span><span class="ls10">.....................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">14<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ycb ff1 fsb fc0 sc0 ls0 ws0">2.6.3 JPEG Processin<span class="_ _0"></span>g <span class="_ _10"></span><span class="ls10">.........................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">15<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ycc ff1 fsb fc0 sc0 ls0 ws0">2.6.4 Video Im<span class="_ _0"></span>age Compositor (VIC)<span class="_ _0"></span> <span class="_ _10"></span><span class="ls10">....................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">15<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ycd ff1 fsb fc0 sc0 ls0 ws0">2.6.5 Audio Proces<span class="_ _0"></span>sing Engine (APE)<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">..................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">16<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yce ff1 fsb fc0 sc0 ls0 ws0">2.6.6 Tegra Secur<span class="_ _0"></span>ity Controller (T<span class="_ _0"></span>SEC) <span class="_ _10"></span><span class="ls10">................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">16<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 ycf ff1 fsb fc0 sc0 ls0 ws0"> Securit<span class="_ _0"></span>y Engine <span class="ls10">.........................................................................................................................................</span> <span class="_ _f"></span><span class="ls11">17<span class="ffc fsa ls0"> </span></span></div><div class="t m0 x4a h36 yd0 ff1 fsb fc0 sc0 ls0 ws0"> Therm<span class="_ _0"></span>al Monitoring and Managem<span class="_ _0"></span>ent<span class="_ _0"></span> <span class="ls10">......................................................................................................</span> <span class="_ _12"></span><span class="ls11">17<span class="ffc fsa ls0"> </span></span></div><div class="t m0 x1 h35 yd1 ff3 fs1 fc0 sc0 ls0 ws0">3.0 Power and S<span class="_ _0"></span>y<span class="_ _4"></span>s<span class="_ _0"></span>tem Management <span class="_ _14"> </span><span class="ls12">18</span><span class="ffc fsa"> </span></div><div class="t m0 x4a h36 yd2 ff1 fsb fc0 sc0 ls0 ws0"> Power Rails<span class="_ _0"></span><span class="ls10">................................................................................................................................................</span> <span class="_ _f"></span><span class="ls11">18<span class="ffc fsa ls0"> </span></span></div><div class="t m0 x4a h36 yd3 ff1 fsb fc0 sc0 ls0 ws0"> Power Seque<span class="_ _0"></span>ncing <span class="ls10">....................................................................................................................................</span> <span class="_ _12"></span><span class="ls11">19<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></div><div class="t m0 x2c h36 yd4 ff1 fsb fc0 sc0 ls11 ws0">3.2.<span class="ls0">1 Power Up<span class="_ _0"></span> <span class="ls10">.....................................................................................................................................</span> <span class="_ _12"></span><span class="ls11">19<span class="ffc fsa ls0"> </span></span></span></div><div class="t m0 x2c h36 yd5 ff1 fsb fc0 sc0 ls0 ws0">3.2.2 Power Down<span class="_ _0"></span> <span class="_ _13"></span><span class="ls10">................................................................................................................................<span class="ls0">. <span class="_ _12"></span><span class="ls11">20<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yd6 ff1 fsb fc0 sc0 ls0 ws0"> Power States<span class="_ _0"></span> <span class="_ _4"></span><span class="ls10">.............................................................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">20<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yd7 ff1 fsb fc0 sc0 ls0 ws0">3.3.1 ON State <span class="ls10">......................................................................................................................................</span> <span class="_ _12"></span><span class="ls11">21<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></div><div class="t m0 x2c h36 yd8 ff1 fsb fc0 sc0 ls0 ws0">3.3.2 OFF State<span class="_ _0"></span> <span class="_ _12"></span><span class="ls10">.....................................................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">21<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yd9 ff1 fsb fc0 sc0 ls0 ws0">3.3.3 SLEEP State<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">22<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yda ff1 fsb fc0 sc0 ls0 ws0"> Clock<span class="_ _0"></span>s <span class="_ _10"></span><span class="ls10">........................................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">23<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 ydb ff1 fsb fc0 sc0 ls0 ws0"> W<span class="_ _0"></span>LAN Power States (TX2 onl<span class="_ _0"></span>y) <span class="_ _3"></span><span class="ls10">................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">23<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ydc ff1 fsb fc0 sc0 ls0 ws0">3.5.1 STA Mode<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">....................................................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">23<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ydd ff1 fsb fc0 sc0 ls0 ws0">3.5.2 P2P Group-<span class="_ _0"></span>owner Po<span class="_ _0"></span>wersave States<span class="_ _0"></span> <span class="_ _10"></span><span class="ls10">................................................................<span class="_ _0"></span>..........................<span class="ls0"> <span class="_ _12"></span><span class="ls11">24<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 yde ff1 fsb fc0 sc0 ls0 ws0"> Bluetooth Po<span class="_ _0"></span>wer States (T<span class="_ _0"></span>X2 only)<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">...........................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">24<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x1 h35 ydf ff3 fs1 fc0 sc0 ls0 ws0">4.0 Interface and Signal Descriptions <span class="_ _15"> </span><span class="ls12">25</span><span class="ffc fsa"> </span></div><div class="t m0 x4a h36 ye0 ff1 fsb fc0 sc0 ls0 ws0"> Storage C<span class="_ _0"></span>ontrollers and Interf<span class="_ _0"></span>aces <span class="_ _f"></span><span class="ls10">............................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">25<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ye1 ff1 fsb fc0 sc0 ls0 ws0">4.1.1 SD/eMMC C<span class="_ _0"></span>ontroller <span class="_ _10"></span><span class="ls10">....................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">25<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ye2 ff1 fsb fc0 sc0 ls0 ws0">4.1.2 Serial ATA (S<span class="_ _0"></span>ATA) Controller<span class="_ _0"></span> <span class="ls10">......................................................................................................</span> <span class="_ _12"></span><span class="ls11">26<span class="ffc fsa ls0"> </span></span></div><div class="t m0 x4a h36 ye3 ff1 fsb fc0 sc0 ls0 ws0"> USB Interf<span class="_ _0"></span>aces<span class="ls10">...........................................................................................................................................</span> <span class="_ _f"></span><span class="ls11">27<span class="ffc fsa ls0"> </span></span></div><div class="t m0 x2c h36 ye4 ff1 fsb fc0 sc0 ls0 ws0">4.2.1 USB 2.0<span class="_ _0"></span> <span class="_ _13"></span><span class="ls10">........................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">27<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ye5 ff1 fsb fc0 sc0 ls0 ws0">4.2.2 USB 3.0<span class="_ _0"></span> <span class="_ _13"></span><span class="ls10">........................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">28<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 ye6 ff1 fsb fc0 sc0 ls0 ws0"> PCI Express<span class="_ _0"></span> (PCIe) Interf<span class="_ _0"></span>ace <span class="_ _3"></span><span class="ls10">....................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">28<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x4a h36 ye7 ff1 fsb fc0 sc0 ls0 ws0"> Display Interf<span class="_ _0"></span>aces <span class="_ _3"></span><span class="ls10">......................................................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">30<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 ye8 ff1 fsb fc0 sc0 ls11 ws0">4.<span class="ls0">4.1 MIPI Displ<span class="_ _0"></span>ay Serial Interf<span class="_ _0"></span>ace (DSI) <span class="_ _3"></span><span class="ls10">..............................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">30<span class="ffc fsa ls0"> </span></span></span></span></span></div><div class="t m0 x2c h36 ye9 ff1 fsb fc0 sc0 ls0 ws0">4.4.2 High-Defin<span class="_ _0"></span>ition Multim<span class="_ _0"></span>edia Interface (HDMI) an<span class="_ _0"></span>d DisplayPort (DP) Interf<span class="_ _0"></span>aces<span class="_ _0"></span> <span class="_ _4"></span><span class="ls10">...........................<span class="ls0"> <span class="_ _f"></span><span class="ls11">31<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yea ff1 fsb fc0 sc0 ls11 ws0">4.<span class="ls0">4.3 Embedded Disp<span class="_ _0"></span>layPort (eDP) In<span class="_ _0"></span>terface<span class="_ _0"></span> <span class="_ _f"></span><span class="ls10">.......................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">32<span class="_ _0"></span><span class="ffc fsa ls0"> </span></span></span></span></span></div><div class="t m0 x4a h36 yeb ff1 fsb fc0 sc0 ls0 ws0"> Audio Contro<span class="_ _0"></span>llers and Interf<span class="_ _0"></span>aces <span class="_ _3"></span><span class="ls10">...............................................................................................................<span class="ls0"> <span class="_ _12"></span><span class="ls11">33<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yec ff1 fsb fc0 sc0 ls0 ws0">4.5.1 Inter-IC Soun<span class="_ _0"></span>d (I2S) Controller<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">....................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">33<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yed ff1 fsb fc0 sc0 ls0 ws0">4.5.2 Digital MIC Contro<span class="_ _0"></span>ller (DMIC)<span class="_ _0"></span> <span class="_ _3"></span><span class="ls10">......................................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">35<span class="ffc fsa ls0"> </span></span></span></span></div><div class="t m0 x2c h36 yee ff1 fsb fc0 sc0 ls0 ws0">4.5.3 Digital Speak<span class="_ _0"></span>er Controller (DS<span class="_ _0"></span>PK)<span class="_ _0"></span> <span class="_ _f"></span><span class="ls10">...............................................................................................<span class="ls0"> <span class="_ _f"></span><span class="ls11">35<span class="ffc fsa ls0"> </span></span></span></span></div></div><a class="l" rel='nofollow' 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