r01an1062ej0110_rl78_safety.zip_Renasys Safety 1062

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/625096746caf5961920bfa61/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625096746caf5961920bfa61/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> APPLICATION <span class="_ _0"></span>NOTE </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">R01AN1062EJ01<span class="_ _1"></span>10 Rev. 1.10 <span class="_ _2"> </span> <span class="_ _3"> </span>Page 1 of 42 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls2 ws2">Nov. 15, 2013 <span class="_ _4"> </span><span class="ls3 ws3"> </span></div><div class="t m0 x1 h4 y4 ff2 fs2 fc0 sc0 ls3 ws4">RL78 Family </div><div class="t m0 x1 h2 y5 ff1 fs0 fc0 sc0 ls4 ws5">IEC60730/60335 Self Test Library for RL78 MCU </div><div class="t m0 x1 h5 y6 ff2 fs3 fc0 sc0 ls5 ws3">Introduction </div><div class="t m0 x1 h3 y7 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y8 ff3 fs1 fc0 sc0 ls6 ws6">Today, as automatic electronic controls systems continue<span class="_ _1"></span> to<span class="ls7 ws7"> expand into many diverse applications, the requirement of </span></div><div class="t m0 x1 h6 y9 ff3 fs1 fc0 sc0 ls8 ws8">reliability and safety are becoming an ever increasing factor in system design. </div><div class="t m0 x1 h6 ya ff3 fs1 fc0 sc0 ls9 ws9">For example, the i<span class="_ _1"></span>ntroduction of the<span class="_ _1"></span> IEC60730 safety<span class="_ _1"></span> standard for house<span class="_ _1"></span>hold appli<span class="_ _1"></span>ances requires m<span class="_ _1"></span>anufactures to </div><div class="t m0 x1 h6 yb ff3 fs1 fc0 sc0 lsa wsa">design automatic electronic co<span class="_ _1"></span>ntrols that ensure<span class="lsb wsb"> safe and reliable operation of their<span class="_ _5"></span> products. </span></div><div class="t m0 x1 h6 yc ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 yd ff3 fs1 fc0 sc0 lsc wsc">The IEC60730 standard<span class="_ _5"></span> covers all aspects of produ<span class="_ _5"></span>ct design but Annex H is of key importance for design of </div><div class="t m0 x1 h6 ye ff3 fs1 fc0 sc0 ls9 wsd">Microcontroll<span class="_ _1"></span>er based control<span class="_ _1"></span> systems. Thi<span class="_ _1"></span>s provides t<span class="_ _1"></span>hree <span class="lsd wse">soft<span class="_ _1"></span>ware classifications for <span class="lse wsf">au<span class="_ _1"></span>tomatic electronic controls: </span></span></div><div class="t m0 x1 h6 yf ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y10 ff3 fs1 fc0 sc0 lsf ws10">1. Class A: C<span class="_ _1"></span>ontrol funct<span class="_ _1"></span>ions, w<span class="_ _1"></span>hich are not<span class="_ _1"></span> intended t<span class="_ _1"></span>o be relied <span class="_ _1"></span>upon for<span class="_ _1"></span> the safety of t<span class="_ _1"></span>he equipm<span class="_ _1"></span>ent. </div><div class="t m0 x2 h6 y11 ff3 fs1 fc0 sc0 ls10 ws11">Examples: Room thermostats, humidity contro<span class="ls11 ws12">ls, lighting contro<span class="_ _5"></span>ls, timers, and switches. </span></div><div class="t m0 x2 h6 y12 ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y13 ff3 fs1 fc0 sc0 ls12 ws13">2. Class B:<span class="_ _1"></span> Control f<span class="_ _1"></span>unctions,<span class="_ _1"></span> which are i<span class="_ _1"></span>ntended to <span class="_ _1"></span>prevent<span class="_ _1"></span> unsafe operati<span class="_ _1"></span>on of the co<span class="_ _1"></span>ntrolled e<span class="_ _1"></span>quipment<span class="_ _1"></span>. </div><div class="t m0 x2 h6 y14 ff3 fs1 fc0 sc0 ls13 ws14">Examples: Therm<span class="_ _1"></span>al cut-offs and doo<span class="lsc ws15">r locks for laundr<span class="_ _5"></span>y equipment. </span></div><div class="t m0 x2 h6 y15 ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y16 ff3 fs1 fc0 sc0 ls14 ws16">3. Class C: C<span class="_ _1"></span>ontrol functi<span class="_ _1"></span>ons, which a<span class="_ _1"></span>re intende<span class="_ _1"></span>d to preve<span class="_ _1"></span>nt special hazar<span class="_ _1"></span>ds </div><div class="t m0 x2 h6 y17 ff3 fs1 fc0 sc0 ls15 ws17">Examples: Autom<span class="_ _1"></span>atic burner controls<span class="ls2 ws18"> and therm<span class="_ _1"></span>al cut-outs for closed. </span></div><div class="t m0 x1 h6 y18 ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y19 ff3 fs1 fc0 sc0 ls16 ws19">Appliances such as washing m<span class="ls13 ws14">achines, dishwashers, dryers, re<span class="lse ws1a">frige<span class="_ _1"></span>rators, freezers, and Cook<span class="ls11 ws1b">ers / Stoves will tend to fall </span></span></span></div><div class="t m0 x1 h6 y1a ff3 fs1 fc0 sc0 ls17 ws3">under the cl<span class="_ _1"></span>assification <span class="_ _1"></span>of Class B. <span class="_ _1"></span> </div><div class="t m0 x1 h3 y1b ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y1c ff3 fs1 fc0 sc0 ls17 ws1c">This Applicat<span class="_ _1"></span>ion Note pr<span class="_ _1"></span>ovides guidel<span class="_ _1"></span>ines of how t<span class="_ _1"></span>o use flex<span class="ls18 ws1d">ible sample software routines to assist with compliance </span></div><div class="t m0 x1 h6 y1d ff3 fs1 fc0 sc0 ls19 ws1e">with IEC60730<span class="_ _1"></span>/60335 class B <span class="_ _1"></span>safety standard<span class="_ _1"></span>s. <span class="fc1 ls3 ws3"> </span></div><div class="t m0 x1 h6 y1e ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y1f ff3 fs1 fc0 sc0 ls1a ws1f">These software routines provided are designed<span class="_ _5"></span> to be used af<span class="ls1b ws20">ter the system power on, o<span class="_ _5"></span>r reset condition and also<span class="_ _5"></span> during </span></div><div class="t m0 x1 h6 y20 ff3 fs1 fc0 sc0 ls10 ws21">the application program execution. The end u<span class="_ _5"></span>ser has the flex<span class="ls1b ws22">ibility of what routin<span class="_ _5"></span>es are included and how to integrate </span></div><div class="t m0 x1 h6 y21 ff3 fs1 fc0 sc0 ls1c ws23">these routines into their overall app<span class="_ _5"></span>lication system design. This document and th<span class="_ _5"></span>e accompanying test harn<span class="_ _5"></span>ess code </div><div class="t m0 x1 h6 y22 ff3 fs1 fc0 sc0 ls7 ws24">provide examples of how to do th<span class="_ _5"></span>is. </div><div class="t m0 x1 h6 y23 ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y24 ff3 fs1 fc0 sc0 ls12 ws13">Note. Thi<span class="_ _1"></span>s docume<span class="_ _1"></span>nt is based on<span class="_ _1"></span> the European <span class="_ _1"></span>Norm EN603<span class="_ _1"></span>35-1:2002/<span class="_ _1"></span>A1:2004 <span class="_ _1"></span>Annex R<span class="_ _1"></span>, in which t<span class="_ _1"></span>he Norm<span class="_ _1"></span> IEC </div><div class="t m0 x1 h6 y25 ff3 fs1 fc0 sc0 ls17 ws3">60730-1 (EN<span class="_ _1"></span>60730-1:20<span class="_ _1"></span>00) is used i<span class="_ _1"></span>n some poi<span class="_ _1"></span>nts. The An<span class="_ _1"></span>nex R of t<span class="_ _1"></span>he mentioned <span class="_ _1"></span>Norm contai<span class="_ _1"></span>ns just a sin<span class="_ _1"></span>gle sheet </div><div class="t m0 x1 h6 y26 ff3 fs1 fc0 sc0 ls1d ws25">that jumps to the IEC 60730-1 for definitions, information and applicable paragraphs<span class="_ _5"></span>. </div><div class="t m0 x1 h5 y27 ff2 fs3 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h5 y28 ff2 fs3 fc0 sc0 ls1e ws26">Target Devices </div><div class="t m0 x1 h3 y29 ff1 fs1 fc0 sc0 ls1f ws3"> <span class="ff3 ls20 ws27">RL78 Microcontr<span class="_ _1"></span>oller </span></div><div class="t m0 x3 h3 y2a ff1 fs1 fc0 sc0 ls9 ws3">R01AN1062E<span class="_ _1"></span>J0110</div><div class="t m0 x4 h3 y2b ff1 fs1 fc0 sc0 lse ws28">Rev. 1.10</div><div class="t m0 x5 h3 y2c ff1 fs1 fc0 sc0 ls13 ws29">Nov. 15, 2013</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625096746caf5961920bfa61/bg2.jpg"><div class="t m0 x1 h5 y2d ff2 fs3 fc0 sc0 ls21 ws2a"> <span class="_ _6"> </span>IEC60730/60335 Self Test Library for RL78 MCU </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">R01AN1062EJ01<span class="_ _1"></span>10 Rev. 1.10 <span class="_ _2"> </span> <span class="_ _3"> </span>Page 2 of 42 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls2 ws2">Nov. 15, 2013 <span class="_ _4"> </span><span class="ls3 ws3"> </span></div><div class="t m0 x1 h5 y2e ff2 fs3 fc0 sc0 ls22 ws3">Contents </div><div class="t m0 x6 h3 y2f ff1 fs1 fc0 sc0 ls3 ws3">1<span class="ff4 fs4"> <span class="_ _7"> </span></span><span class="ls6 ws2b">Self Test Librar<span class="ls23 ws10">ies Introduction ..............................................................................................<span class="_ _1"></span><span class="ls1f ws2c">........... 3<span class="ff4 fs4 ls3 ws3"> </span></span></span></span></div><div class="t m0 x6 h3 y30 ff1 fs1 fc0 sc0 ls3 ws3">2<span class="ff4 fs4"> <span class="_ _7"> </span></span><span class="ls23 ws10">Self Test Library Functions ...................................................................................................<span class="ls1f ws2c">............ 4</span></span><span class="ff4 fs4"> </span></div><div class="t m0 x6 h3 y31 ff1 fs1 fc0 sc0 ls16 ws3">2.1<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls15 ws2d">CPU Register</span><span class="ls1f"> Tests.............................................................................................................<span class="ws2c">.............. 4</span><span class="ff4 fs4 ls3"> </span></span></div><div class="t m0 x6 h3 y32 ff1 fs1 fc0 sc0 ls16 ws3">2.2<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls24 ws2e">Invariable Memory Te<span class="ls23 ws10">st – Flash ROM <span class="_ _1"></span>............................................................................................<span class="_ _1"></span><span class="ls25 ws2f"> 11<span class="ff4 fs4 ls3 ws3"> </span></span></span></span></div><div class="t m0 x6 h3 y33 ff1 fs1 fc0 sc0 ls16 ws3">2.3<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls2 ws2">Variable memory<span class="ls1a ws30"> - SRAM ........................................................................................................<span class="_ _1"></span><span class="ls26 ws31">....... 15<span class="ff4 fs4 ls3 ws3"> </span></span></span></span></div><div class="t m0 x6 h3 y34 ff1 fs1 fc0 sc0 ls16 ws3">2.4<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls1a ws30">System Clock Test <span class="_ _1"></span>.............................................................................................................<span class="_ _1"></span><span class="ls27 ws32">............. 21<span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y35 ff1 fs1 fc0 sc0 ls3 ws3">3<span class="ff4 fs4"> <span class="_ _7"> </span></span><span class="ls1a ws30">Example Usage <span class="_ _9"></span>.................................................................................................................<span class="ls27 ws32">.............. 26<span class="_ _1"></span><span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y36 ff1 fs1 fc0 sc0 ls16 ws3">3.1<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="lse ws28">CPU Verifi<span class="ls1f ws33">cation ..............................................................................................................<span class="ls1c ws34">................ 26</span></span></span><span class="ff4 fs4 ls3"> </span></div><div class="t m0 x6 h3 y37 ff1 fs1 fc0 sc0 ls16 ws3">3.2<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls15 ws35">Flash ROM Veri<span class="ls1a ws36">fication ........................................................................................................<span class="_ _1"></span><span class="ls27 ws32">........... 27<span class="ff4 fs4 ls3 ws3"> </span></span></span></span></div><div class="t m0 x6 h3 y38 ff1 fs1 fc0 sc0 ls16 ws3">3.3<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ws37">RAM Verification <span class="_ _a"></span><span class="ls1f ws3">.............................................................................................................................. <span class="_ _9"></span><span class="ls25">28<span class="ff4 fs4 ls3"> </span></span></span></span></div><div class="t m0 x6 h3 y39 ff1 fs1 fc0 sc0 ls16 ws3">3.4<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls1a ws30">System Clock Verification .....................................................................................................<span class="ls7 ws38">.......... 29</span></span><span class="ff4 fs4 ls3"> </span></div><div class="t m0 x6 h3 y3a ff1 fs1 fc0 sc0 ls16 ws3">3.5<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls1a ws30">Code Coverage <span class="_ _b"></span>.................................................................................................................<span class="ls27 ws32">.............. 29<span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y3b ff1 fs1 fc0 sc0 ls3 ws3">4<span class="ff4 fs4"> <span class="_ _7"> </span></span><span class="ls1a ws39">Benchmarking ..................................................................................................................<span class="ls1c ws34">............... 30</span></span><span class="ff4 fs4"> </span></div><div class="t m0 x6 h3 y3c ff1 fs1 fc0 sc0 ls16 ws3">4.1<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls1d ws3a">Development En<span class="ls1a ws3b">vironment .......................................................................................................<span class="ls26 ws31">....... 30</span></span></span><span class="ff4 fs4 ls3"> </span></div><div class="t m0 x6 h3 y3d ff1 fs1 fc0 sc0 ls16 ws3">4.2<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls1a ws30">CubeSuite+ Settings ...........................................................................................................<span class="_ _1"></span><span class="ls27 ws32">............ 30<span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y3e ff1 fs1 fc0 sc0 ls3 ws3">5<span class="ff4 fs4"> <span class="_ _7"> </span></span><span class="ls15 ws2d">Additional Hardware Resources <span class="_ _a"></span><span class="ls1a ws3c">...................................................................................................... 33<span class="_ _1"></span><span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y3f ff1 fs1 fc0 sc0 ls16 ws3">5.1<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="ls28 ws3d">Additional Safety<span class="ls1a ws30"> Functions <span class="_ _a"></span>...................................................................................................<span class="ls7 ws38">.......... 33<span class="ff4 fs4 ls3 ws3"> </span></span></span></span></div><div class="t m0 x6 h3 y40 ff1 fs1 fc0 sc0 ls16 ws3">5.2<span class="ff4 fs4 ls3"> <span class="_ _8"> </span></span><span class="lse ws28">Additional Self Test Functions <span class="_ _a"></span><span class="ls1a ws3c">......................................................................................................... 38<span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y41 ff1 fs1 fc0 sc0 ls3 ws3">6<span class="ff4 fs4"> <span class="_ _7"> </span></span><span class="ls10 ws3e">Related Applic<span class="ls29 ws3f">ation No<span class="ls1f ws40">te ......................................................................................................<span class="ls27 ws32">........... 39</span></span></span></span><span class="ff4 fs4"> </span></div><div class="t m0 x6 h3 y42 ff1 fs1 fc0 sc0 lse ws28">Revision Re<span class="ls1f ws41">cord ...............................................................................................................<span class="ls23 ws42">....................... 40<span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y43 ff1 fs1 fc0 sc0 ls8 ws43">General Precautions in the H<span class="ls2 ws2">andling of MPU/MC<span class="ls1c ws27">U Products <span class="_ _9"></span>................................................................. <span class="_ _9"></span>41<span class="ff4 fs4 ls3 ws3"> </span></span></span></div><div class="t m0 x6 h3 y44 ff1 fs1 fc0 sc0 ls3 ws3"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625096746caf5961920bfa61/bg3.jpg"><div class="t m0 x1 h5 y2d ff2 fs3 fc0 sc0 ls21 ws2a"> <span class="_ _6"> </span>IEC60730/60335 Self Test Library for RL78 MCU </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">R01AN1062EJ01<span class="_ _1"></span>10 Rev. 1.10 <span class="_ _2"> </span> <span class="_ _3"> </span>Page 3 of 42 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls2 ws2">Nov. 15, 2013 <span class="_ _4"> </span><span class="ls3 ws3"> </span></div><div class="t m0 x1 h5 y2e ff2 fs3 fc0 sc0 ls5 ws44">1 <span class="_ _c"> </span>Self Test Libraries Introduction </div><div class="t m0 x1 h6 y45 ff3 fs1 fc0 sc0 ls13 ws45">The self test library (STL) provides sel<span class="_ _1"></span>f test functions cove<span class="lsa ws46">ring the CPU re<span class="_ _1"></span>gisters, intern<span class="ls13 ws45">al memory and system<span class="_ _1"></span> clock. </span></span></div><div class="t m0 x1 h6 y46 ff3 fs1 fc0 sc0 ls2 ws47">The library test harness provides an <span class="ls2a ws48">Application Program<span class="_ _1"></span>mers Interface (API) fo<span class="lsa ws49">r eac<span class="_ _1"></span>h of the self test m<span class="_ _1"></span>odules, which </span></span></div><div class="t m0 x1 h6 y47 ff3 fs1 fc0 sc0 ls1d ws25">are described in this applications <span class="ls2b ws4a">note<span class="_ _5"></span>. These ca<span class="_ _5"></span>n be used<span class="_ _5"></span> in custo<span class="_ _5"></span>mer’s ap<span class="_ _5"></span>plicatio<span class="_ _5"></span>n wherev<span class="_ _5"></span>er requir<span class="_ _5"></span>ed. </span></div><div class="t m0 x1 h6 y48 ff3 fs1 fc0 sc0 ls2 ws4b">For the purposes of VDE certifi<span class="_ _1"></span><span class="ls2a ws4c">cation, the self test library functions a<span class="_ _1"></span>re <span class="ls3 ws4d">built as separate m<span class="_ _1"></span>odules. The Cube<span class="_ _1"></span>Suite+ test </span></span></div><div class="t m0 x1 h6 y49 ff3 fs1 fc0 sc0 ls2 ws18">harness allows each of the test<span class="_ _1"></span>s functions to be sel<span class="ls3 ws4e">ected in turn and run a<span class="_ _1"></span>s <span class="ls8 ws8">a stand alone function. <span class="_ _1"></span> </span></span></div><div class="t m0 x1 h6 y4a ff3 fs1 fc0 sc0 ls2a ws4f">The system hardware require<span class="_ _1"></span>ments includ<span class="ls2c ws50">e that at least two independe<span class="_ _1"></span>nt clock sources are available, e.g. Crystal / </span></div><div class="t m0 x1 h6 y4b ff3 fs1 fc0 sc0 ls18 ws51">ceramic oscillator and an independ<span class="_ _5"></span>ent oscillator or external<span class="ls1f ws52"> input source. The requirement is needed to pro<span class="_ _5"></span>vide an </span></div><div class="t m0 x1 h6 y4c ff3 fs1 fc0 sc0 ls2d ws53">independent cl<span class="_ _1"></span>ock reference f<span class="_ _1"></span>or monitori<span class="_ _1"></span>ng the system<span class="_ _1"></span> clock. The RL7<span class="_ _1"></span>8 is able to pr<span class="_ _1"></span>ovide these usi<span class="_ _1"></span>ng the Hig<span class="_ _1"></span>h speed </div><div class="t m0 x1 h6 y4d ff3 fs1 fc0 sc0 ls1a ws54">and Low speed intern<span class="_ _5"></span>al oscillators wh<span class="lsb wsb">ich are in<span class="_ _5"></span>dependent of each other. </span></div><div class="t m0 x1 h6 y4e ff3 fs1 fc0 sc0 ls2c ws50">Equally the application can provide a m<span class="_ _1"></span>ore accurate external <span class="ls2e ws55">reference<span class="_ _1"></span> clock or external cr<span class="ls2c ws50">ystal/resonators for the m<span class="_ _1"></span>ain </span></span></div><div class="t m0 x1 h6 y4f ff3 fs1 fc0 sc0 ls20 ws27">system cl<span class="_ _1"></span>ock can equall<span class="_ _1"></span>y be used. </div><div class="t m0 x1 h3 y50 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y51 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y52 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y53 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y54 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y55 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x7 h7 y56 ff2 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x8 h7 y57 ff2 fs1 fc0 sc0 ls2e ws56">Figure 1 Self Test Library (STL) Confi<span class="_ _1"></span>guration </div><div class="t m0 x1 h3 y58 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y59 ff3 fs1 fc0 sc0 ls6 ws57">The following CPU self test functions are <span class="ls2f ws58">included in the RL78 self test library. </span></div><div class="t m0 x2 h3 y5a ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff3 ls11 ws12">CPU Registers </span></span></div><div class="t m0 x9 h6 y5b ff3 fs1 fc0 sc0 ls16 ws59">The following CPU registers tests are included in this library </div><div class="t m0 x9 h6 y5c ff3 fs1 fc0 sc0 ls26 ws5a">All CPU working Registers in all four register<span class="_ _5"></span><span class="lsa ws5b"> banks, Stack Pointer <span class="lse ws5c">(SP), Processor Status </span></span></div><div class="t m0 x9 h6 y5d ff3 fs1 fc0 sc0 ls30 ws5d">word (PSW), Ex<span class="_ _5"></span>tension reg<span class="_ _5"></span>isters ES and CS. </div><div class="t m0 x9 h6 y5e ff3 fs1 fc0 sc0 ls2a ws4f">Internal data path are verified as <span class="_ _1"></span>part of the correct operation of these re<span class="_ _1"></span>gister tests </div><div class="t m0 x9 h6 y5f ff3 fs1 fc0 sc0 ls12 ws5e">IEC Reference - IEC 60<span class="_ _1"></span>730: 1999+A1:<span class="_ _1"></span>2003 Annex H - Tabl<span class="_ _1"></span>e H.11.12.1 C<span class="_ _1"></span>PU. </div><div class="t m0 x2 h3 y60 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff3 ls31 ws5f">Invariable Mem<span class="_ _1"></span>ory </span></span></div><div class="t m0 x9 h6 y61 ff3 fs1 fc0 sc0 ls1d ws25">This tests the MCU internal Flash memory </div><div class="t m0 x9 h6 y62 ff3 fs1 fc0 sc0 ls26 ws1">IEC Reference - IEC 6073<span class="_ _5"></span>0: 1999+A1:2003 <span class="_ _5"></span>Annex H – H2.19.4.1<span class="_ _5"></span> CRC – Single Word. </div><div class="t m0 x2 h3 y63 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff3 lsd wse">Variable Memory </span></span></div><div class="t m0 x9 h6 y64 ff3 fs1 fc0 sc0 ls1b ws60">This tests the Internal SRAM memory </div><div class="t m0 x9 h6 y65 ff3 fs1 fc0 sc0 ls1b ws1">IEC Reference - IEC 6073<span class="_ _5"></span>0: 1999+A1:2003 <span class="_ _5"></span>Annex H – H2.19.4.1<span class="_ _5"></span> CRC – Single Word. </div><div class="t m0 x1 h6 y66 ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x2 h3 y67 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff3 ls14 ws16">System Cl<span class="_ _1"></span>ock: Verifies the sy<span class="_ _1"></span>stem clock <span class="_ _1"></span>operation and c<span class="_ _1"></span>orrect freque<span class="_ _1"></span>ncy against a<span class="_ _1"></span> reference cloc<span class="_ _1"></span>k </span></span></div><div class="t m0 xa h6 y68 ff3 fs1 fc0 sc0 ls10 ws11">source(Note this test requires the use of an internal<span class="ls29 ws61"> or external independe<span class="_ _1"></span>nt reference cloc<span class="_ _1"></span>k)IEC Reference </span></div><div class="t m0 xa h6 y69 ff3 fs1 fc0 sc0 ls27 ws62">- IEC 60730: 19<span class="_ _5"></span>99+A1:2003 Annex H – H2.1<span class="_ _5"></span>9.4.1 CRC – Single Word<span class="_ _5"></span>. </div><div class="t m0 x1 h6 y6a ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x9 h6 y6b ff3 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x9 h6 y6c ff3 fs1 fc0 sc0 ls3 ws3"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625096746caf5961920bfa61/bg4.jpg"><div class="t m0 x1 h5 y2d ff2 fs3 fc0 sc0 ls21 ws2a"> <span class="_ _6"> </span>IEC60730/60335 Self Test Library for RL78 MCU </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">R01AN1062EJ01<span class="_ _1"></span>10 Rev. 1.10 <span class="_ _2"> </span> <span class="_ _3"> </span>Page 4 of 42 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls2 ws2">Nov. 15, 2013 <span class="_ _4"> </span><span class="ls3 ws3"> </span></div><div class="t m0 x1 h5 y6d ff2 fs3 fc0 sc0 ls5 ws44">2 <span class="_ _c"> </span>Self Test Library Functions </div><div class="t m0 x1 h5 y6e ff2 fs3 fc0 sc0 ls32 ws44">2.1 <span class="_ _e"> </span>CPU Register Tests </div><div class="t m0 x1 h3 y6f ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h6 y70 ff3 fs1 fc0 sc0 ls2f ws63">This section describes CPU register tests routines. Th<span class="_ _5"></span>e test harness control file ‘<span class="fc2 ls33 ws3">mai<span class="_ _5"></span>n.<span class="_ _5"></span>c</span><span class="lsf ws64">’ provides exam<span class="_ _1"></span>ples of the API </span></div><div class="t m0 x1 h6 y71 ff3 fs1 fc0 sc0 ls2d ws53">for each of t<span class="_ _1"></span>he CPU register t<span class="_ _1"></span>ests using “C” <span class="_ _1"></span>language. </div><div class="t m0 x1 h6 y72 ff3 fs1 fc0 sc0 ls2d ws65">These modules t<span class="_ _1"></span>est the fundam<span class="_ _1"></span>ental aspects of the CPU <span class="_ _1"></span>operation. Each <span class="_ _1"></span>of the API funct<span class="_ _1"></span>ions has a return val<span class="_ _1"></span>ue in order </div><div class="t m0 x1 h6 y73 ff3 fs1 fc0 sc0 ls24 ws66">to indicate the result of a test. </div><div class="t m0 x1 h6 y74 ff3 fs1 fc0 sc0 ls14 ws16">Each of the tes<span class="_ _1"></span>t modules save<span class="_ _1"></span>s the original c<span class="_ _1"></span>ontents of t<span class="_ _1"></span>he register(s<span class="_ _1"></span>) under te<span class="_ _1"></span>st and restores the<span class="_ _1"></span> contents o<span class="_ _1"></span>n completi<span class="_ _1"></span>on. </div><div class="t m0 x1 h6 y75 ff3 fs1 fc0 sc0 ls2c ws67">The following CPU registers are tested: </div><div class="t m0 xb h3 y76 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x2 h7 y77 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff2 ls2a ws68">Working registers and Accumulator</span><span class="ls2f ws69">: <span class="_ _f"> </span> AX, HL, DE, BC in Register Banks 0 – 3 </span></span></div><div class="t m0 x2 h3 y78 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 xb h3 y79 ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y7a ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y7b ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y7c ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y7d ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y7e ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y7f ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y80 ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xc h3 y81 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 xd h7 y82 ff2 fs1 fc0 sc0 lsa ws62">Figure 2 Working Register Configurati<span class="_ _1"></span>on </div><div class="t m0 xb h3 y83 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x2 h7 y84 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff2 ls24 ws2e">Stack Pointer</span><span class="ls1b ws6a"> (SP) </span></span></div><div class="t m0 x1 h3 y85 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y86 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 xe h3 y87 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 xf h7 y88 ff2 fs1 fc0 sc0 ls2a ws68">Figure 3 Stack Pointer Configuration </div><div class="t m0 x2 h3 y89 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x2 h7 y8a ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff2 ws6b">Processor Status Word</span><span class="ls1a ws30"> (PSW) </span></span></div><div class="t m0 x1 h3 y8b ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y8c ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x10 h3 y8d ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x11 h7 y8e ff2 fs1 fc0 sc0 ls2a ws68">Figure 4 PSW Register Configuration </div><div class="t m0 x2 h3 y8f ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x2 h7 y90 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff2 ls1 ws1">Code Address Extensio<span class="_ _1"></span>n Register<span class="ff1 ls34 ws6c"> (CS) </span></span></span></div><div class="t m0 x1 h3 y91 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x1 h3 y92 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x12 h3 y93 ff1 fs1 fc0 sc0 ls3 ws3"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625096746caf5961920bfa61/bg5.jpg"><div class="t m0 x1 h5 y2d ff2 fs3 fc0 sc0 ls21 ws2a"> <span class="_ _6"> </span>IEC60730/60335 Self Test Library for RL78 MCU </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">R01AN1062EJ01<span class="_ _1"></span>10 Rev. 1.10 <span class="_ _2"> </span> <span class="_ _3"> </span>Page 5 of 42 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls2 ws2">Nov. 15, 2013 <span class="_ _4"> </span><span class="ls3 ws3"> </span></div><div class="t m0 xd h7 y94 ff2 fs1 fc0 sc0 lsa ws62">Figure 5 Working Register Configurati<span class="_ _1"></span>on </div><div class="t m0 x2 h3 y95 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 x2 h7 y96 ff5 fs1 fc0 sc0 ls3 ws3"><span class="ff1"> <span class="_ _d"> </span><span class="ff2 lsd ws6d">Data Address Extension Regis<span class="_ _1"></span>ter<span class="ff1 ls24 ws2e"> (ES) </span></span></span></div><div class="t m0 x2 h3 y97 ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 xb h3 y98 ff1 fs1 fc0 sc0 ls3 ws3"><span class="fc3 sc0"> </span></div><div class="t m0 x13 h3 y99 ff1 fs1 fc0 sc0 ls3 ws3"> </div><div class="t m0 xd h7 y9a ff2 fs1 fc0 sc0 lsa ws62">Figure 6 Working Register Configurati<span class="_ _1"></span>on </div><div class="t m0 x14 h3 y9b ff1 fs1 fc0 sc0 ls3 ws3"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>