an_r01an0749eg0201_rl78_apl.zip_situationr88_Renasys Safety 0749

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/625154c26caf5961923eb047/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625154c26caf5961923eb047/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> APPLICATION <span class="_ _0"></span>NOTE </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls1 ws1">R01AN0749EG020<span class="_ _1"></span>1 Rev.2.01 <span class="_ _2"> </span> <span class="_ _3"> </span>Page 1 of 50 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls1 ws1">Mar 04, 2014 <span class="_ _4"> </span><span class="ls2 ws2"> </span></div><div class="t m0 x1 h4 y4 ff2 fs2 fc0 sc0 ls2 ws3">RL78 Family </div><div class="t m0 x1 h2 y5 ff1 fs0 fc0 sc0 ls3 ws4">VDE Certified IEC60730/60335 Self Test Library </div><div class="t m0 x1 h5 y6 ff2 fs3 fc0 sc0 ls4 ws2">Introduction </div><div class="t m0 x1 h3 y7 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y8 ff3 fs1 fc0 sc0 ls5 ws5">Today, as automatic electronic controls systems continue<span class="_ _1"></span> to<span class="ls6 ws6"> expand into many diverse applications, the requirement of </span></div><div class="t m0 x1 h6 y9 ff3 fs1 fc0 sc0 ls7 ws7">reliability and safety are becoming an ever increasing factor in system design. </div><div class="t m0 x1 h6 ya ff3 fs1 fc0 sc0 ls8 ws8">For example, the i<span class="_ _1"></span>ntroduction of the<span class="_ _1"></span> IEC60730 safety st<span class="_ _1"></span>andard for house<span class="_ _1"></span>hold appli<span class="_ _1"></span>ances requires m<span class="_ _1"></span>anufactures to </div><div class="t m0 x1 h6 yb ff3 fs1 fc0 sc0 ls9 ws9">design automatic electronic co<span class="_ _1"></span>ntrols that ensure<span class="lsa wsa"> safe and reliable operation of their<span class="_ _5"></span> products. </span></div><div class="t m0 x1 h6 yc ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 yd ff3 fs1 fc0 sc0 lsb wsb">The IEC60730 standard<span class="_ _5"></span> covers all aspects of produ<span class="_ _5"></span>ct design but Annex H is of key importance for design of </div><div class="t m0 x1 h6 ye ff3 fs1 fc0 sc0 ls8 wsc">Microcontroll<span class="_ _1"></span>er based control<span class="_ _1"></span> systems. Thi<span class="_ _1"></span>s provides three<span class="_ _1"></span> <span class="lsc wsd">software<span class="_ _1"></span> classifications for <span class="lsd wse">autom<span class="_ _1"></span>atic electronic controls: </span></span></div><div class="t m0 x1 h6 yf ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y10 ff3 fs1 fc0 sc0 lse wsf">1. Class A: C<span class="_ _1"></span>ontrol funct<span class="_ _1"></span>ions, w<span class="_ _1"></span>hich are not <span class="_ _1"></span>intended t<span class="_ _1"></span>o be relied <span class="_ _1"></span>upon for t<span class="_ _1"></span>he safety of t<span class="_ _1"></span>he equipm<span class="_ _1"></span>ent. </div><div class="t m0 x2 h6 y11 ff3 fs1 fc0 sc0 lsf ws10">Examples: Room thermostats, humidity contro<span class="ls10 ws11">ls, lighting contro<span class="_ _5"></span>ls, timers, and switches. </span></div><div class="t m0 x2 h6 y12 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y13 ff3 fs1 fc0 sc0 ls11 ws12">2. Class B:<span class="_ _1"></span> Control f<span class="_ _1"></span>unctions, w<span class="_ _1"></span>hich are i<span class="_ _1"></span>ntended to <span class="_ _1"></span>prevent un<span class="_ _1"></span>safe operati<span class="_ _1"></span>on of the cont<span class="_ _1"></span>rolled e<span class="_ _1"></span>quipment. <span class="_ _1"></span> </div><div class="t m0 x2 h6 y14 ff3 fs1 fc0 sc0 ls12 ws13">Examples: Therm<span class="_ _1"></span>al cut-offs and doo<span class="lsb ws14">r locks for laun<span class="_ _5"></span>dry equipment. </span></div><div class="t m0 x2 h6 y15 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y16 ff3 fs1 fc0 sc0 ls13 ws15">3. Class C: C<span class="_ _1"></span>ontrol functi<span class="_ _1"></span>ons, which a<span class="_ _1"></span>re intended t<span class="_ _1"></span>o preven<span class="_ _1"></span>t special hazards <span class="_ _1"></span> </div><div class="t m0 x2 h6 y17 ff3 fs1 fc0 sc0 ls1 ws16">Examples: Autom<span class="_ _1"></span>atic burner controls<span class="ls14 ws17"> and therm<span class="_ _1"></span>al cut-outs for closed. </span></div><div class="t m0 x1 h6 y18 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y19 ff3 fs1 fc0 sc0 ls15 ws18">Appliances such as washing m<span class="ls12 ws13">achines, dishwashers, dryers, re<span class="lsd ws19">frige<span class="_ _1"></span>rators, freezers, and Cook<span class="ls10 ws1a">ers / Stoves will tend to fall </span></span></span></div><div class="t m0 x1 h6 y1a ff3 fs1 fc0 sc0 ls16 ws2">under the cl<span class="_ _1"></span>assification <span class="_ _1"></span>of Class B. </div><div class="t m0 x1 h3 y1b ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y1c ff3 fs1 fc0 sc0 ls16 ws1b">This Applicat<span class="_ _1"></span>ion Note pr<span class="_ _1"></span>ovides guidel<span class="_ _1"></span>ines of how to <span class="_ _1"></span>use flex<span class="ls17 ws1c">ible sample software routines to assist with compliance </span></div><div class="t m0 x1 h6 y1d ff3 fs1 fc0 sc0 ls18 ws1d">with IEC60730/60335<span class="_ _5"></span> class B safety standards. These routin<span class="_ _5"></span>es have been certified by VDE Test an<span class="_ _5"></span>d Certification </div><div class="t m0 x1 h6 y1e ff3 fs1 fc0 sc0 ls19 ws1e">Institute GmbH. A copy of the Test Certificate is available <span class="ls1a ws1f">in the download package for this Application Note together </span></div><div class="t m0 x1 h6 y1f ff3 fs1 fc0 sc0 ls1b ws20">with the certified self test library sour<span class="ls1c ws21">ce code and the test harness IAR project<span class="fc1 ls2 ws2"> </span></span></div><div class="t m0 x1 h6 y20 ff3 fs1 fc0 sc0 ls8 ws22">Although these<span class="_ _1"></span> routines were <span class="_ _1"></span>developed usi<span class="_ _1"></span>ng IEC60730/<span class="_ _1"></span>60335 com<span class="_ _1"></span>pliance as a basis, t<span class="_ _1"></span>hey can be implem<span class="_ _1"></span>ented in any </div><div class="t m0 x1 h6 y21 ff3 fs1 fc0 sc0 ls1d ws23">system for self testing of Renesas Microcontroller families.<span class="fc1 ls2 ws2"> </span></div><div class="t m0 x1 h6 y22 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y23 ff3 fs1 fc0 sc0 ls1e ws24">These software routines provided are designed<span class="_ _5"></span> to be used af<span class="ls1f ws25">ter the system power on, o<span class="_ _5"></span>r reset condition and also<span class="_ _5"></span> during </span></div><div class="t m0 x1 h6 y24 ff3 fs1 fc0 sc0 lsf ws26">the application program execution. The end u<span class="_ _5"></span>ser has the flex<span class="ls1f ws27">ibility of what routin<span class="_ _5"></span>es are included and how to integrate </span></div><div class="t m0 x1 h6 y25 ff3 fs1 fc0 sc0 ls20 ws28">these routines into their overall app<span class="_ _5"></span>lication system design. This document and th<span class="_ _5"></span>e accompanying test harn<span class="_ _5"></span>ess code </div><div class="t m0 x1 h6 y26 ff3 fs1 fc0 sc0 ls6 ws29">provide examples of how to do th<span class="_ _5"></span>is. </div><div class="t m0 x1 h6 y27 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y28 ff3 fs1 fc0 sc0 ls11 ws12">Note. Thi<span class="_ _1"></span>s docume<span class="_ _1"></span>nt is based on<span class="_ _1"></span> the European <span class="_ _1"></span>Norm EN603<span class="_ _1"></span>35-1:2002/<span class="_ _1"></span>A1:2004 <span class="_ _1"></span>Annex R, i<span class="_ _1"></span>n which t<span class="_ _1"></span>he Norm IEC<span class="_ _1"></span> </div><div class="t m0 x1 h6 y29 ff3 fs1 fc0 sc0 ls16 ws2">60730-1 (EN<span class="_ _1"></span>60730-1:20<span class="_ _1"></span>00) is used i<span class="_ _1"></span>n some poi<span class="_ _1"></span>nts. The An<span class="_ _1"></span>nex R of the m<span class="_ _1"></span>entioned N<span class="_ _1"></span>orm contains <span class="_ _1"></span>just a singl<span class="_ _1"></span>e sheet </div><div class="t m0 x1 h6 y2a ff3 fs1 fc0 sc0 ls1b ws20">that jumps to the IEC 60730-1 for definitions, information and applicable paragraphs<span class="_ _5"></span>. </div><div class="t m0 x1 h5 y2b ff2 fs3 fc0 sc0 ls2 ws2"> </div><div class="t m0 x3 h3 y2c ff1 fs1 fc0 sc0 ls21 ws2">R01AN0749E<span class="_ _1"></span>G0201</div><div class="t m0 x4 h3 y2d ff1 fs1 fc0 sc0 ls14 ws2">Rev.2.01</div><div class="t m0 x5 h3 y2e ff1 fs1 fc0 sc0 ls22 ws2a">Mar 04, 2014</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625154c26caf5961923eb047/bg2.jpg"><div class="t m0 x1 h5 y2f ff2 fs3 fc0 sc0 ls23 ws2b">RL78 Family <span class="_ _6"> </span>VDE Certified IE<span class="ls24 ws2c">C60730/60335 Self Test Library </span></div><div class="t m0 x1 h6 y30 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y31 ff1 fs1 fc0 sc0 ls1 ws1">R01AN0749EG020<span class="_ _1"></span>1 Rev.2.01 <span class="_ _7"> </span> <span class="_ _3"> </span>Page 2 of 50 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls1 ws1">Mar 04, 2014 <span class="_ _4"> </span><span class="ls2 ws2"> </span></div><div class="t m0 x1 h5 y32 ff2 fs3 fc0 sc0 ls25 ws2d">Target Devices </div><div class="t m0 x1 h3 y33 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h7 y34 ff3 fs3 fc0 sc0 ls26 ws2e">RL78 Family </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625154c26caf5961923eb047/bg3.jpg"><div class="t m0 x1 h5 y2f ff2 fs3 fc0 sc0 ls23 ws2b">RL78 Family <span class="_ _6"> </span>VDE Certified IE<span class="ls24 ws2c">C60730/60335 Self Test Library </span></div><div class="t m0 x1 h6 y30 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y31 ff1 fs1 fc0 sc0 ls1 ws1">R01AN0749EG020<span class="_ _1"></span>1 Rev.2.01 <span class="_ _7"> </span> <span class="_ _3"> </span>Page 3 of 50 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls1 ws1">Mar 04, 2014 <span class="_ _4"> </span><span class="ls2 ws2"> </span></div><div class="t m0 x1 h5 y35 ff2 fs3 fc0 sc0 ls27 ws2">Contents </div><div class="t m0 x6 h3 y36 ff1 fs1 fc0 sc0 ls28 ws2">1.<span class="ff4 fs4 ls2"><span class="_ _8"> </span></span><span class="ls5 ws2f">Self Test Librar<span class="ls1a wsf">ies Introduction ..............................................................................................<span class="_ _1"></span><span class="ls29 ws30">........... 4<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y37 ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff4 fs4"><span class="_ _9"> </span></span><span class="ff1 ls2a ws31">CPU Registers <span class="_ _a"></span><span class="ls29 ws2">...............................................................................................................................<span class="ws30">.... 4</span><span class="ff4 fs4 ls2"></span></span></span></div><div class="t m0 x6 h3 y38 ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff4 fs4"><span class="_ _9"> </span></span><span class="ff1 lsd">Invariable <span class="ls1e ws32">Memory .............................................................................................................<span class="_ _1"></span><span class="ls29 ws30">................ 4<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y39 ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff4 fs4"><span class="_ _9"> </span></span><span class="ff1 ls12 ws33">Variable Me<span class="ls1e ws34">mory ...............................................................................................................<span class="_ _1"></span><span class="ls29 ws30">................ 4<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y3a ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff4 fs4"><span class="_ _9"> </span></span><span class="ff1 ls29">System Clock <span class="_ _1"></span>..................................................................................................................<span class="ws30">.................. 4</span><span class="ff4 fs4 ls2"></span></span></div><div class="t m0 x6 h3 y3b ff1 fs1 fc0 sc0 ls28 ws2">2.<span class="ff4 fs4 ls2"><span class="_ _8"> </span></span><span class="ls1a wsf">Self Test Library Functions ...................................................................................................<span class="ls29 ws30">............ 5</span></span><span class="ff4 fs4 ls2"></span></div><div class="t m0 x6 h3 y3c ff1 fs1 fc0 sc0 ls15 ws2">2.1<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls1 ws35">CPU Register</span><span class="ls29"> Tests.............................................................................................................<span class="ws30">.............. 5</span><span class="ff4 fs4 ls2"></span></span></div><div class="t m0 x6 h3 y3d ff1 fs1 fc0 sc0 ls15 ws2">2.2<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls1d ws36">Invariable Memory Te<span class="ls1a wsf">st – Flash ROM <span class="_ _1"></span>............................................................................................<span class="_ _1"></span><span class="ls28 ws37"> 12<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y3e ff1 fs1 fc0 sc0 ls15 ws2">2.3<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls14 ws38">Variable memory<span class="ls1e ws39"> - SRAM ........................................................................................................<span class="_ _1"></span><span class="ls2b ws3a">....... 16<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y3f ff1 fs1 fc0 sc0 ls15 ws2">2.4<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls1e ws39">System Clock Test <span class="_ _1"></span>.............................................................................................................<span class="ls2c ws3b">............. 22<span class="_ _1"></span><span class="ff4 fs4 ls2 ws2"></span></span></span></div><div class="t m0 x6 h3 y40 ff1 fs1 fc0 sc0 ls2 ws2">3<span class="ff4 fs4"><span class="_ _c"> </span></span><span class="ls1e ws39">Example Usage <span class="_ _d"></span>.................................................................................................................<span class="ls2c ws3b">.............. 27<span class="_ _1"></span><span class="ff4 fs4 ls2 ws2"></span></span></span></div><div class="t m0 x6 h3 y41 ff1 fs1 fc0 sc0 ls15 ws2">3.1<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="lsd ws3c">CPU Verifi<span class="ls29 ws3d">cation ..............................................................................................................<span class="ls20 ws3e">................ 27</span></span></span><span class="ff4 fs4 ls2"></span></div><div class="t m0 x6 h3 y42 ff1 fs1 fc0 sc0 ls15 ws2">3.2<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls1 ws1">Flash ROM Veri<span class="ls1e ws3f">fication ........................................................................................................<span class="_ _1"></span><span class="ls2c ws3b">........... 28<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y43 ff1 fs1 fc0 sc0 ls15 ws2">3.3<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ws40">RAM Verification <span class="_ _a"></span><span class="ls29 ws2">.............................................................................................................................. <span class="_ _e"></span><span class="ls28">29<span class="ff4 fs4 ls2"></span></span></span></span></div><div class="t m0 x6 h3 y44 ff1 fs1 fc0 sc0 ls15 ws2">3.4<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls1e ws39">System Clock Verification .....................................................................................................<span class="ls6 ws41">.......... 30</span></span><span class="ff4 fs4 ls2"></span></div><div class="t m0 x6 h3 y45 ff1 fs1 fc0 sc0 ls2 ws2">4<span class="ff4 fs4"><span class="_ _c"> </span></span><span class="ls1e ws42">Benchmarking ..................................................................................................................<span class="ls20 ws3e">............... 31</span></span><span class="ff4 fs4"></span></div><div class="t m0 x6 h3 y46 ff1 fs1 fc0 sc0 ls15 ws2">4.1<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls1b ws43">Development En<span class="ls1e ws44">vironment .......................................................................................................<span class="ls2b ws3a">....... 31</span></span></span><span class="ff4 fs4 ls2"></span></div><div class="t m0 x6 h3 y47 ff1 fs1 fc0 sc0 ls15 ws2">4.2<span class="ff4 fs4 ls2"><span class="_ _b"> </span></span><span class="ls2d ws45">IAR Embedded Workbench Settings <span class="_ _a"></span><span class="ls1e ws46">............................................................................................... 31<span class="_ _1"></span><span class="ff4 fs4 ls2 ws2"></span></span></span></div><div class="t m0 x6 h3 y48 ff1 fs1 fc0 sc0 ls2 ws2">5<span class="ff4 fs4"><span class="_ _c"> </span></span><span class="ls29 ws47">Resources .....................................................................................................................<span class="ls20 ws3e">.................. 38</span></span><span class="ff4 fs4"></span></div><div class="t m0 x6 h3 y49 ff1 fs1 fc0 sc0 ls2 ws2">6<span class="ff4 fs4"><span class="_ _c"> </span></span><span class="ls1 ws35">Additional Hardware Resources <span class="_ _a"></span><span class="ls1e ws46">...................................................................................................... 43<span class="_ _1"></span><span class="ff4 fs4 ls2 ws2"></span></span></span></div><div class="t m0 x6 h3 y4a ff1 fs1 fc0 sc0 ls2 ws2">7<span class="ff4 fs4"><span class="_ _c"> </span></span><span class="ls17 ws48">VDE Certificat<span class="ls1e ws39">ion Status <span class="_ _f"></span>......................................................................................................<span class="ls2c ws3b">............ 49<span class="ff4 fs4 ls2 ws2"></span></span></span></span></div><div class="t m0 x6 h3 y4b ff1 fs1 fc0 sc0 ls14 ws38">Website and <span class="ls1e ws49">Support ...........................................................................................................<span class="ls20 ws3e">.................... 50<span class="_ _1"></span><span class="ff4 fs4 ls2 ws2"></span></span></span></div><div class="t m0 x1 h3 y4c ff1 fs1 fc0 sc0 ls2 ws2"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625154c26caf5961923eb047/bg4.jpg"><div class="t m0 x1 h5 y2f ff2 fs3 fc0 sc0 ls23 ws2b">RL78 Family <span class="_ _6"> </span>VDE Certified IE<span class="ls24 ws2c">C60730/60335 Self Test Library </span></div><div class="t m0 x1 h6 y30 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y31 ff1 fs1 fc0 sc0 ls1 ws1">R01AN0749EG020<span class="_ _1"></span>1 Rev.2.01 <span class="_ _7"> </span> <span class="_ _3"> </span>Page 4 of 50 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls1 ws1">Mar 04, 2014 <span class="_ _4"> </span><span class="ls2 ws2"> </span></div><div class="t m0 x1 h5 y35 ff2 fs3 fc0 sc0 ls26 ws4a">1. <span class="_ _10"> </span>Self Test Libraries Introduction </div><div class="t m0 x1 h6 y4d ff3 fs1 fc0 sc0 ls12 ws4b">The self test library (STL) provides sel<span class="_ _1"></span>f test functions cove<span class="ls9 ws4c">ring the CPU registers, i<span class="_ _1"></span>ntern<span class="ls12 ws4b">al memory and system<span class="_ _1"></span> clock. </span></span></div><div class="t m0 x1 h6 y4e ff3 fs1 fc0 sc0 ls14 ws4d">The library test harness provides an <span class="ls2e ws4e">Application Program<span class="_ _1"></span>mers Interface (API) fo<span class="ls9 ws4f">r each <span class="_ _1"></span>of the self test m<span class="_ _1"></span>odules, which </span></span></div><div class="t m0 x1 h6 y4f ff3 fs1 fc0 sc0 ls1b ws20">are described in this applications <span class="ls2f ws50">note<span class="_ _5"></span>. These ca<span class="_ _5"></span>n be used<span class="_ _5"></span> in custo<span class="_ _5"></span>mer’s ap<span class="_ _5"></span>plication wh<span class="_ _5"></span>erever<span class="_ _5"></span> required<span class="_ _5"></span>. </span></div><div class="t m0 x1 h6 y50 ff3 fs1 fc0 sc0 ls9 ws51">For the purposes of VDE cert<span class="_ _1"></span>ification, the self test libra<span class="_ _1"></span><span class="ls14 ws52">ry functions are built as separate m<span class="_ _1"></span>odules. The IAR Embedde<span class="_ _1"></span>d </span></div><div class="t m0 x1 h6 y51 ff3 fs1 fc0 sc0 ls1 ws53">Workbench test harness allows each <span class="_ _1"></span>of the <span class="ls14 ws54">tests functions to be selected in turn<span class="ls2d ws55"> an<span class="_ _1"></span>d run as a stand alone function. In </span></span></div><div class="t m0 x1 h6 y52 ff3 fs1 fc0 sc0 ls2b ws56">order to minimise the affects of the optimisation in the C <span class="ls2d ws57">compiler and minimise resources used, all of t<span class="_ _1"></span>he self test </span></div><div class="t m0 x1 h6 y53 ff3 fs1 fc0 sc0 ls1b ws58">library files have been written in<span class="_ _5"></span> assembler. The default <span class="ls1f ws59">build of the test h<span class="_ _5"></span>arness C files has been built with the </span></div><div class="t m0 x1 h6 y54 ff3 fs1 fc0 sc0 ls13 ws15">optimis<span class="_ _1"></span>ation set to “None” i<span class="_ _1"></span>n the IAR Em<span class="_ _1"></span>bedded work<span class="_ _1"></span>bench. </div><div class="t m0 x1 h6 y55 ff3 fs1 fc0 sc0 ls21 ws5a">All of the STL<span class="_ _1"></span> modules and t<span class="_ _1"></span>est harness fil<span class="_ _1"></span>es are MISRA-C <span class="_ _1"></span>compliant </div><div class="t m0 x1 h6 y56 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y57 ff3 fs1 fc0 sc0 ls2e ws5b">The system hardware require<span class="_ _1"></span>ments includ<span class="ls1c ws21">e that at least two independe<span class="_ _1"></span>nt clock sources are available, e.g. Crystal / </span></div><div class="t m0 x1 h6 y58 ff3 fs1 fc0 sc0 ls17 ws5c">ceramic oscillator and an independ<span class="_ _5"></span>ent oscillator or external<span class="ls29 ws5d"> input source. The requirement is needed to pro<span class="_ _5"></span>vide an </span></div><div class="t m0 x1 h6 y59 ff3 fs1 fc0 sc0 ls30 ws5e">independent cl<span class="_ _1"></span>ock reference f<span class="_ _1"></span>or monitori<span class="_ _1"></span>ng the system<span class="_ _1"></span> clock. The RL78 i<span class="_ _1"></span>s able to pr<span class="_ _1"></span>ovide these usi<span class="_ _1"></span>ng the High s<span class="_ _1"></span>peed </div><div class="t m0 x1 h6 y5a ff3 fs1 fc0 sc0 ls1e ws5f">and Low speed intern<span class="_ _5"></span>al oscillators wh<span class="lsa wsa">ich are in<span class="_ _5"></span>dependent of each other. </span></div><div class="t m0 x1 h6 y5b ff3 fs1 fc0 sc0 ls1c ws21">Equally the application can provide a m<span class="_ _1"></span>ore accurate external <span class="ls2d ws60">reference<span class="_ _1"></span> clock or external cr<span class="ls1c ws21">ystal/resonators for the main </span></span></div><div class="t m0 x1 h6 y5c ff3 fs1 fc0 sc0 ls31 ws61">system cl<span class="_ _1"></span>ock can equall<span class="_ _1"></span>y be used. </div><div class="t m0 x1 h3 y5d ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y5e ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y5f ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y60 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y61 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y62 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y63 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x7 h8 y64 ff2 fs1 fc0 sc0 ls2d ws45">Figure 1 Self Test Library (STL) Confi<span class="_ _1"></span>guration </div><div class="t m0 x1 h6 y65 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y66 ff3 fs1 fc0 sc0 ls5 ws62">The following CPU self test functions are <span class="ls19 ws63">included in the RL78 self test library. </span></div><div class="t m0 x2 h5 y67 ff5 fs3 fc0 sc1 ls2 ws2">•<span class="ff2 sc0"> <span class="_ _10"> </span><span class="ff1 fs1 ls2a ws31">CPU Register<span class="_ _1"></span>s </span></span></div><div class="t m0 x8 h6 y68 ff3 fs1 fc0 sc0 ls15 ws64">The following CPU registers tests are included in this library </div><div class="t m0 x8 h6 y69 ff3 fs1 fc0 sc0 ls2b ws65">All CPU working Registers in all four register<span class="_ _5"></span><span class="ls9 ws66"> banks, Stack Pointer <span class="lsd ws67">(SP), Processor Status </span></span></div><div class="t m0 x8 h6 y6a ff3 fs1 fc0 sc0 ls32 ws68">word (PSW), Ex<span class="_ _5"></span>tension reg<span class="_ _5"></span>isters ES and CS. </div><div class="t m0 x8 h6 y6b ff3 fs1 fc0 sc0 ls2e ws5b">Internal data path are verified as <span class="_ _1"></span>part of the correct operation of these re<span class="_ _1"></span>gister tests </div><div class="t m0 x8 h6 y6c ff3 fs1 fc0 sc0 ls33 ws69">IEC Reference - IEC 60<span class="_ _1"></span>730: 1999+A1:2<span class="_ _1"></span>003 Annex H - Table H.1<span class="_ _1"></span>1.12.7 </div><div class="t m0 x2 h5 y6d ff5 fs3 fc0 sc1 ls2 ws2">•<span class="ff2 sc0"> <span class="_ _10"> </span><span class="ff1 fs1 ls2e ws6a">Invariable Me<span class="_ _1"></span>mory </span></span></div><div class="t m0 x8 h6 y6e ff3 fs1 fc0 sc0 ls1b ws20">This tests the MCU internal Flash memory </div><div class="t m0 x8 h6 y6f ff3 fs1 fc0 sc0 ls33 ws69">IEC Reference - IEC 60<span class="_ _1"></span>730: 1999+A1:2<span class="_ _1"></span>003 Annex H - Table H.1<span class="_ _1"></span>1.12.7 </div><div class="t m0 x2 h5 y70 ff5 fs3 fc0 sc1 ls2 ws2">•<span class="ff2 sc0"> <span class="_ _10"> </span><span class="ff1 fs1 lsc ws6b">Variable Me<span class="_ _1"></span>mory </span></span></div><div class="t m0 x8 h6 y71 ff3 fs1 fc0 sc0 ls1f ws6c">This tests the Internal SRAM memory </div><div class="t m0 x8 h6 y72 ff3 fs1 fc0 sc0 ls33 ws69">IEC Reference - IEC 60<span class="_ _1"></span>730: 1999+A1:2<span class="_ _1"></span>003 Annex H - Table H.1<span class="_ _1"></span>1.12.7 </div><div class="t m0 x2 h5 y73 ff5 fs3 fc0 sc1 ls2 ws2">•<span class="ff2 sc0"> <span class="_ _10"> </span><span class="ff1 fs1 ls2c ws6d">System Clock </span></span></div><div class="t m0 x8 h3 y74 ff3 fs1 fc0 sc0 ls8 wsc">Verifies the sy<span class="_ _1"></span>stem clock ope<span class="_ _1"></span>ration and c<span class="_ _1"></span>orrect frequency<span class="_ _1"></span> against a re<span class="_ _1"></span>ference clock<span class="_ _1"></span><span class="ff1 ls2 ws2"> <span class="ff3 ls34">source</span> </span></div><div class="t m0 x8 h6 y75 ff3 fs1 fc0 sc0 ls33 ws69">IEC Reference - IEC 60<span class="_ _1"></span>730: 1999+A1:2<span class="_ _1"></span>003 Annex H - Table H.1<span class="_ _1"></span>1.12.7 </div><div class="t m1 x9 h9 y76 ff1 fs5 fc0 sc0 ls35 ws2"><span class="fc2 sc0">fi</span><span class="fc2 sc0">n</span></div><div class="t m1 xa ha y77 ff1 fs6 fc0 sc0 ls36 ws2">Sub </div><div class="t m1 xb ha y78 ff1 fs6 fc0 sc0 ls37 ws2">Clock</div><div class="t m2 xc hb y79 ff1 fs7 fc0 sc0 ls38 ws2"><span class="fc2 sc0">HS </span></div><div class="t m2 xd hb y7a ff1 fs7 fc0 sc0 ls39 ws2"><span class="fc2 sc0">O</span><span class="fc2 sc0">s</span><span class="fc2 sc0">c</span><span class="fc2 sc0">i</span><span class="fc2 sc0">l</span><span class="fc2 sc0">l</span><span class="fc2 sc0">at</span><span class="fc2 sc0">or</span></div><div class="t m2 xe hb y7b ff1 fs7 fc0 sc0 ls3a ws2"><span class="fc2 sc0">LS </span></div><div class="t m2 xf hb y7c ff1 fs7 fc0 sc0 ls39 ws2"><span class="fc2 sc0">O</span><span class="fc2 sc0">s</span><span class="fc2 sc0">c</span><span class="fc2 sc0">i</span><span class="fc2 sc0">l</span><span class="fc2 sc0">l</span><span class="fc2 sc0">at</span><span class="fc2 sc0">or</span></div><div class="t m3 x10 hc y7d ff1 fs8 fc0 sc0 ls3b ws2"><span class="fc2 sc0">App</span><span class="fc2 sc0">licat</span><span class="fc2 sc0">i</span><span class="fc2 sc0">o</span><span class="fc2 sc0">n</span></div><div class="t m3 x11 hc y7e ff1 fs8 fc0 sc0 ls3c ws2"><span class="fc2 sc0">So</span><span class="fc2 sc0">ftw</span><span class="_ _1"></span><span class="fc2 sc0">a</span><span class="fc2 sc0">r</span><span class="fc2 sc0">e</span></div><div class="t m3 x12 hc y7f ff1 fs8 fc0 sc0 ls3d ws2"><span class="fc2 sc0">STL</span></div><div class="t m1 x13 ha y80 ff1 fs6 fc0 sc0 ls2 ws2"><span class="fc2 sc0">Ca</span><span class="fc2 sc0">l</span><span class="fc2 sc0">l</span></div><div class="t m1 x14 ha y81 ff1 fs6 fc0 sc0 ls3e ws2"><span class="fc2 sc0">Ret</span><span class="fc2 sc0">u</span><span class="fc2 sc0">r</span><span class="fc2 sc0">n</span></div><div class="t m1 x9 h9 y76 ff1 fs5 fc0 sc0 ls35 ws2">fin</div><div class="t m1 xa ha y77 ff1 fs6 fc0 sc0 ls36 ws2">Sub </div><div class="t m1 xb ha y78 ff1 fs6 fc0 sc0 ls37 ws2">Clock</div><div class="t m2 xc hb y79 ff1 fs7 fc0 sc0 ls38 ws2">HS </div><div class="t m2 xd hb y7a ff1 fs7 fc0 sc0 ls39 ws2">Oscillator</div><div class="t m2 xe hb y7b ff1 fs7 fc0 sc0 ls3a ws2">LS </div><div class="t m2 xf hb y7c ff1 fs7 fc0 sc0 ls39 ws2">Oscillator</div><div class="t m3 x10 hc y7d ff1 fs8 fc0 sc0 ls3b ws2">Application</div><div class="t m3 x11 hc y7e ff1 fs8 fc0 sc0 ls3c ws2">Softw<span class="_ _1"></span>are</div><div class="t m3 x12 hc y7f ff1 fs8 fc0 sc0 ls3d ws2">STL</div><div class="t m1 x13 ha y80 ff1 fs6 fc0 sc0 ls2 ws2">Call</div><div class="t m1 x14 ha y81 ff1 fs6 fc0 sc0 ls3e ws2">Return</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/625154c26caf5961923eb047/bg5.jpg"><div class="t m0 x1 h5 y2f ff2 fs3 fc0 sc0 ls23 ws2b">RL78 Family <span class="_ _6"> </span>VDE Certified IE<span class="ls24 ws2c">C60730/60335 Self Test Library </span></div><div class="t m0 x1 h6 y30 ff3 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y31 ff1 fs1 fc0 sc0 ls1 ws1">R01AN0749EG020<span class="_ _1"></span>1 Rev.2.01 <span class="_ _7"> </span> <span class="_ _3"> </span>Page 5 of 50 </div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls1 ws1">Mar 04, 2014 <span class="_ _4"> </span><span class="ls2 ws2"> </span></div><div class="t m0 x1 h5 y32 ff2 fs3 fc0 sc0 ls26 ws4a">2. <span class="_ _10"> </span>Self Test Library Functions </div><div class="t m0 x1 h5 y82 ff2 fs3 fc0 sc0 ls25 ws2">2.1 <span class="_ _11"> </span><span class="fs4 ls3f ws6e">CPU Register Tests </span></div><div class="t m0 x1 h3 y83 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h6 y84 ff3 fs1 fc0 sc0 ls19 ws6f">This section describes CPU register tests routines. Th<span class="_ _5"></span>e test harness control file ‘<span class="fc3 ls40 ws2">mai<span class="_ _5"></span>n.<span class="_ _5"></span>c</span><span class="lse ws70">’ provides exam<span class="_ _1"></span>ples of the API </span></div><div class="t m0 x1 h6 y85 ff3 fs1 fc0 sc0 ls30 ws5e">for each of t<span class="_ _1"></span>he CPU register t<span class="_ _1"></span>ests using “C” <span class="_ _1"></span>language. </div><div class="t m0 x1 h6 y86 ff3 fs1 fc0 sc0 ls30 ws71">These modules t<span class="_ _1"></span>est the fundam<span class="_ _1"></span>ental aspects of the CPU <span class="_ _1"></span>operation. Each <span class="_ _1"></span>of the API funct<span class="_ _1"></span>ions has a return val<span class="_ _1"></span>ue in order </div><div class="t m0 x1 h6 y87 ff3 fs1 fc0 sc0 ls1d ws23">to indicate the result of a test. </div><div class="t m0 x1 h6 y88 ff3 fs1 fc0 sc0 ls13 ws15">Each of the tes<span class="_ _1"></span>t modules save<span class="_ _1"></span>s the original c<span class="_ _1"></span>ontents of t<span class="_ _1"></span>he register(s<span class="_ _1"></span>) under test<span class="_ _1"></span> and restores the<span class="_ _1"></span> contents on c<span class="_ _1"></span>ompletion.<span class="_ _1"></span> </div><div class="t m0 x1 h6 y89 ff3 fs1 fc0 sc0 ls1c ws72">The following CPU registers are tested: </div><div class="t m0 x15 h3 y8a ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x2 h8 y8b ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff1"> <span class="_ _12"> </span><span class="ff2 ls2e ws6a">Working registers and Accumulator</span><span class="ls19 ws73">: <span class="_ _13"> </span> AX, HL, DE, BC in Register Banks 0 – 3 </span></span></div><div class="t m0 x2 h3 y8c ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x15 h3 y8d ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y8e ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y8f ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y90 ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y91 ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y92 ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y93 ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x15 h3 y94 ff1 fs1 fc0 sc0 ls2 ws2"><span class="fc2 sc0"> </span></div><div class="t m0 x3 h3 y95 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x16 h8 y96 ff2 fs1 fc0 sc0 ls9 ws74">Figure 2 Working Register Configurati<span class="_ _1"></span>on </div><div class="t m0 x15 h3 y97 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x15 h3 y98 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x2 h8 y99 ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff1"> <span class="_ _12"> </span><span class="ff2 ls1d ws36">Stack Pointer</span><span class="ls1f ws75"> (SP) </span></span></div><div class="t m0 x1 h3 y9a ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 y9b ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x3 h3 y9c ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x17 h8 y9d ff2 fs1 fc0 sc0 ls2e ws6a">Figure 3 Stack Pointer Configuration </div><div class="t m0 x2 h3 y9e ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x2 h3 y9f ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x2 h8 ya0 ff5 fs1 fc0 sc0 ls2 ws2">•<span class="ff1"> <span class="_ _12"> </span><span class="ff2 ws76">Processor Status Word</span><span class="ls1e ws39"> (PSW) </span></span></div><div class="t m0 x1 h3 ya1 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x1 h3 ya2 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x18 h3 ya3 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x19 h8 ya4 ff2 fs1 fc0 sc0 ls2e ws6a">Figure 4 PSW Register Configuration </div><div class="t m0 x2 h3 ya5 ff1 fs1 fc0 sc0 ls2 ws2"> </div><div class="t m0 x2 h3 ya6 ff1 fs1 fc0 sc0 ls2 ws2"> </div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>