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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62501b7b6caf596192fb47e0/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">July 2012<span class="_ _0"> </span>Doc ID 15965 Rev <span class="_ _1"></span>6<span class="_ _2"> </span>1/822</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">RM0038</div><div class="t m0 x3 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">Reference man<span class="_ _1"></span>ual</div><div class="t m0 x4 h4 y4 ff1 fs2 fc0 sc0 ls3 ws3">STM32L151xx, STM32L152xx and STM32L162xx</div><div class="t m0 x5 h4 y5 ff1 fs2 fc0 sc0 ls3 ws4"> adv<span class="_ _1"></span>anced ARM-based 32-bit MCUs</div><div class="t m0 x6 h5 y6 ff2 fs3 fc0 sc0 ls4 ws1">Intr<span class="_ _1"></span>oduction</div><div class="t m0 x6 h6 y7 ff1 fs4 fc0 sc0 ls5 ws5">This reference manual targets applicatio<span class="_ _3"></span>n dev<span class="_ _1"></span>e<span class="ls6 ws6">lopers<span class="_ _1"></span>. It pro<span class="_ _1"></span>vides complete inf<span class="_ _1"></span>ormation on </span></div><div class="t m0 x6 h6 y8 ff1 fs4 fc0 sc0 ls7 ws7">how to use the STM3<span class="_ _1"></span>2L151xx, STM32L15<span class="_ _1"></span>2xx and STM32L162xx micro<span class="_ _1"></span>controller memory </div><div class="t m0 x6 h6 y9 ff1 fs4 fc0 sc0 ls8 ws8">and peripherals. Th<span class="ls9 ws9">e STM32L151xx, STM32L<span class="lsa wsa">152xx and STM32L162xx will be ref<span class="_ _1"></span>erred to </span></span></div><div class="t m0 x6 h6 ya ff1 fs4 fc0 sc0 lsb wsb">as STM32L15xxx throug<span class="_ _1"></span>hout the document, unle<span class="_ _1"></span>ss otherwise specifie<span class="_ _1"></span>d.</div><div class="t m0 x6 h6 yb ff1 fs4 fc0 sc0 lsc wsc">The STM32L1<span class="_ _3"></span>5xxx is a f<span class="_ _1"></span>amily of microc<span class="_ _3"></span>ontrollers wi<span class="_ _3"></span>th diff<span class="_ _1"></span>erent memo<span class="_ _3"></span>r<span class="_ _3"></span>y sizes, pac<span class="_ _1"></span>kages and </div><div class="t m0 x6 h6 yc ff1 fs4 fc0 sc0 lsd ws1">peripherals<span class="_ _1"></span>.</div><div class="t m0 x6 h6 yd ff1 fs4 fc0 sc0 lse wsd">F<span class="_ _1"></span>or ordering inf<span class="_ _1"></span>ormation, mechanical and electrical de<span class="_ _1"></span>vice char<span class="_ _1"></span>acteristics please ref<span class="_ _1"></span>er to the </div><div class="t m0 x6 h6 ye ff1 fs4 fc0 sc0 lsf ws1">correspond<span class="_ _3"></span>ing<span class="ff3 ls10"> </span><span class="ls11">datashee<span class="_ _3"></span>ts.</span></div><div class="t m0 x6 h6 yf ff1 fs4 fc0 sc0 ls12 wse">F<span class="_ _1"></span>or inf<span class="_ _1"></span>ormation on progr<span class="_ _1"></span>amming,<span class="_ _1"></span> erasing and pr<span class="_ _1"></span>otection of the int<span class="_ _1"></span>ernal Flash memor<span class="_ _3"></span>y </div><div class="t m0 x6 h6 y10 ff1 fs4 fc0 sc0 lsb wsb">please ref<span class="_ _1"></span>er to t<span class="_ _1"></span>he <span class="ff3 ls13 wsf">STM32L15xxx Flash prog<span class="_ _1"></span>rammin<span class="_ _1"></span>g manual.</span></div><div class="t m0 x6 h6 y11 ff1 fs4 fc0 sc0 ls7 ws7">F<span class="_ _1"></span>or inf<span class="_ _1"></span>ormation on the ARM Cor<span class="_ _3"></span>te<span class="_ _1"></span>x™-M3 core<span class="_ _1"></span>, please ref<span class="_ _1"></span>e<span class="_ _1"></span>r to the <span class="ff3 ls14 ws10">Cor<span class="_ _3"></span>tex™-M3 T<span class="_ _4"></span>echnical </span></div><div class="t m0 x6 h6 y12 ff3 fs4 fc0 sc0 ls15 ws11">Reference Manual<span class="ff1 ls10 ws1">.</span></div><div class="t m0 x6 h5 y13 ff2 fs3 fc0 sc0 ls16 ws12">Related documents</div><div class="t m0 x6 h6 y14 ff1 fs4 fc0 sc0 lsc ws13">A<span class="_ _1"></span>v<span class="_ _1"></span>ailable from <span class="ff3 ls17 ws1">www<span class="_ _5"></span>.arm.<span class="_ _3"></span>com<span class="ff1 ls10">:</span></span></div><div class="t m1 x6 h7 y15 ff4 fs5 fc0 sc0 ls10 ws1">■</div><div class="t m0 x7 h8 y15 ff3 fs4 fc0 sc0 lsb wsb">Cortex™-M3 Technical Re<span class="_ _1"></span>ference Manual, availa<span class="_ _1"></span>ble from:</div><div class="t m2 x6 h6 y16 ff1 fs4 fc0 sc0 ls18 ws1">http://infocenter<span class="_ _5"></span>.ar<span class="_ _3"></span>m.com/help/topic/com.ar<span class="_ _3"></span>m.doc.ddi0337<span class="_ _3"></span>g/DDI0337G_cor<span class="_ _3"></span>tex_m3_r2p0_trm.pd<span class="_ _3"></span>f</div><div class="t m0 x6 h6 y17 ff1 fs4 fc0 sc0 lsc ws13">A<span class="_ _5"></span>vailable from <span class="ff3 ws1">www<span class="_ _5"></span>.st.com<span class="ff1 ls10">:</span></span></div><div class="t m1 x6 h7 y18 ff4 fs5 fc0 sc0 ls10 ws1">■</div><div class="t m0 x7 h8 y18 ff3 fs4 fc0 sc0 lse ws14">STM32L151xx STM32L152xx dat<span class="_ _1"></span>asheets</div><div class="t m1 x6 h7 y19 ff4 fs5 fc0 sc0 ls10 ws1">■</div><div class="t m0 x7 h8 y19 ff3 fs4 fc0 sc0 lsd ws15">STM32L162xx data<span class="_ _1"></span>sheet </div><div class="t m1 x6 h7 y1a ff4 fs5 fc0 sc0 ls10 ws1">■</div><div class="t m0 x7 h8 y1a ff3 fs4 fc0 sc0 ls7 ws7">STM32L15xxx Flash progr<span class="_ _1"></span>amming manual</div><div class="t m0 x6 h9 y1b ff1 fs6 fc0 sc0 ls19 ws1"> </div><div class="t m0 x6 h8 y1c ff2 fs4 fc0 sc0 lsb wsb">T<span class="_ _5"></span>ab<span class="_ _1"></span>le 1.<span class="_ _6"> </span>Applicable pr<span class="_ _5"></span>oducts</div><div class="t m0 x8 ha y1d ff2 fs0 fc0 sc0 ls1a ws16">T<span class="_ _5"></span>ype<span class="_ _7"> </span>Prod<span class="_ _1"></span>uct sub-class</div><div class="t m0 x9 h2 y1e ff1 fs0 fc0 sc0 ls2 ws1">Microcontroller</div><div class="t m0 xa h2 y1f ff1 fs0 fc0 sc0 ls1b ws17">STM32L151xx, STM32L152xx and </div><div class="t m0 xa h2 y20 ff1 fs0 fc0 sc0 ls1c ws1">STM32L162xx</div><div class="t m0 xb hb y21 ff3 fs7 fc1 sc0 ls1d ws1">www<span class="_ _5"></span>.s<span class="_ _3"></span>t.com</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><div class="d m3"></div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62501b7b6caf596192fb47e0/bg2.jpg"><div class="t m0 x1 h8 y22 ff2 fs4 fc0 sc0 ls1e ws1">Contents<span class="_ _8"> </span><span class="ls12">RM0038</span></div><div class="t m0 x1 h2 y23 ff1 fs0 fc0 sc0 ls0 ws0">2/822<span class="_ _2"> </span>Doc ID 15965 Rev 6</div><div class="t m0 x1 hc y24 ff2 fs8 fc0 sc0 ls1f ws1">Contents</div><div class="t m0 x1 hd y25 ff2 fs9 fc0 sc0 ls20 ws18">1<span class="_ _9"> </span>Documentation con<span class="_ _5"></span>ventions <span class="_ _a"> </span> . . . <span class="ls21 ws19">. . . . . . . . . . . . . . . . <span class="ws1a">. . . . . . . . . . . . . . <span class="_ _b"></span>37</span></span></div><div class="t m0 x6 he y26 ff1 fsa fc0 sc0 ls22 ws1">1.1<span class="_ _6"> </span>List of abbre<span class="_ _5"></span>viations for <span class="_ _1"></span>registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>37</div><div class="t m0 x6 he y27 ff1 fsa fc0 sc0 ls22 ws1">1.2<span class="_ _6"> </span>P<span class="_ _5"></span>eripheral av<span class="_ _5"></span>ailability <span class="_ _3"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . <span class="_ _c"> </span>37</div><div class="t m0 x1 hd y28 ff2 fs9 fc0 sc0 ls23 ws1b">2<span class="_ _9"> </span>Memory and bus ar<span class="_ _1"></span>chitecture <span class="_ _c"> </span> . . <span class="ls21 ws19">. . . . . . . . . . . . . . . . <span class="ws1a">. . . . . . . . . . . . . . <span class="_ _b"></span>38</span></span></div><div class="t m0 x6 he y29 ff1 fsa fc0 sc0 ls24 ws1c">2.1<span class="_ _6"> </span>System architecture . <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>38</div><div class="t m0 x6 he y2a ff1 fsa fc0 sc0 ls22 ws1">2.2<span class="_ _6"> </span>Memory organization <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>41</div><div class="t m0 x6 he y2b ff1 fsa fc0 sc0 ls22 ws1">2.3<span class="_ _6"> </span>Memory map <span class="_ _a"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . <span class="_ _c"> </span>41</div><div class="t m0 xc h6 y2c ff1 fs4 fc0 sc0 ls25 ws1d">2.3.1<span class="_ _6"> </span>Emb<span class="_ _3"></span>edded SRAM <span class="_ _e"> </span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 44</div><div class="t m0 xc h6 y2d ff1 fs4 fc0 sc0 ls5 ws1">2.3.2<span class="_ _6"> </span>Bit ba<span class="_ _3"></span>nding <span class="_ _b"></span>. . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 44</div><div class="t m0 xc h6 y2e ff1 fs4 fc0 sc0 ls5 ws1">2.3.3<span class="_ _6"> </span>Emb<span class="_ _3"></span>edded Flash <span class="_ _3"></span>memor<span class="_ _3"></span>y <span class="_ _3"></span> . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . 45</div><div class="t m0 x6 he y2f ff1 fsa fc0 sc0 ls26 ws1e">2.4<span class="_ _6"> </span>Boot configuration <span class="_ _a"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . <span class="_ _c"> </span>53</div><div class="t m0 x1 hd y30 ff2 fs9 fc0 sc0 ls27 ws1f">3<span class="_ _9"> </span>CRC calculation unit <span class="_ _a"> </span>. . . . . . . <span class="ls28 ws20">. . . . . . . . . . . . . . . . . <span class="ls21 ws19">. . . . . . . . . . . . . . . . <span class="_ _b"></span>55</span></span></div><div class="t m0 x6 he y31 ff1 fsa fc0 sc0 ls22 ws1">3.1<span class="_ _6"> </span>CRC introduction <span class="_ _b"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _c"> </span>55</div><div class="t m0 x6 he y32 ff1 fsa fc0 sc0 ls22 ws1">3.2<span class="_ _6"> </span>CRC main f<span class="_ _5"></span>eatures <span class="_ _b"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _c"> </span>55</div><div class="t m0 x6 he y33 ff1 fsa fc0 sc0 ls22 ws1e">3.3<span class="_ _6"> </span>CRC functional description <span class="_ _3"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>55</div><div class="t m0 x6 he y34 ff1 fsa fc0 sc0 ls22 ws1">3.4<span class="_ _6"> </span>CRC registers <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . <span class="_ _c"> </span>56</div><div class="t m0 xc h6 y35 ff1 fs4 fc0 sc0 lsc ws21">3.4.1<span class="_ _6"> </span>Data r<span class="_ _3"></span>egister (CRC_<span class="_ _3"></span>DR) <span class="_ _b"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . 5<span class="_ _3"></span>6</div><div class="t m0 xc h6 y36 ff1 fs4 fc0 sc0 ls25 ws1d">3.4.2<span class="_ _6"> </span>Indep<span class="_ _3"></span>endent data<span class="_ _3"></span> register (CR<span class="_ _3"></span>C_IDR) <span class="_"> </span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 56</div><div class="t m0 xc h6 y37 ff1 fs4 fc0 sc0 lsc ws21">3.4.3<span class="_ _6"> </span>Contro<span class="_ _3"></span>l register (C<span class="_ _3"></span>RC_CR) <span class="_ _b"></span> . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . 57</div><div class="t m0 xc h6 y38 ff1 fs4 fc0 sc0 ls5 ws1">3.4.4<span class="_ _6"> </span>CRC r<span class="_ _3"></span>egister map<span class="_ _3"></span> <span class="_ _e"> </span> . . . . . . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 5<span class="_ _3"></span>7</div><div class="t m0 x1 hd y39 ff2 fs9 fc0 sc0 ls10 ws22">4<span class="_ _9"> </span>P<span class="_ _5"></span>ower contr<span class="_ _1"></span>ol (PWR) <span class="_ _b"></span>. . . . . . . <span class="ls28 ws20">. . . . . . . . . . . . . . . . . <span class="ls21 ws19">. . . . . . . . . . . . . . . . <span class="_ _b"></span>58</span></span></div><div class="t m0 x6 he y3a ff1 fsa fc0 sc0 ls22 ws1">4.1<span class="_ _6"> </span>P<span class="_ _5"></span>ow<span class="_ _1"></span>er supplies <span class="_ _a"> </span>. . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _c"> </span>58</div><div class="t m0 xc h6 y3b ff1 fs4 fc0 sc0 ls12 ws23">4.1.1<span class="_ _6"> </span>Indepe<span class="_ _1"></span>ndent A/D and D<span class="_ _5"></span>A<span class="_ _5"></span>C conv<span class="_ _1"></span>er<span class="_ _3"></span>ter supply and r<span class="_ _1"></span>ef<span class="_ _5"></span>e<span class="_ _3"></span>rence v<span class="_ _5"></span>oltage . . . 59</div><div class="t m0 xc h6 y3c ff1 fs4 fc0 sc0 ls25 ws1d">4.1.2<span class="_ _6"> </span>Indep<span class="_ _3"></span>endent LCD su<span class="_ _3"></span>pply <span class="_ _a"> </span>. . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . 6<span class="_ _3"></span>0</div><div class="t m0 xc h6 y3d ff1 fs4 fc0 sc0 lsc ws21">4.1.3<span class="_ _6"> </span>RTC and R<span class="_ _1"></span>TC backup registers <span class="_ _e"> </span>. . . . . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 60</div><div class="t m0 xc h6 y3e ff1 fs4 fc0 sc0 ls5 ws1">4.1.4<span class="_ _6"> </span>V<span class="_ _5"></span>oltage regula<span class="_ _3"></span>tor <span class="_ _d"></span> . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . <span class="_ _3"></span>61</div><div class="t m0 xc h6 y3f ff1 fs4 fc0 sc0 ls25 ws1d">4.1.5<span class="_ _6"> </span>Dyna<span class="_ _3"></span>mic voltage scaling manage<span class="_ _3"></span>ment <span class="_ _e"> </span> . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. 61</div><div class="t m0 xc h6 y40 ff1 fs4 fc0 sc0 lsc ws21">4.1.6<span class="_ _6"> </span>Dynam<span class="_ _3"></span>ic voltage scaling configuration<span class="_ _3"></span> .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 63</div><div class="t m0 xc h6 y41 ff1 fs4 fc0 sc0 ls7 ws7">4.1.7<span class="_ _6"> </span>V<span class="_ _f"></span>oltage regulat<span class="_ _1"></span>or and cloc<span class="_ _1"></span>k management when VDD drop<span class="_ _1"></span>s</div><div class="t m0 xd h6 y42 ff1 fs4 fc0 sc0 ls25 ws1d">below 2.0<span class="_"> </span>V <span class="_ _e"> </span> . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 64</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return 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<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62501b7b6caf596192fb47e0/bg3.jpg"><div class="t m0 x1 h8 y22 ff2 fs4 fc0 sc0 ls12 ws1">RM0038<span class="_ _8"> </span><span class="ls29">Contents</span></div><div class="t m0 xe h2 y23 ff1 fs0 fc0 sc0 ls2a ws24">Doc ID 15965 Rev <span class="_ _1"></span>6<span class="_ _2"> </span>3/822</div><div class="t m0 xc h6 y43 ff1 fs4 fc0 sc0 lsb wsb">4.1.8<span class="_ _6"> </span>V<span class="_ _f"></span>oltage regulat<span class="_ _1"></span>or and clock man<span class="_ _1"></span>agement when modifyin<span class="_ _1"></span>g the</div><div class="t m0 xd h6 y44 ff1 fs4 fc0 sc0 ls25 ws1d">VCORE range <span class="_ _b"></span> . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . 64</div><div class="t m0 x6 he y45 ff1 fsa fc0 sc0 ls24 ws1c">4.2<span class="_ _6"> </span>P<span class="_ _5"></span>ow<span class="_ _1"></span>er supply supervisor <span class="_ _c"> </span> . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>64</div><div class="t m0 xc h6 y46 ff1 fs4 fc0 sc0 ls5 ws1">4.2.1<span class="_ _6"> </span>P<span class="_ _1"></span>ower on reset (POR)/power down reset <span class="_ _3"></span>(PDR) <span class="_"> </span>. . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 67</div><div class="t m0 xc h6 y47 ff1 fs4 fc0 sc0 ls5 ws1">4.2.2<span class="_ _6"> </span>Brown out re<span class="_ _3"></span>set (BOR) <span class="_ _10"> </span> . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . 6<span class="_ _3"></span>7</div><div class="t m0 xc h6 y48 ff1 fs4 fc0 sc0 lsc ws21">4.2.3<span class="_ _6"> </span>Programmable voltage detector (PVD) <span class="_ _e"> </span> . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . <span class="_ _3"></span>68</div><div class="t m0 xc h6 y49 ff1 fs4 fc0 sc0 lsc ws25">4.2.4<span class="_ _6"> </span>Inter<span class="_ _3"></span>na<span class="_ _3"></span>l v<span class="_ _1"></span>oltage reference (VREFINT)<span class="_ _3"></span> <span class="_ _a"> </span>.<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . <span class="_ _3"></span>. . . 69</div><div class="t m0 x6 he y4a ff1 fsa fc0 sc0 ls22 ws1">4.3<span class="_ _6"> </span>Low<span class="_ _1"></span>-power modes <span class="_ _11"></span> . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>70</div><div class="t m0 xc h6 y4b ff1 fs4 fc0 sc0 ls25 ws1d">4.3.1<span class="_ _6"> </span>Behavior of clocks in low power modes <span class="_ _a"> </span>. . . . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 7<span class="_ _3"></span>1</div><div class="t m0 xc h6 y4c ff1 fs4 fc0 sc0 lsc ws21">4.3.2<span class="_ _6"> </span>Slowing down system<span class="_ _3"></span> clocks <span class="_ _c"> </span>. . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 71</div><div class="t m0 xc h6 y4d ff1 fs4 fc0 sc0 ls25 ws1d">4.3.3<span class="_ _6"> </span>P<span class="_ _1"></span>eripheral clock gating <span class="_ _d"></span>. . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 72</div><div class="t m0 xc h6 y4e ff1 fs4 fc0 sc0 lsf ws26">4.3.4<span class="_ _6"> </span>Low power ru<span class="_ _3"></span>n mode (L<span class="_ _3"></span>P run)<span class="_ _3"></span> <span class="_ _a"> </span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 72</div><div class="t m0 xc h6 y4f ff1 fs4 fc0 sc0 ls5 ws1">4.3.5<span class="_ _6"> </span>Sleep<span class="_ _3"></span> mode <span class="_ _3"></span> . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 7<span class="_ _3"></span>3</div><div class="t m0 xc h6 y50 ff1 fs4 fc0 sc0 ls25 ws1d">4.3.6<span class="_ _6"> </span>Low power sleep mod<span class="_ _3"></span>e (LP sleep) <span class="_ _3"></span>. . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . 74</div><div class="t m0 xc h6 y51 ff1 fs4 fc0 sc0 ls5 ws1">4.3.7<span class="_ _6"> </span>Stop<span class="_ _3"></span> mode <span class="_"> </span>. . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . 7<span class="_ _3"></span>6</div><div class="t m0 xc h6 y52 ff1 fs4 fc0 sc0 ls5 ws1">4.3.8<span class="_ _6"> </span>Stan<span class="_ _3"></span>dby mode <span class="_ _d"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 7<span class="_ _3"></span>7</div><div class="t m0 xc h6 y53 ff1 fs4 fc0 sc0 lsb wsb">4.3.9<span class="_ _6"> </span>W<span class="_ _5"></span>aking up the de<span class="_ _1"></span>vice from Stop and Stan<span class="_ _1"></span>dby mo<span class="_ _1"></span>des using the R<span class="_ _1"></span>TC and</div><div class="t m0 xd h6 y54 ff1 fs4 fc0 sc0 ls5 ws1">comparators <span class="_ _b"></span>. .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 7<span class="_ _3"></span>9</div><div class="t m0 x6 he y55 ff1 fsa fc0 sc0 ls22 ws1">4.4<span class="_ _6"> </span>P<span class="_ _5"></span>ow<span class="_ _1"></span>er control registers <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>80</div><div class="t m0 xc h6 y56 ff1 fs4 fc0 sc0 lsc ws21">4.4.1<span class="_ _6"> </span>PWR p<span class="_ _3"></span>ow<span class="_ _1"></span>er contro<span class="_ _3"></span>l register (PWR<span class="_ _3"></span>_CR) <span class="_ _11"></span> . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . <span class="_ _3"></span>. . . 81</div><div class="t m0 xc h6 y57 ff1 fs4 fc0 sc0 lsc ws21">4.4.2<span class="_ _6"> </span>PWR p<span class="_ _3"></span>ow<span class="_ _1"></span>er contro<span class="_ _3"></span>l/status regis<span class="_ _3"></span>ter (PWR_CSR<span class="_ _3"></span>) <span class="_ _11"></span>. . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 83</div><div class="t m0 xc h6 y58 ff1 fs4 fc0 sc0 ls25 ws1d">4.4.3<span class="_ _6"> </span>PWR re<span class="_ _3"></span>gister map<span class="_ _3"></span> <span class="_"> </span>. . . . . . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . 84</div><div class="t m0 x1 hd y59 ff2 fs9 fc0 sc0 ls2b ws27">5<span class="_ _9"> </span>Reset and c<span class="_ _1"></span>loc<span class="_ _1"></span>k contr<span class="_ _1"></span>ol (RCC) <span class="_ _b"></span>. . <span class="ls21 ws19">. . . . . . . . . . . . . . . . <span class="ws1a">. . . . . . . . . . . . . . <span class="_ _b"></span>85</span></span></div><div class="t m0 x6 he y5a ff1 fsa fc0 sc0 ls22 ws1">5.1<span class="_ _6"> </span>Reset <span class="_ _b"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>85</div><div class="t m0 xc h6 y5b ff1 fs4 fc0 sc0 ls5 ws1">5.1.1<span class="_ _6"> </span>Syste<span class="_ _3"></span>m reset <span class="_ _b"></span> . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 85</div><div class="t m0 xc h6 y5c ff1 fs4 fc0 sc0 ls5 ws1">5.1.2<span class="_ _6"> </span>P<span class="_ _1"></span>ower reset <span class="_ _b"></span> . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 86</div><div class="t m0 xc h6 y5d ff1 fs4 fc0 sc0 ls25 ws1d">5.1.3<span class="_ _6"> </span>RTC and backup registers re<span class="_ _3"></span>set <span class="_ _a"> </span> . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . 8<span class="_ _3"></span>6</div><div class="t m0 x6 he y5e ff1 fsa fc0 sc0 ls22 ws1">5.2<span class="_ _6"> </span>Clock<span class="_ _1"></span>s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>87</div><div class="t m0 xc h6 y5f ff1 fs4 fc0 sc0 ls25 ws1d">5.2.1<span class="_ _6"> </span>HSE clo<span class="_ _3"></span>ck <span class="_ _a"> </span> . . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . <span class="_ _3"></span>89</div><div class="t m0 xc h6 y60 ff1 fs4 fc0 sc0 ls25 ws1d">5.2.2<span class="_ _6"> </span>HSI clo<span class="_ _3"></span>ck <span class="_ _3"></span> . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 90</div><div class="t m0 xc h6 y61 ff1 fs4 fc0 sc0 ls5 ws1">5.2.3<span class="_ _6"> </span>MSI clock <span class="_ _c"> </span>. . . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. 90</div><div class="t m0 xc h6 y62 ff1 fs4 fc0 sc0 ls5 ws1">5.2.4<span class="_ _6"> </span>PLL <span class="_"> </span> . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . <span class="_ _3"></span>91</div><div class="t m0 xc h6 y63 ff1 fs4 fc0 sc0 lsc ws21">5.2.5<span class="_ _6"> </span>LSE clock <span class="_ _b"></span>. . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . 9<span class="_ _3"></span>2</div><div class="t m0 xc h6 y64 ff1 fs4 fc0 sc0 ls5 ws1">5.2.6<span class="_ _6"> </span>LSI c<span class="_ _3"></span>lock <span class="_ _a"> </span> . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 92</div><div class="t m0 xc h6 y65 ff1 fs4 fc0 sc0 ls14 ws10">5.2.7<span class="_ _6"> </span>System clock (SYSCLK) selection <span class="_ _b"></span>. . . . . . . <span class="_ _3"></span>. . . . . . . . . . . . . . . . <span class="_ _3"></span>. . . . . . 93</div><div class="t m0 xc h6 y66 ff1 fs4 fc0 sc0 ls25 ws1d">5.2.8<span class="_ _6"> </span>Syste<span class="_ _3"></span>m clock source freque<span class="_ _3"></span>ncy versus voltage range <span class="_ _b"></span>. . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 93</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62501b7b6caf596192fb47e0/bg4.jpg"><div class="t m0 x1 h8 y22 ff2 fs4 fc0 sc0 ls1e ws1">Contents<span class="_ _8"> </span><span class="ls12">RM0038</span></div><div class="t m0 x1 h2 y23 ff1 fs0 fc0 sc0 ls0 ws0">4/822<span class="_ _2"> </span>Doc ID 15965 Rev 6</div><div class="t m0 xc h6 y43 ff1 fs4 fc0 sc0 lsc ws21">5.2.9<span class="_ _6"> </span>Clock secur<span class="_ _3"></span>ity system (C<span class="_ _3"></span>SS) <span class="_ _a"> </span>. . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . 93</div><div class="t m0 xc h6 y67 ff1 fs4 fc0 sc0 lsc ws25">5.2.10<span class="_ _12"> </span>Clock Security Sys<span class="_ _3"></span>tem on LSE <span class="_ _e"> </span> . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . 94</div><div class="t m0 xc h6 y68 ff1 fs4 fc0 sc0 ls25 ws1d">5.2.11<span class="_ _12"> </span>R<span class="_ _1"></span>TC and LC<span class="_ _3"></span>D clock <span class="_ _a"> </span>. . . . . . . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . 94</div><div class="t m0 xc h6 y69 ff1 fs4 fc0 sc0 ls5 ws1">5.2.12<span class="_ _12"> </span>W<span class="_ _1"></span>atchdog clock <span class="_ _3"></span> . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . 94</div><div class="t m0 xc h6 y6a ff1 fs4 fc0 sc0 ls14 ws10">5.2.13<span class="_ _12"> </span>Cloc<span class="_ _1"></span>k-out capability <span class="_ _3"></span> <span class="_ _3"></span>. . . . . . . . . . . . . <span class="_ _3"></span>. . . . . . . . . . . . . . . . . . <span class="_ _3"></span>. . . . . . . . . 94</div><div class="t m0 xc h6 y6b ff1 fs4 fc0 sc0 ls13 wsf">5.2.14<span class="_ _13"> </span>Internal/external clock measu<span class="_ _1"></span>rement with TIM9/TIM<span class="_ _1"></span>10/TIM11 <span class="_ _b"></span> . . . . . . . 95</div><div class="t m0 xc h6 y6c ff1 fs4 fc0 sc0 ls13 ws28">5.2.15<span class="_ _13"> </span>Clock-in<span class="_ _1"></span>dependent syst<span class="_ _1"></span>em clock <span class="_ _1"></span>sources f<span class="_ _5"></span>or TIM9/TIM10/TIM11 <span class="_ _11"> </span>. . . . . 96</div><div class="t m0 x6 he y6d ff1 fsa fc0 sc0 ls22 ws1">5.3<span class="_ _6"> </span>RCC registers <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . <span class="_ _c"> </span>97</div><div class="t m0 xc h6 y6e ff1 fs4 fc0 sc0 lsc ws21">5.3.1<span class="_ _6"> </span>Clock control re<span class="_ _3"></span>gister (RCC_C<span class="_ _3"></span>R) <span class="_ _d"></span>. . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. 97</div><div class="t m0 xc h6 y6f ff1 fs4 fc0 sc0 ls2c ws29">5.3.2<span class="_ _6"> </span>Inter<span class="_ _3"></span>nal clo<span class="_ _3"></span>ck sources calibration registe<span class="_ _3"></span>r (RCC_ICSCR) <span class="_ _c"> </span>. . . . . . .<span class="_ _3"></span> . . . . 99</div><div class="t m0 xc h6 y70 ff1 fs4 fc0 sc0 lsc ws21">5.3.3<span class="_ _6"> </span>Clock configuration re<span class="_ _3"></span>gister (RCC_C<span class="_ _3"></span>FGR) <span class="_ _11"> </span> . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>100</div><div class="t m0 xc h6 y71 ff1 fs4 fc0 sc0 lsc ws21">5.3.4<span class="_ _6"> </span>Clock interr<span class="_ _3"></span>upt register<span class="_ _3"></span> (RCC_CIR) <span class="_ _c"> </span>. . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . 102</div><div class="t m0 xc h6 y72 ff1 fs4 fc0 sc0 lsc ws25">5.3.5<span class="_ _6"> </span>AHB pe<span class="_ _3"></span>riphe<span class="_ _3"></span>ral reset register<span class="_ _3"></span> (RCC_AHBRSTR) <span class="_ _e"> </span> . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 10<span class="_ _3"></span>5</div><div class="t m0 xc h6 y73 ff1 fs4 fc0 sc0 ls2d ws2a">5.3.6<span class="_ _6"> </span>APB2 peripheral reset register (RCC_APB2RS<span class="_ _3"></span>TR) <span class="_"> </span> . . . . . . . . . . . . . . <span class="_ _3"></span>107</div><div class="t m0 xc h6 y74 ff1 fs4 fc0 sc0 ls2d ws2a">5.3.7<span class="_ _6"> </span>APB1 peripheral reset register (RCC_APB1RS<span class="_ _3"></span>TR) <span class="_"> </span> . . . . . . . . . . . . . . <span class="_ _3"></span>108</div><div class="t m0 xc h6 y75 ff1 fs4 fc0 sc0 ls2c ws29">5.3.8<span class="_ _6"> </span>AHB pe<span class="_ _3"></span>ripheral clock enable register (R<span class="_ _3"></span>CC_AHBENR) <span class="_"> </span> . . . . . . . . . . . <span class="_ _3"></span>111</div><div class="t m0 xc h6 y76 ff1 fs4 fc0 sc0 ls2e ws2b">5.3.9<span class="_ _6"> </span>APB2 peripheral clock enable register (RCC_APB2ENR) <span class="_ _d"></span>. . . . . <span class="_ _3"></span>. . . . . 113</div><div class="t m0 xc h6 y77 ff1 fs4 fc0 sc0 ls2e ws2b">5.3.10<span class="_ _13"> </span>APB1 peripheral clock enable register (RCC_APB1ENR) <span class="_ _b"></span>. . . . . . . . . . 115</div><div class="t m0 xc h6 y78 ff1 fs4 fc0 sc0 ls7 ws7">5.3.11<span class="_ _13"> </span>AHB peripheral cloc<span class="_ _5"></span>k enable in low po<span class="_ _5"></span>wer mode register</div><div class="t m0 xd h6 y79 ff1 fs4 fc0 sc0 ls2f ws25">(RCC_AHBLPENR) <span class="_ _a"> </span>. .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>117</div><div class="t m0 xc h6 y7a ff1 fs4 fc0 sc0 ls30 ws2c">5.3.12<span class="_ _13"> </span>APB2 peripheral clock enab<span class="lsa wsa">le in low po<span class="_ _1"></span>wer mode register</span></div><div class="t m0 xd h6 y7b ff1 fs4 fc0 sc0 ls2f ws25">(RCC_APB2LPENR)<span class="_ _3"></span> <span class="_"> </span>. . . . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 119</div><div class="t m0 xc h6 y7c ff1 fs4 fc0 sc0 ls30 ws2c">5.3.13<span class="_ _13"> </span>APB1 peripheral clock enab<span class="lsa wsa">le in low po<span class="_ _1"></span>wer mode register</span></div><div class="t m0 xd h6 y7d ff1 fs4 fc0 sc0 ls2f ws25">(RCC_APB1LPENR)<span class="_ _3"></span> <span class="_"> </span>. . . . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 121</div><div class="t m0 xc h6 y7e ff1 fs4 fc0 sc0 ls25 ws1d">5.3.14<span class="_ _12"> </span>Control/stat<span class="_ _3"></span>us register <span class="_ _3"></span>(RCC_CSR) <span class="_ _b"></span>. . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . <span class="_ _3"></span>. . 123</div><div class="t m0 xc h6 y7f ff1 fs4 fc0 sc0 ls25 ws1d">5.3.15<span class="_ _12"> </span>RCC register<span class="_ _3"></span> map <span class="_ _11"> </span> . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>126</div><div class="t m0 x1 hd y80 ff2 fs9 fc0 sc0 ls31 ws2d">6<span class="_ _9"> </span>General-purpose I/Os (GPI<span class="ls20 ws22">O) <span class="_ _14"> </span>. . . . . . . . . . </span><span class="ws19">. . . . . . . . . . . . <span class="ws1a">. . . . . . . . . . <span class="_ _b"></span>128</span></span></div><div class="t m0 x6 he y81 ff1 fsa fc0 sc0 ls22 ws1">6.1<span class="_ _6"> </span>GPIO introduction <span class="_ _3"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _c"> </span>128</div><div class="t m0 x6 he y82 ff1 fsa fc0 sc0 ls22 ws1">6.2<span class="_ _6"> </span>GPIO main f<span class="_ _5"></span>eatures <span class="_ _3"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . <span class="_ _c"> </span>128</div><div class="t m0 x6 he y83 ff1 fsa fc0 sc0 ls22 ws1">6.3<span class="_ _6"> </span>GPIO functional description <span class="_"> </span>. . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>128</div><div class="t m0 xc h6 y84 ff1 fs4 fc0 sc0 ls5 ws1">6.3.1<span class="_ _6"> </span>General-p<span class="_ _3"></span>ur<span class="_ _3"></span>pose I/O<span class="_ _3"></span> (GPIO) <span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 13<span class="_ _3"></span>0</div><div class="t m0 xc h6 y85 ff1 fs4 fc0 sc0 lsc ws21">6.3.2<span class="_ _6"> </span>I/O pin<span class="_ _3"></span> multiple<span class="_ _1"></span>xe<span class="_ _1"></span>r and mapp<span class="_ _3"></span>ing <span class="_ _a"> </span> . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 131</div><div class="t m0 xc h6 y86 ff1 fs4 fc0 sc0 ls5 ws1">6.3.3<span class="_ _6"> </span>I/O <span class="_ _3"></span>por<span class="_ _3"></span>t con<span class="_ _3"></span>trol registers <span class="_ _e"> </span> . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 13<span class="_ _3"></span>3</div><div class="t m0 xc h6 y87 ff1 fs4 fc0 sc0 ls5 ws1">6.3.4<span class="_ _6"> </span>I/O <span class="_ _3"></span>por<span class="_ _3"></span>t da<span class="_ _3"></span>ta registers <span class="_ _11"></span> . . . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . 1<span class="_ _3"></span>33</div><div class="t m0 xc h6 y88 ff1 fs4 fc0 sc0 ls25 ws1d">6.3.5<span class="_ _6"> </span>I/O da<span class="_ _3"></span>ta bitwise ha<span class="_ _3"></span>ndling <span class="_"> </span>. . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . 134</div><div class="t m0 xc h6 y89 ff1 fs4 fc0 sc0 lsc ws21">6.3.6<span class="_ _6"> </span>GPIO lo<span class="_ _3"></span>cking mechanism <span class="_ _c"> </span> . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . 134</div><div class="t m0 xc h6 y8a ff1 fs4 fc0 sc0 ls25 ws1d">6.3.7<span class="_ _6"> </span>I/O alte<span class="_ _3"></span>r<span class="_ _3"></span>nate functio<span class="_ _3"></span>n input/outp<span class="_ _3"></span>ut . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . 134</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' 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rel='nofollow' onclick='return false;'><div class="d m3"></div></a><div class="d m3"></div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62501b7b6caf596192fb47e0/bg5.jpg"><div class="t m0 x1 h8 y22 ff2 fs4 fc0 sc0 ls12 ws1">RM0038<span class="_ _8"> </span><span class="ls29">Contents</span></div><div class="t m0 xe h2 y23 ff1 fs0 fc0 sc0 ls2a ws24">Doc ID 15965 Rev <span class="_ _1"></span>6<span class="_ _2"> </span>5/822</div><div class="t m0 xc h6 y43 ff1 fs4 fc0 sc0 ls25 ws1d">6.3.8<span class="_ _6"> </span>Exter<span class="_ _3"></span>n<span class="_ _3"></span>al interru<span class="_ _3"></span>pt/wakeup lines <span class="_ _3"></span> . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . 135</div><div class="t m0 xc h6 y67 ff1 fs4 fc0 sc0 ls5 ws1">6.3.9<span class="_ _6"> </span>Input<span class="_ _3"></span> configuration <span class="_ _a"> </span>. <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>135</div><div class="t m0 xc h6 y68 ff1 fs4 fc0 sc0 ls25 ws1d">6.3.10<span class="_ _12"> </span>Output con<span class="_ _3"></span>figuration <span class="_"> </span> . . . . . . . <span class="_ _3"></span>. . . . . . . . .<span class="_ _3"></span> . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>136</div><div class="t m0 xc h6 y69 ff1 fs4 fc0 sc0 ls25 ws1d">6.3.11<span class="_ _12"> </span>Alter<span class="_ _3"></span>nate fun<span class="_ _3"></span>ction configuration<span class="_ _3"></span> <span class="_ _e"> </span>. <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . 1<span class="_ _3"></span>36</div><div class="t m0 xc h6 y6a ff1 fs4 fc0 sc0 ls25 ws1d">6.3.12<span class="_ _12"> </span>Analog conf<span class="_ _3"></span>iguration <span class="_ _11"> </span> .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>137</div><div class="t m0 xc h6 y6b ff1 fs4 fc0 sc0 ls7 ws7">6.3.13<span class="_ _13"> </span>Using the OSC32_IN/O<span class="_ _1"></span>SC32_OUT pins as GPIO PC14/PC1<span class="_ _1"></span>5</div><div class="t m0 xd h6 y8b ff1 fs4 fc0 sc0 ls5 ws1">por<span class="_ _3"></span>t p<span class="_ _3"></span>ins <span class="_ _b"></span>. . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . 1<span class="_ _3"></span>38</div><div class="t m0 xc h6 y8c ff1 fs4 fc0 sc0 ls7 ws7">6.3.14<span class="_ _13"> </span>Using the OSC_IN/OSC_OUT pin<span class="_ _1"></span>s as GPIO PH0/PH1 por<span class="_ _3"></span>t pins . . . . 138</div><div class="t m0 xc h6 y8d ff1 fs4 fc0 sc0 ls32 ws2e">6.3.15<span class="_ _12"> </span>Selection of <span class="_ _3"></span>R<span class="_ _1"></span>TC_AF1 alter<span class="_ _3"></span>nate fu<span class="_ _3"></span>nctions <span class="_ _d"></span>. . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>138</div><div class="t m0 x6 he y8e ff1 fsa fc0 sc0 ls26 ws1e">6.4<span class="_ _6"> </span>GPIO registers . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . <span class="_ _c"> </span>139</div><div class="t m0 xc h6 y8f ff1 fs4 fc0 sc0 ls2f ws25">6.4.1<span class="_ _6"> </span>GPIO p<span class="_ _3"></span>or<span class="_ _3"></span>t mode<span class="_ _3"></span> register (G<span class="_ _3"></span>PIOx_MODER) (<span class="_ _3"></span>x = A..H) <span class="_ _3"></span> .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 13<span class="_ _3"></span>9</div><div class="t m0 xc h6 y90 ff1 fs4 fc0 sc0 ls29 ws2f">6.4.2<span class="_ _6"> </span>GPIO por<span class="_ _3"></span>t ou<span class="ls17 ws30">tput type register (GPIOx_OTYPER) (x = A..H) . . . . . . . <span class="_ _3"></span>140</span></div><div class="t m0 xc h6 y91 ff1 fs4 fc0 sc0 ls29 ws2f">6.4.3<span class="_ _6"> </span>GPIO por<span class="_ _3"></span>t ou<span class="ls33 ws31">tput speed register (GPIOx_OSPEEDR) </span></div><div class="t m0 xd h6 y92 ff1 fs4 fc0 sc0 ls5 ws1">(x = A..H) <span class="_ _3"></span> . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 140</div><div class="t m0 xc h6 y93 ff1 fs4 fc0 sc0 lsb wsb">6.4.4<span class="_ _6"> </span>GPIO port pull-up/pull-down regi<span class="_ _1"></span>ster (GPIOx_PUPDR)</div><div class="t m0 xd h6 y94 ff1 fs4 fc0 sc0 ls5 ws1">(x = A..H) <span class="_ _3"></span> . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 140</div><div class="t m0 xc h6 y95 ff1 fs4 fc0 sc0 ls2f ws25">6.4.5<span class="_ _6"> </span>GPIO p<span class="_ _3"></span>or<span class="_ _3"></span>t inpu<span class="_ _3"></span>t data registe<span class="_ _3"></span>r (GPIOx_IDR) (<span class="_ _3"></span>x = A..H) <span class="_ _11"> </span> .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 14<span class="_ _3"></span>1</div><div class="t m0 xc h6 y96 ff1 fs4 fc0 sc0 ls34 ws32">6.4.6<span class="_ _6"> </span>GPIO port output data register (GPIOx_ODR)<span class="_ _1"></span> (x = A..H) <span class="_ _11"> </span> . . . . . . . . . . 141</div><div class="t m0 xc h6 y97 ff1 fs4 fc0 sc0 ls2c ws29">6.4.7<span class="_ _6"> </span>GPIO p<span class="_ _3"></span>or<span class="_ _3"></span>t bit set/<span class="_ _3"></span>reset regist<span class="_ _3"></span>er (GPIOx_BSRR) <span class="_ _3"></span>(x = A..H) <span class="_"> </span>. . . . . . . <span class="_ _3"></span>. . 142</div><div class="t m0 xc h6 y98 ff1 fs4 fc0 sc0 ls35 ws33">6.4.8<span class="_ _6"> </span>GPIO port configuration lock<span class="_ _1"></span> register (GPIOx_LCKR)</div><div class="t m0 xd h6 y99 ff1 fs4 fc0 sc0 ls5 ws1">(x = A..H) <span class="_ _3"></span> . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 142</div><div class="t m0 xc h6 y9a ff1 fs4 fc0 sc0 ls13 wsf">6.4.9<span class="_ _6"> </span>GPIO alternate function lo<span class="_ _1"></span>w register<span class="ls2f ws25"> (GPIOx_AFRL) (x = A..<span class="_ _3"></span>H) <span class="_ _e"> </span> . .<span class="_ _3"></span> . . . 143</span></div><div class="t m0 xc h6 y9b ff1 fs4 fc0 sc0 ls5 ws1">6.4.10<span class="_ _12"> </span>GPIO alter<span class="_ _3"></span>n<span class="_ _3"></span>ate functi<span class="_ _3"></span>on high regist<span class="_ _3"></span>er (GPIOx_AF<span class="_ _3"></span>RH)</div><div class="t m0 xd h6 y9c ff1 fs4 fc0 sc0 ls5 ws1">(x = A..H) <span class="_ _3"></span> . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . 144</div><div class="t m0 xc h6 y9d ff1 fs4 fc0 sc0 ls5 ws1">6.4.11<span class="_ _12"> </span>GPIO reg<span class="_ _3"></span>ister map <span class="_ _b"></span>. . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . 1<span class="_ _3"></span>44</div><div class="t m0 x1 hd y9e ff2 fs9 fc0 sc0 ls10 ws34">7<span class="_ _9"> </span>System configuration con<span class="ls36 ws35">troller (SYSCFG) and</span></div><div class="t m0 x6 hd y9f ff2 fs9 fc0 sc0 ls37 ws1b">routing interface (RI) <span class="_ _11"></span>. . . . . . . <span class="ls28 ws20">. . . . . . . . . . . . . . . . . <span class="ls31 ws1">. . . . . . . . . . . . . . . <span class="_ _b"></span>146</span></span></div><div class="t m0 x6 he ya0 ff1 fsa fc0 sc0 ls22 ws1">7.1<span class="_ _6"> </span>SYSCFG and RI introduction <span class="_ _a"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>146</div><div class="t m0 x6 he ya1 ff1 fsa fc0 sc0 ls22 ws1">7.2<span class="_ _6"> </span>RI main f<span class="_ _5"></span>eatures <span class="_ _e"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . <span class="_ _c"> </span>146</div><div class="t m0 x6 he ya2 ff1 fsa fc0 sc0 ls22 ws1">7.3<span class="_ _6"> </span>RI functional description <span class="_ _b"></span>. . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _1"></span> . . . . . . . . . . . . <span class="_ _c"> </span>150</div><div class="t m0 xc h6 ya3 ff1 fs4 fc0 sc0 ls25 ws1d">7.3.1<span class="_ _6"> </span>Spec<span class="_ _3"></span>ial I/O config<span class="_ _3"></span>uration <span class="_ _3"></span> . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>. . 150</div><div class="t m0 xc h6 ya4 ff1 fs4 fc0 sc0 lsf ws26">7.3.2<span class="_ _6"> </span>Input<span class="_ _3"></span> capture ro<span class="_ _3"></span>uting <span class="_ _b"></span> . . . . . . . <span class="_ _3"></span>. . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>153</div><div class="t m0 xc h6 ya5 ff1 fs4 fc0 sc0 ls5 ws1">7.3.3<span class="_ _6"> </span>Reference voltage routing <span class="_ _b"></span> . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . . <span class="_ _3"></span>. . . . . . <span class="_ _3"></span>. . 154</div><div class="t m0 x6 he ya6 ff1 fsa fc0 sc0 ls22 ws1">7.4<span class="_ _6"> </span>RI registers <span class="_ _b"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>155</div><div class="t m0 xc h6 ya7 ff1 fs4 fc0 sc0 ls25 ws1d">7.4.1<span class="_ _6"> </span>RI in<span class="_ _3"></span>put capture r<span class="_ _3"></span>egister (RI_<span class="_ _3"></span>ICR) <span class="_ _a"> </span>. . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . 1<span class="_ _3"></span>55</div><div class="t m0 xc h6 ya8 ff1 fs4 fc0 sc0 lsc ws21">7.4.2<span class="_ _6"> </span>RI ana<span class="_ _3"></span>log switches control regis<span class="_ _3"></span>ter (RI_ASCR1) <span class="_ _11"> </span>. . .<span class="_ _3"></span> . . . . . . . .<span class="_ _3"></span> . . . . . . <span class="_ _3"></span>157</div><div class="t m0 xc h6 ya9 ff1 fs4 fc0 sc0 lsc ws25">7.4.3<span class="_ _6"> </span>RI ana<span class="_ _3"></span>log switch control register 2<span class="_ _3"></span> (RI_ASCR2) <span class="_ _b"></span> . . . . . . . . . <span class="_ _3"></span>. . . . . . . . <span class="_ _3"></span>159</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' 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