CH03_EMIO.rar_7035_MIZ7035 EMIO Example_Linux/Unix编程下载-pudn.com

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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622bada83d2fbb0007d19d48/bg2.jpg"><div class="t m0 x2 h5 y5 ff3 fs2 fc0 sc0 ls3 ws3">Zynq-7<span class="_ _2"></span>000 AP SoC T<span class="_ _2"></span>echnical R<span class="_ _2"></span>eference Man<span class="_ _3"></span>ual<span class="_ _4"> </span><span class="ff4 fc1 ls4 ws0">www<span class="_ _0"></span>.xilinx<span class="_ _3"></span>.co<span class="_ _3"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls5">2</span></span></div><div class="t m0 x2 h6 y6 ff4 fs2 fc0 sc0 ls6 ws4">U<span class="_ _3"></span>G585 (v1.10) Febru<span class="_ _3"></span>ary 23, 2015</div><div class="t m0 x2 h7 y7 ff1 fs3 fc0 sc0 ls7 ws5">Notice of Disclaimer</div><div class="t m0 x2 h8 y8 ff5 fs3 fc0 sc0 ls8 ws6">The inform<span class="_ _3"></span>ation disclo<span class="_ _3"></span>sed to yo<span class="_ _3"></span>u hereun<span class="_ _3"></span>der (the “Mat<span class="_ _3"></span>erials”<span class="_ _3"></span>) is prov<span class="_ _3"></span>ided sole<span class="_ _3"></span>ly for the selec<span class="_ _3"></span>tion and use o<span class="_ _2"></span>f X<span class="_ _6"></span>ilinx pr<span class="_ _3"></span>oduct<span class="_ _3"></span>s. T<span class="_ _0"></span><span class="ls9 ws7">o the maximum </span></div><div class="t m0 x2 h8 y9 ff5 fs3 fc0 sc0 lsa ws8">extent permitted by applicable law: (1) Materials are ma<span class="_ _3"></span>de avai<span class="_ _2"></span><span class="lsb ws9">lable "AS IS" and with all fault<span class="_ _3"></span>s, X<span class="_ _6"></span>il<span class="_ _3"></span>inx hereb<span class="_ _3"></span>y DISCLAIMS ALL W<span class="lsc ws0">ARRANTIES<span class="_ _3"></span> </span></span></div><div class="t m0 x2 h8 ya ff5 fs3 fc0 sc0 lsd wsa">AND CONDITIONS, EXP<span class="_ _6"></span>RESS, IMPLIED<span class="_ _2"></span>, OR ST<span class="_ _2"></span>A<span class="_ _2"></span>TUTOR<span class="_ _3"></span>Y<span class="_ _0"></span>,<span class="_ _6"></span> INCLUDING BUT NO<span class="_ _2"></span>T L<span class="_ _6"></span>IMITED T<span class="_ _2"></span>O WARRANTIES OF MERCHANT<span class="_ _2"></span>ABILIT<span class="_ _6"></span>Y<span class="_ _0"></span>, </div><div class="t m0 x2 h8 yb ff5 fs3 fc0 sc0 lse wsb">NON-INFRINGE<span class="_ _6"></span>MENT<span class="_ _2"></span>, OR FITNE<span class="lsf wsc">SS FOR ANY P<span class="_ _2"></span>ARTICULAR PURPOSE; and (2<span class="_ _6"></span><span class="ls10 wsd">) Xilinx<span class="_ _6"></span> shall not be liable (whe<span class="lse wsb">ther <span class="_ _6"></span>in contract or tor<span class="_ _6"></span>t, inclu<span class="ls11 ws0">ding </span></span></span></span></div><div class="t m0 x2 h8 yc ff5 fs3 fc0 sc0 ls12 wse">negligence, or under any other t<span class="_ _6"></span>heory of liability) for any loss or<span class="ls13 wsf"> dama<span class="_ _6"></span>ge o<span class="_ _3"></span>f any kind or n<span class="_ _6"></span>ature r<span class="_ _3"></span>elated to, arising unde<span class="_ _6"></span>r<span class="_ _0"></span>, or <span class="ls12 wse">in connection<span class="_ _6"></span> with, </span></span></div><div class="t m0 x2 h8 yd ff5 fs3 fc0 sc0 ls14 ws10">the Material<span class="_ _6"></span>s (including your use<span class="_ _6"></span> o<span class="_ _3"></span>f the Materia<span class="_ _6"></span>ls), including for any<span class="_ _6"></span> direct, indirect, special,<span class="_ _6"></span> incidental, or consequential <span class="_ _6"></span><span class="ls15 ws11">loss<span class="_ _3"></span> or damage </span></div><div class="t m0 x2 h8 ye ff5 fs3 fc0 sc0 ls16 ws0">(<span class="_ _6"></span>i<span class="_ _6"></span>n<span class="_ _6"></span>c<span class="_ _6"></span>l<span class="_ _6"></span>u<span class="_ _6"></span>d<span class="_ _6"></span>i<span class="_ _6"></span>n<span class="_ _6"></span>g<span class="_ _6"></span> lo<span class="_ _6"></span>s<span class="_ _6"></span>s<span class="_ _6"></span> o<span class="_ _6"></span>f<span class="_ _6"></span> d<span class="_ _6"></span>a<span class="_ _6"></span>t<span class="_ _6"></span>a<span class="_ _6"></span>, <span class="_ _6"></span>pr<span class="_ _6"></span>o<span class="_ _6"></span>f<span class="_ _7"></span>i<span class="_ _6"></span>t<span class="_ _6"></span>s,<span class="_ _6"></span> g<span class="_ _6"></span>o<span class="_ _6"></span>o<span class="_ _6"></span>d<span class="_ _6"></span>w<span class="_ _6"></span>i<span class="_ _6"></span>l<span class="_ _6"></span>l<span class="_ _6"></span>,<span class="_ _6"></span> o<span class="_ _6"></span>r<span class="_ _6"></span> a<span class="_ _6"></span>n<span class="_ _6"></span>y<span class="_ _6"></span> t<span class="_ _6"></span>y<span class="_ _6"></span>p<span class="_ _6"></span>e<span class="_ _6"></span> of<span class="_ _6"></span> l<span class="_ _6"></span>o<span class="_ _6"></span>s<span class="_ _6"></span>s<span class="_ _6"></span> o<span class="_ _6"></span>r<span class="_ _6"></span> d<span class="_ _6"></span>a<span class="_ _6"></span>m<span class="_ _6"></span>a<span class="_ _6"></span>g<span class="_ _6"></span>e<span class="_ _6"></span> s<span class="_ _6"></span>u<span class="_ _6"></span>f<span class="_ _6"></span>f<span class="_ _6"></span>e<span class="_ _6"></span>re<span class="_ _6"></span>d<span class="_ _6"></span> a<span class="_ _6"></span>s<span class="_ _6"></span> a<span class="_ _6"></span> r<span class="_ _6"></span>e<span class="_ _6"></span>s<span class="_ _6"></span>u<span class="_ _6"></span>l<span class="_ _6"></span>t<span class="_ _6"></span> of<span class="_ _6"></span> a<span class="_ _6"></span>n<span class="_ _6"></span>y<span class="_ _6"></span> a<span class="_ _6"></span>c<span class="_ _6"></span>t<span class="_ _6"></span>i<span class="_ _6"></span>o<span class="_ _6"></span>n<span class="_ _6"></span> b<span class="_ _6"></span>r<span class="_ _6"></span>ou<span class="_ _6"></span>g<span class="_ _6"></span>h<span class="_ _6"></span>t<span class="_ _6"></span> b<span class="_ _6"></span>y<span class="_ _6"></span> a<span class="_ _6"></span> t<span class="_ _6"></span>h<span class="_ _6"></span>i<span class="_ _6"></span>r<span class="_ _6"></span>d<span class="_ _6"></span><span class="ls15 ws12"> party) even if such </span></div><div class="t m0 x2 h8 yf ff5 fs3 fc0 sc0 ls17 ws13">damage or loss was reasonably foreseeable or Xili<span class="_ _6"></span>nx had been a<span class="_ _3"></span>d<span class="ls18 ws14">vised of the pos<span class="_ _6"></span>sibility of the <span class="ls19 ws15">same. X<span class="_ _6"></span>ilinx as<span class="_ _3"></span>sumes no obligati<span class="ls1a ws16">on to correct </span></span></span></div><div class="t m0 x2 h8 y10 ff5 fs3 fc0 sc0 ls1b ws17">any errors con<span class="_ _3"></span>tained in<span class="_ _3"></span> the Materi<span class="_ _3"></span>als or to notify you o<span class="_ _3"></span>f updates t<span class="_ _3"></span>o the Materials or t<span class="_ _2"></span>o <span class="_ _6"></span>pr<span class="_ _2"></span>oduct specif<span class="_ _6"></span>ications. Y<span class="_ _0"></span>ou may not re<span class="_ _3"></span><span class="ls1c ws0">produce, </span></div><div class="t m0 x2 h8 y11 ff5 fs3 fc0 sc0 ls1d ws18">modify, distribute, or public<span class="_ _6"></span>ly display the Materials <span class="_ _6"></span>without prior written co<span class="_ _6"></span>nsent. Certain products are subject to th<span class="_ _6"></span>e terms <span class="ls1e ws19">and conditions </span></div><div class="t m0 x2 h8 y12 ff5 fs3 fc0 sc0 ls1f ws1a">of Xilinx<span class="_ _6"></span>’<span class="_ _2"></span>s limited warranty<span class="_ _2"></span>, p<span class="_ _6"></span>lea<span class="_ _3"></span>se refer to X<span class="_ _6"></span>ilinx’<span class="_ _2"></span>s T<span class="_ _0"></span>erms of Sale which can be viewed at <span class="fc1 ls20 ws0">ht<span class="_ _6"></span>tp:/<span class="_ _3"></span>/www<span class="_ _3"></span>.xilinx.com/legal.htm#tos</span></div><div class="t m0 x3 h8 y13 ff5 fs3 fc0 sc0 ls21 ws1b">; IP cores m<span class="_ _3"></span>ay be </div><div class="t m0 x2 h8 y14 ff5 fs3 fc0 sc0 lsd ws1c">subject to war<span class="_ _6"></span>ranty and suppor<span class="_ _6"></span>t terms con<span class="_ _6"></span>t<span class="_ _2"></span>ai<span class="_ _6"></span>ned in a license issu<span class="_ _6"></span>ed to you by X<span class="_ _6"></span>ilinx. X<span class="_ _6"></span>ilinx products are not designe<span class="_ _6"></span>d or intended to be </div><div class="t m0 x2 h8 y15 ff5 fs3 fc0 sc0 ls22 ws1d">fail-safe or for use in any ap<span class="_ _6"></span>plication requiring fail-safe per<span class="_ _6"></span>for<span class="ls17 ws1e">mance; you assume sole ris<span class="_ _6"></span>k and liability for use of X<span class="_ _6"></span>ilinx p<span class="ls23 ws1f">roduct<span class="_ _3"></span>s in such </span></span></div><div class="t m0 x2 h8 y16 ff5 fs3 fc0 sc0 ls22 ws20">critical app<span class="_ _6"></span>lications, please r<span class="_ _3"></span>efer to Xi<span class="_ _6"></span>linx’<span class="_ _2"></span>s T<span class="_ _0"></span>erms of Sale which can be viewed at <span class="fc1 ls1f ws0">http://www.xilinx.com/legal.htm#tos</span></div><div class="t m0 x4 h8 y17 ff5 fs3 fc0 sc0 ls5 ws0">.</div><div class="t m0 x2 h8 y18 ff5 fs3 fc0 sc0 ls24 ws21">© Copyright 2012–2015 X<span class="_ _6"></span>ilinx, Inc.<span class="_ _3"></span> X<span class="_ _6"></span>ilinx, the Xilin<span class="_ _6"></span>x <span class="_ _3"></span>logo, Ar<span class="_ _6"></span>tix, ISE, Kintex, Spartan, V<span class="_ _6"></span>irtex, V<span class="_ _6"></span>iv<span class="_ _3"></span>ado, Z<span class="_ _2"></span>ynq, and other design<span class="ls25 ws22">ated brands </span></div><div class="t m0 x2 h8 y19 ff5 fs3 fc0 sc0 ls22 ws20">included herein are trademarks of Xilinx in the United Stat<span class="_ _3"></span>es an<span class="ls1a ws23">d other countries.<span class="_ _6"></span> All other trademarks are the property of the<span class="ls26 ws24">ir respecti<span class="_ _3"></span>ve </span></span></div><div class="t m0 x2 h8 y1a ff5 fs3 fc0 sc0 ls27 ws0">owners.</div><div class="t m0 x2 h9 y1b ff3 fs4 fc0 sc0 ls28 ws25">R<span class="_ _3"></span>evision His<span class="_ _2"></span>tory</div><div class="t m0 x2 ha y1c ff5 fs2 fc0 sc0 ls29 ws26">The following table shows the revision histor<span class="_ _6"></span>y for this document. Chan<span class="_ _6"></span>ge b<span class="_ _2"></span>a<span class="_ _6"></span>rs indicate the latest revisions.</div><div class="t m0 x2 hb y1d ff4 fs5 fc0 sc0 ls5 ws0"> </div><div class="t m0 x5 h5 y1e ff3 fs2 fc0 sc0 ls2a ws0">Date<span class="_ _8"> </span>V<span class="_ _2"></span>ersion<span class="_ _9"> </span>Revision</div><div class="t m0 x6 hc y1f ff5 fs6 fc0 sc0 ls2b ws27">04/08/2012<span class="_ _a"> </span>1.0<span class="_ _b"> </span> X<span class="_ _6"></span>ilinx initial r<span class="_ _3"></span>elease.</div><div class="t m0 x6 hc y20 ff5 fs6 fc0 sc0 ls2c ws28">06/25/2012<span class="_ _a"> </span>1.1<span class="_ _b"> </span>Remov<span class="_ _3"></span>ed Chapter 30, Boar<span class="ls2d ws29">d Design (now part of UG933, <span class="ff6 ls2e ws2a">Zynq-7000 All <span class="_ _6"></span>Pr<span class="_ _3"></span>ogrammable </span></span></div><div class="t m0 x7 hd y21 ff6 fs6 fc0 sc0 ls2f ws2b">SoC PCB Design and P<span class="_ _3"></span>in Planning Guide).</div><div class="t m0 x6 ha y22 ff5 fs6 fc0 sc0 ls30 ws2c">08/08/2012<span class="_ _a"> </span>1.2<span class="_ _b"> </span>Added information about the <span class="fs2 ls31 ws2d">7z010 CLG225 dev<span class="_ _3"></span>ice and refer<span class="_ _3"></span>ences to section </span></div><div class="t m0 x7 ha y23 ff5 fs2 fc1 sc0 ls32 ws2e">2.5.4<span class="_ _c"> </span>MIO-at<span class="_ _2"></span>-a-Glance T<span class="_ _d"></span>able<span class="fc0 ls33 ws2f"> throughout document. </span></div><div class="t m0 x8 hc y24 ff5 fs6 fc0 sc0 ls34 ws30">Added sectio<span class="_ _6"></span>n headings </div><div class="t m0 x7 hc y25 ff5 fs6 fc1 sc0 ls35 ws31">1.1.1<span class="_ _e"> </span>Block Diagram<span class="fc0 ls36 ws32"> and </span><span class="ls37 ws33">1.1.2<span class="_ _f"> </span>Documen<span class="_ _3"></span>tati<span class="_ _3"></span>on R<span class="_ _2"></span>esources<span class="fc0 ls38 ws34">, a<span class="_ _3"></span>dded sections <span class="fc1 ls39 ws0">1.1.3<span class="_ _f"> </span>Notices<span class="fc0 ls5"> </span></span></span></span></div><div class="t m0 x7 hc y26 ff5 fs6 fc0 sc0 ls36 ws0">and <span class="fc1 ls30 ws2c">T<span class="_ _0"></span>rustZon<span class="_ _6"></span>e Cap<span class="_ _3"></span>abilities<span class="fc0 ls3a ws35">, and clarif<span class="_ _6"></span>ied </span><span class="ls2e ws36">PS MIO I/Os <span class="fc0 ls3b ws0">in <span class="_ _6"></span><span class="fc1 ls3c">Ch<span class="_ _3"></span>apter<span class="_ _10"> </span>1<span class="fc0 ls38 ws37">. Updated </span><span class="ls3d">Ta<span class="_ _6"></span>b<span class="_ _11"> </span>l<span class="_ _7"></span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _7"></span>1<span class="_ _11"> </span><span class="fc0 ls3e">. </span></span></span></span></span></span></div><div class="t m0 x7 hc y27 ff5 fs6 fc0 sc0 ls3f ws0">Changed <span class="ff6 ls40 ws27">2.4.2 MIO-EMIO Connections<span class="ff5 ws38"> heading to <span class="fc1 ls41 ws39">2.5.2<span class="_ _f"> </span>IOP Interface Connections</span><span class="ls36 ws3a"> and </span></span></span></div><div class="t m0 x7 hc y28 ff5 fs6 fc0 sc0 ls42 ws3b">clarif<span class="_ _6"></span>ied f<span class="_ _6"></span>irst paragraph. Updat<span class="_ _3"></span>ed <span class="fc1 ls43 ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _7"></span>4<span class="_ _7"></span></span><span class="ls38 ws3c">. Added section <span class="fc1 ls30 ws3d">2.7.1<span class="_ _f"> </span>Clocks and Reset<span class="_ _3"></span>s<span class="fc0 ls3b ws3e"> and </span></span></span></div><div class="t m0 x7 hc y29 ff5 fs6 fc1 sc0 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _7"></span>7<span class="_ _7"></span><span class="fc0 ls44 ws3f">, an<span class="_ _6"></span>d updated </span>Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _7"></span>1<span class="_ _7"></span>3<span class="_ _11"> </span><span class="fc0 ls5"> </span><span class="ls2e ws40">PS MIO I/Os <span class="_ _6"></span></span><span class="fc0 ls45">in <span class="_ _2"></span><span class="fc1 ls3c">Chapter<span class="_"> </span>2<span class="fc0 ls45 ws41">. Added note under </span><span class="ls46">Branch </span></span></span></div><div class="t m0 x7 hc y2a ff5 fs6 fc1 sc0 ls46 ws0">Prediction<span class="fc0 ls36 ws3a"> and </span><span class="ls43">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>3<span class="_ _7"></span>-<span class="_ _7"></span>8<span class="_ _7"></span><span class="fc0 ls41 ws39"> in </span><span class="ls47">Chap<span class="_ _6"></span>ter<span class="_"> </span>3<span class="fc0 ls48 ws42">. Updated <span class="_ _3"></span><span class="fc1 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>4<span class="_ _7"></span>-<span class="_ _7"></span>1<span class="_ _7"></span><span class="fc0 ls2c ws43"> in <span class="_ _6"></span></span><span class="ls45">Chapter<span class="_"> </span>4<span class="fc0 ls38 ws44">. Added section </span></span></span></span></span></span></div><div class="t m0 x7 hc y2b ff5 fs6 fc1 sc0 ls49 ws45">5.1.7<span class="_ _e"> </span>Read/Write Request Capabil<span class="_ _6"></span>ity<span class="fc0 ls2c ws43"> in </span><span class="ls45 ws0">Chapter<span class="_"> </span>5<span class="fc0 ls48 ws46">. Updated </span></span></div><div class="t m0 x9 ha y2c ff5 fs2 fc1 sc0 ls4a ws47">NAND Boot<span class="fc0 ls4b ws48"> MIO pin </span></div><div class="t m0 x7 ha y2d ff5 fs2 fc0 sc0 ls4c ws49">assignment<span class="_ _3"></span>s and </div><div class="t m0 xa hc y2e ff5 fs6 fc1 sc0 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>6<span class="_ _7"></span>-<span class="_ _7"></span>6<span class="_ _7"></span><span class="fc0 ls3b ws4a"> in </span><span class="ls47">Chap<span class="_ _6"></span>ter<span class="_"> </span>6<span class="fc0 ls41 ws4b">. Updated section <span class="_ _3"></span><span class="fc1 ws4c">7.1.5<span class="_ _f"> </span>CPU Interrupt Signal </span></span></span></div><div class="t m0 x7 hc y2f ff5 fs6 fc1 sc0 ls46 ws0">P<span class="_ _3"></span>ass-thr<span class="_ _3"></span>ough<span class="fc0 ls41 ws4b"> in </span><span class="ls45">Chapter<span class="_"> </span>7<span class="fc0 ls3f ws4d">. Added section heading <span class="_ _3"></span><span class="fc1 ws0">10.1.1<span class="_ _f"> </span>Features<span class="fc0 ls36 ws4e"> and added section </span></span></span></span></div><div class="t m0 x7 hc y30 ff5 fs6 fc1 sc0 ls45 ws0">10.1.3<span class="_ _e"> </span>Notices<span class="fc0 ls2c ws43"> in </span><span class="ls2c">Chapter<span class="_ _13"> </span>10<span class="fc0 ls48 ws42">. Updated <span class="_ _3"></span><span class="fc1 ls2b ws27">Parallel (SRAM/NOR) Interface<span class="fc0 ls4d ws4f"> featur<span class="_ _2"></span>es list and </span></span></span></span></div><div class="t m0 x7 hc y31 ff5 fs6 fc0 sc0 ls47 ws50">added section <span class="fc1 ls4e ws0">11.1.3<span class="_ _14"> </span>Notices</span><span class="ls41 ws4b"> in <span class="fc1 ls45 ws0">Chapter<span class="_"> </span>11</span><span class="ws39">. Reor<span class="_ _2"></span>ganized, clarif<span class="_ _6"></span>ied, and expanded </span></span></div><div class="t m0 x7 hc y32 ff5 fs6 fc1 sc0 ls45 ws0">Chapter<span class="_"> </span>12<span class="fc0 ls2f ws51"> to include pr<span class="_ _2"></span>ogramming models (added sections <span class="_ _3"></span><span class="fc1 ls35 ws0">12.1.4<span class="_ _f"> </span>Notices<span class="fc0">, </span></span></span></div><div class="t m0 x7 hc y33 ff5 fs6 fc1 sc0 ls35 ws52">12.3<span class="_ _e"> </span>Programming Guide<span class="fc0 ls48 ws46">, and </span><span class="ls4f ws53">12.5.2<span class="_ _f"> </span>MIO Programmi<span class="_ _3"></span>ng<span class="fc0 ls38 ws44">). Added last note in section </span></span></div><div class="t m0 x7 hc y34 ff5 fs6 fc1 sc0 ls46 ws54">13.3.4<span class="_ _e"> </span>Using ADMA<span class="_ _6"></span><span class="fc0 ls41 ws4b"> in </span><span class="ls3c ws0">Ch<span class="_ _3"></span>apter<span class="_ _10"> </span>13<span class="fc0 ls48 ws46">. Added </span><span class="ls50">Res<span class="_ _6"></span>t<span class="_ _6"></span>r<span class="_ _6"></span>ic<span class="_ _6"></span>t<span class="_ _6"></span>io<span class="_ _6"></span>n<span class="_ _6"></span>s<span class="fc0 ls2c ws43"> in </span><span class="ls45">Chap<span class="_ _6"></span>te<span class="_ _3"></span>r<span class="_"> </span>14<span class="fc0 ls51 ws55">. Clarif<span class="_ _7"></span>ied f<span class="_ _6"></span>ir<span class="_ _6"></span>st </span></span></span></span></div><div class="t m0 x7 hc y35 ff5 fs6 fc0 sc0 ls52 ws56">paragraph, add<span class="_ _6"></span>ed section <span class="fc1 ls45 ws0">15.1.3<span class="_ _e"> </span>Notices</span><span class="ls2f ws57">, and clarif<span class="_ _6"></span>ied <span class="fc1 ls53 ws0">Fig<span class="_ _2"></span>ur<span class="_ _3"></span>e<span class="_ _10"> </span>15<span class="_ _2"></span>-7<span class="fc0 ls54 ws58"> thr<span class="_ _3"></span>ough </span></span></span></div><div class="t m0 x7 hc y36 ff5 fs6 fc1 sc0 ls55 ws0">Figure<span class="_"> </span>15-17<span class="fc0 ls2c ws43"> in </span><span class="ls45">Chapter<span class="_"> </span>15<span class="fc0 ls38 ws44">. Added section </span>16.1.4<span class="_ _e"> </span>Notices<span class="_ _6"></span><span class="fc0 ls3b ws4a"> in </span><span class="ls3c">Chapte<span class="_ _3"></span>r<span class="_"> </span>16<span class="fc0 ls2f ws57">. Clarif<span class="_ _6"></span>ied </span></span></span></div><div class="t m0 x7 hc y37 ff5 fs6 fc0 sc0 ls4e ws0">sections <span class="fc1 ls2c ws43">17.2.5<span class="_ _e"> </span>SPI FIFOs<span class="_ _6"></span></span><span class="ls3e">, <span class="fc1 ls2e ws36">17.2.6<span class="_ _f"> </span>SPI Clocks<span class="_ _6"></span></span><span class="ls48 ws46">, and <span class="fc1 ls46 ws59">17.2.7<span class="_ _f"> </span>SPI EMIO <span class="_ _6"></span>Considerations</span><span class="ls2c ws43"> in </span></span></span></div><div class="t m0 x7 hc y38 ff5 fs6 fc1 sc0 ls45 ws0">Chapter<span class="_"> </span>17<span class="fc0 ls41 ws4b">. R<span class="_ _3"></span>eorganized, c<span class="_ _3"></span>larif<span class="_ _6"></span>ied, and expanded <span class="_ _2"></span><span class="fc1 ls47 ws0">Ch<span class="_ _6"></span>apter<span class="_"> </span>18<span class="fc0 ls56 ws5a"> to include pr<span class="_ _3"></span>ogramming </span></span></span></div><div class="t m0 x7 hc y39 ff5 fs6 fc0 sc0 ls34 ws30">models (adde<span class="_ _6"></span>d sections <span class="fc1 ls45 ws0">18.1.4<span class="_ _f"> </span>Notices</span><span class="ls36 ws3a"> and <span class="_ _6"></span><span class="fc1 ls2d ws29">18.5.1<span class="_ _f"> </span>MIO Programming</span><span class="ls57 ws0">).</span></span></div><div class="c xb y3a w2 he"><div class="t m1 xc hf y3b ff7 fs7 fc2 sc0 ls5 ws0"><span class="fc3 sc0">Send F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">edback</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' 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class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622bada83d2fbb0007d19d48/bg3.jpg"><div class="t m0 x2 h5 y5 ff3 fs2 fc0 sc0 ls3 ws3">Zynq-7<span class="_ _2"></span>000 AP SoC T<span class="_ _2"></span>echnical R<span class="_ _2"></span>eference Man<span class="_ _3"></span>ual<span class="_ _4"> </span><span class="ff4 fc1 ls4 ws0">www<span class="_ _0"></span>.xilinx<span class="_ _3"></span>.co<span class="_ _3"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls5">3</span></span></div><div class="t m0 x2 h6 y6 ff4 fs2 fc0 sc0 ls6 ws4">U<span class="_ _3"></span>G585 (v1.10) Febru<span class="_ _3"></span>ary 23, 2015</div><div class="t m0 x6 hc y3c ff5 fs6 fc0 sc0 ls30 ws0">08/08/2012<span class="_ _a"> </span>1.2</div><div class="t m0 xd hc y3d ff5 fs6 fc0 sc0 ls5 ws0">(<span class="_ _6"></span><span class="ff6 ls58">Cont’<span class="_ _0"></span>d)</span></div><div class="t m0 x7 hc y3c ff5 fs6 fc0 sc0 ls59 ws5b">R<span class="_ _3"></span>eorganized,<span class="_ _6"></span> clarif<span class="_ _6"></span>ied, an<span class="_ _6"></span>d expanded <span class="fc1 ls3c ws0">Chapte<span class="_ _3"></span>r<span class="_"> </span>19<span class="fc0 ls5a ws5c"> to include p<span class="_ _6"></span>r<span class="_ _3"></span>ogrammin<span class="_ _6"></span>g models </span></span></div><div class="t m0 x7 hc y3d ff5 fs6 fc0 sc0 ls5b ws4c">(added sections <span class="_ _3"></span><span class="fc1 ls35 ws0">19.1.3<span class="_ _f"> </span>Notices<span class="fc0">, </span><span class="ws5d">19.3<span class="_ _e"> </span>Programming Guide<span class="fc0 ls48 ws42">, and </span></span><span class="ls2d">19.5.1<span class="_ _f"> </span>MIO </span></span></div><div class="t m0 x7 hc y3e ff5 fs6 fc1 sc0 ls30 ws0">Programming<span class="fc0 ls4f ws53">). Updated </span><span class="ls54">T<span class="_ _d"></span>able<span class="_"> </span>22-2<span class="fc0 ls36 ws3a"> and </span><span class="ls3d">Ta<span class="_ _11"> </span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>2<span class="_ _7"></span>2<span class="_ _11"> </span>-<span class="_ _7"></span>3<span class="_ _7"></span><span class="fc0 ls41 ws4b"> in </span><span class="ls3c">Chapter<span class="_"> </span>2<span class="_ _3"></span>2<span class="fc0 ls39 ws5e">. Added section </span><span class="ls5c">CPU </span></span></span></span></div><div class="t m0 x7 hc y3f ff5 fs6 fc1 sc0 ls36 ws3a">Clock Divisor R<span class="_ _3"></span>estriction<span class="fc0 ls3b ws4a"> in </span><span class="ls47 ws0">Chap<span class="_ _6"></span>t<span class="_ _3"></span>er<span class="_"> </span>25<span class="fc0 ls38 ws37">. Updated </span><span class="ls3d">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _7"></span>6<span class="_ _7"></span>-<span class="_ _7"></span>4<span class="_ _7"></span><span class="fc0 ls41 ws4b"> in </span><span class="ls3c">Chapter<span class="_"> </span>26<span class="fc0 ls51 ws5f">. Clarif<span class="_ _6"></span>ied </span></span></span></span></div><div class="t m0 x7 hc y40 ff5 fs6 fc0 sc0 ls5d ws0">section <span class="fc1 ls2d ws60">27.3<span class="_ _e"> </span>I/O Signals<span class="_ _6"></span></span><span class="ls2c ws43"> in </span><span class="fc1 ls45">Chapter<span class="_"> </span>27</span><span class="ls5b ws4c">. Added section </span><span class="fc1 ls5e">28.1.2<span class="_ _f"> </span>Notices</span><span class="ls2c ws43"> in </span><span class="fc1 ls47">Chap<span class="_ _6"></span>ter<span class="_"> </span>28</span><span class="ls3e">. </span></div><div class="t m0 x7 hc y41 ff5 fs6 fc0 sc0 ls42 ws0">Clarif<span class="_ _6"></span>ied <span class="fc1 ls38 ws44">Mapping Summar<span class="_ _6"></span>y</span><span class="ls35 ws61"> and updated </span><span class="fc1 ls54">T<span class="_ _d"></span>able<span class="_"> </span>29-1<span class="fc0 ls3e">, </span><span class="ls43">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _6"></span>9<span class="_ _11"> </span>-<span class="_ _7"></span>3<span class="_ _7"></span><span class="fc0 ls3b ws4a">, and </span></span>T<span class="_ _0"></span>able<span class="_"> </span>29-5<span class="fc0 ls2c ws43"> in </span></span></div><div class="t m0 x7 hc y42 ff5 fs6 fc1 sc0 ls45 ws0">Chapter<span class="_"> </span>29<span class="fc0 ls5f ws62">. Added sect<span class="_ _6"></span>ion </span><span class="ls4e">30.1.3<span class="_ _f"> </span>Notices</span><span class="fc0 ws63"> in </span>Chap<span class="_ _6"></span>ter<span class="_"> </span>30<span class="fc0 ls42 ws64">. Upda<span class="_ _3"></span>ted dat<span class="_ _3"></span>a sheet r<span class="_ _3"></span>eferences </span></div><div class="t m0 x7 hc y43 ff5 fs6 fc0 sc0 ls5b ws4c">in section <span class="fc1 ls60 ws2a">A.3.1<span class="_ _f"> </span>Zynq-7000 AP<span class="_"> </span>SoC Documents</span><span class="ls61 ws65"> of <span class="fc1 ls62 ws0">Ap<span class="_ _6"></span>pendix<span class="_"> </span>A</span><span class="ls63 ws5c">. Updat<span class="_ _3"></span>ed reg<span class="_ _3"></span>ister </span></span></div><div class="t m0 x7 hc y44 ff5 fs6 fc0 sc0 ls64 ws66">datab<span class="_ _3"></span>ase in sections <span class="fc1 ls65 ws67">B.3<span class="_ _f"> </span>Module Summary</span><span class="ls54 ws58"> through <span class="fc1 ls39 ws68">B.34<span class="_ _e"> </span>USB Controller (usb)</span><span class="ls45 ws69"> in </span></span></div><div class="t m0 x7 hc y45 ff5 fs6 fc1 sc0 ls66 ws0">Appendix<span class="_"> </span>B<span class="fc0 ls5">.</span></div><div class="t m0 x6 hc y46 ff5 fs6 fc0 sc0 ls62 ws6a">10/30/2012<span class="_ _a"> </span>1.3<span class="_ _b"> </span>Changed product name <span class="ls40 ws6b">from Extensible Processing Plat<span class="_ _2"></span><span class="ls62 ws6a">f<span class="_ _6"></span>orm (EPP) t<span class="_ _3"></span>o All Programmable </span></span></div><div class="t m0 x7 hc y47 ff5 fs6 fc0 sc0 ls35 ws6c">SoC (AP<span class="_"> </span>SoC) throughout document. Added <span class="_ _3"></span><span class="fc1 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>1<span class="_ _7"></span>-<span class="_ _7"></span>1<span class="_ _7"></span><span class="fc0 ls67 ws6d">. Added </span><span class="ls39">2.1.1<span class="_ _e"> </span>Notices<span class="fc0 ls3e">, </span><span class="ls68">2.4<span class="_ _f"> </span>PS–PL </span></span></span></div><div class="t m0 x7 hc y48 ff5 fs6 fc1 sc0 ls59 ws6e">V<span class="_ _2"></span>oltage Level <span class="_ _6"></span>Shifter En<span class="_ _6"></span>ables<span class="fc0 ls3e ws0">, <span class="fc1 ws6f">A summary of the dedicated PS signal<span class="_ _3"></span> pins is shown i<span class="_ _3"></span>n </span></span></div><div class="t m0 x7 hc y49 ff5 fs6 fc1 sc0 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _7"></span>2<span class="_ _7"></span>.<span class="_ _11"></span><span class="fc0 ls3e">, </span><span class="ls69 ws70">VREF Source Considerations<span class="fc0 ls5b ws71">, updated </span></span>Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _11"> </span>2<span class="_ _7"></span><span class="fc0 ls38 ws37">, and added warning <span class="_ _3"></span>to </span></div><div class="t m0 x7 hc y4a ff5 fs6 fc1 sc0 ls60 ws2a">2.5.7<span class="_ _e"> </span>MIO Pin Electrical Parameters<span class="fc0 ls66 ws6f">. Added <span class="fc1">Initialization o<span class="_ _3"></span>f L1 Caches<span class="fc0 ws0">, <span class="fc1 ls2d">3.2.4<span class="_ _f"> </span>Memor<span class="_ _6"></span>y </span></span></span></span></div><div class="t m0 x7 hc y4b ff5 fs6 fc1 sc0 ls2c ws0">Ordering<span class="fc0 ls66 ws6f">, expanded <span class="_ _3"></span><span class="fc1 ls30 ws72">3.2.5<span class="_ _e"> </span>Memor<span class="_ _6"></span>y Management Unit (MMU)<span class="fc0 ls5b ws4c">, added </span><span class="ls4e ws73">Cache Lockdown </span></span></span></div><div class="t m0 x7 hc y4c ff5 fs6 fc1 sc0 ls3e ws74">by W<span class="_ _2"></span>a<span class="_ _6"></span>y Sequence<span class="fc0 ls36 ws75"> and </span><span class="ls47 ws76">3.9<span class="_ _f"> </span>CPU Init<span class="_ _6"></span>ialization Sequen<span class="_ _6"></span>ce<span class="fc0 ls36 ws77">. Added </span><span class="ls5d ws78">Z<span class="_ _2"></span>ynq-700<span class="_ _6"></span>0 AP SoC 7z010 </span></span></div><div class="t m0 x7 hc y4d ff5 fs6 fc1 sc0 ls6a ws79">CL<span class="_ _3"></span>G225 Device Notice<span class="fc0 ls48 ws46"> and expanded </span><span class="ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>4<span class="_ _7"></span>-<span class="_ _11"> </span>7<span class="_ _7"></span><span class="fc0 ls2f ws51">. Updated and exp<span class="_ _3"></span>anded t<span class="_ _3"></span>ables in </span></span></div><div class="t m0 x7 hc y4e ff5 fs6 fc1 sc0 ls4e ws7a">6.3.4</div><div class="t m0 xe hc y4f ff5 fs6 fc1 sc0 ls4e ws7a">Q</div><div class="t m0 xf hc y50 ff5 fs6 fc1 sc0 ls4e ws7a">uad-SPI Boot<span class="fc0 ls2c ws7b"> through </span><span class="ls46 ws7c">6.3.13<span class="_ _e"> </span>Po<span class="_ _3"></span>st BootROM St<span class="_ _2"></span>ate<span class="fc0 ls6b ws7d">, rework<span class="_ _3"></span>ed <span class="fc1 ls6a ws7e">6.3.6<span class="_ _e"> </span>Debug S<span class="_ _3"></span>tatus<span class="fc0 ls3e ws0">, </span></span></span></span></div><div class="t m0 x7 hc y51 ff5 fs6 fc0 sc0 ls3b ws35">and adde<span class="_ _6"></span>d <span class="fc1 ls30 ws72">6.3.13<span class="_ _f"> </span>Post BootROM S<span class="_ _3"></span>tate<span class="fc0 ls36 ws3a"> and </span><span class="ls2c ws28">AXI and DMA Done S<span class="_ _2"></span>tatus Interrupts<span class="fc0 ls3e ws0">. </span></span></span></div><div class="t m0 x7 hc y52 ff5 fs6 fc0 sc0 ls50 ws0">Re<span class="_ _6"></span>wo<span class="_ _6"></span>r<span class="_ _6"></span>ked<span class="_ _6"></span> <span class="_ _6"></span><span class="fc1 ls43">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>7<span class="_ _6"></span>-<span class="_ _11"> </span>4<span class="_ _7"></span></span><span class="ls67 ws7f">. Added </span><span class="fc1 ls39">8.1.2<span class="_ _f"> </span>Notices</span><span class="ls3e">, <span class="fc1 ls6c ws52">In<span class="_ _6"></span>terrupt <span class="_ _6"></span>to PS Inter<span class="_ _6"></span>rupt Cont<span class="_ _6"></span>roller</span><span class="ls48 ws46">, and </span></span></div><div class="t m0 x7 hc y53 ff5 fs6 fc1 sc0 ls50 ws0">Re<span class="_ _6"></span>se<span class="_ _6"></span>t<span class="_ _6"></span><span class="fc0 ls63 ws5c">. R<span class="_ _2"></span>eorganized a<span class="_ _3"></span>nd expand<span class="_ _3"></span>ed <span class="fc1 ls55 ws80">Chapter<span class="_"> </span>9, DMA Controller</span><span class="ls36 ws4e">. Added <span class="fc1 ls6a ws0">10.1.3<span class="_ _f"> </span>Notices<span class="fc0 ls3e">, </span></span></span></span></div><div class="t m0 x7 hc y54 ff5 fs6 fc0 sc0 ls63 ws0">expanded <span class="_ _3"></span><span class="fc1 ls6a ws81">10.1.6<span class="_ _e"> </span>I/O Signals<span class="fc0 ls5b ws4c">, added </span><span class="ls62 ws82">10.6.11<span class="_ _f"> </span>DRAM <span class="_ _6"></span>Write Lat<span class="_ _3"></span>ency R<span class="_ _3"></span>estriction<span class="fc0 ls3e ws0">, </span></span></span></div><div class="t m0 x7 hc y55 ff5 fs6 fc1 sc0 ls3e ws83">10.8.1<span class="_ _f"> </span>ECC Initialization<span class="fc0 ws0">, <span class="_ _d"></span><span class="fc1 ls6d ws84">10<span class="_ _6"></span>.8.4<span class="_ _f"> </span>ECC Programming Mo<span class="_ _6"></span>del<span class="fc0 ls48 ws85">, and </span><span class="ls6a ws86">10.9.1<span class="_ _f"> </span>Operating Modes<span class="fc0 ls3e ws0">. </span></span></span></span></div><div class="t m0 x7 hc y56 ff5 fs6 fc0 sc0 ls2f ws0">Added <span class="_ _0"></span><span class="fc1 ls6e ws87">12.2.4<span class="_ _14"> </span>I/O Mode Considerations<span class="fc0 ls5b ws88"> and updated </span><span class="ls48 ws89">12.3.5<span class="_ _f"> </span>Rx/T<span class="_ _0"></span>x FIFO Response to I/O </span></span></div><div class="t m0 x7 hc y57 ff5 fs6 fc1 sc0 ls35 ws6c">Command Sequences<span class="fc0 ls6a ws8a">. R<span class="_ _2"></span>eworked <span class="fc1 ls46 ws8b">16.3.3<span class="_ _e"> </span>I/O Conf<span class="_ _6"></span>iguratio<span class="_ _6"></span>n</span><span class="ls5b ws8c">, a<span class="_ _3"></span>dded <span class="fc1 ls54 ws8d">16.4<span class="_ _e"> </span>IEEE 1588 T<span class="_ _6"></span>ime </span></span></span></div><div class="t m0 x7 hc y58 ff5 fs6 fc1 sc0 ls6f ws0">Sta<span class="_ _6"></span>m<span class="_ _6"></span>pi<span class="_ _6"></span>n<span class="_ _6"></span>g<span class="fc0 ls42 ws8e"> and </span><span class="ls5f ws8f">16.6.7<span class="_ _e"> </span>MIO Pin Con<span class="_ _6"></span>siderations<span class="fc0 ls66 ws6f">. Added </span></span><span class="ls46">18.2.7<span class="_ _e"> </span>CAN0-to-CAN1 </span></div><div class="t m0 x7 hc y59 ff5 fs6 fc1 sc0 ls6a ws0">Connection<span class="fc0 ws90">. Expanded </span><span class="ls70">19.1<span class="_ _f"> </span>In<span class="_ _6"></span>tr<span class="_ _3"></span>oduction<span class="fc0 ls3e">, </span><span class="ls4e">19.1.3<span class="_ _e"> </span>N<span class="_ _6"></span>otices<span class="fc0 ls48 ws42">, and </span><span class="ls54">T<span class="_ _d"></span>able<span class="_"> </span>19-1<span class="fc0 ls66 ws6f">. Added </span></span></span></span></div><div class="t m0 x7 hc y5a ff5 fs6 fc1 sc0 ls66 ws42">R<span class="_ _3"></span>eceiver T<span class="_ _6"></span>imeout Mechanism<span class="_ _3"></span><span class="fc0 ls5b ws4c">, updated <span class="fc1 ls5f ws0">Figure<span class="_"> </span>19-7</span><span class="ls67 ws7f">. Added </span><span class="fc1 ws0">19.2.9<span class="_ _e"> </span>UAR<span class="_ _2"></span>T0-to-U<span class="_ _2"></span>A<span class="_ _6"></span>R<span class="_ _2"></span>T1 </span></span></div><div class="t m0 x7 hc y5b ff5 fs6 fc1 sc0 ls6a ws0">Connection<span class="fc0 ls3b ws4a"> and </span><span class="ls2d ws29">19.2.10<span class="_ _e"> </span>St<span class="_ _3"></span>atus and Interrupts<span class="fc0 ls3f ws91">, expanded </span><span class="ls46 ws59">19.2.11<span class="_ _e"> </span>Modem Control<span class="fc0 ls3e ws0">, </span></span></span></div><div class="t m0 x7 hc y5c ff5 fs6 fc0 sc0 ls71 ws0">reworked <span class="_ _6"></span><span class="fc1 ls35 ws5d">19.3<span class="_ _f"> </span>Programming Guide</span><span class="ls42 ws8e"> and <span class="_ _3"></span><span class="fc1 ls35 ws0">19.4.2<span class="_ _e"> </span>R<span class="_ _3"></span>esets<span class="fc0 ls36 ws4e">. Add<span class="_ _3"></span>ed <span class="fc1 ls54 ws0">20.2.7<span class="_ _e"> </span>I2C0-to-I2C1 </span></span></span></span></div><div class="t m0 x7 hc y5d ff5 fs6 fc1 sc0 ls6a ws0">Connection<span class="fc0 ls36 ws4e">. Added </span><span class="ls45 ws69">21.1.2<span class="_ _f"> </span>PL <span class="_ _6"></span>R<span class="_ _2"></span>esources by Device T<span class="_ _2"></span>ype<span class="fc0 ls3e ws0">, </span><span class="ls2f ws57">V<span class="_ _2"></span>oltage Level Shifters<span class="fc0 ws8e"> and </span></span></span></div><div class="t m0 x7 hc y5e ff5 fs6 fc0 sc0 ls5e ws92">reor<span class="_ _2"></span>ganized content of <span class="fc1 ls38 ws37">Chapter<span class="_"> </span>21, Progra<span class="_ _3"></span>mmable Logic Description<span class="fc0">. Add<span class="_ _3"></span>ed </span></span></div><div class="t m0 x7 hc y5f ff5 fs6 fc1 sc0 ls4e ws73">25.7.1<span class="_ _e"> </span>Clock Throttle<span class="fc0 ls72 ws93">. Expanded </span><span class="ls62 ws94">26.4.1<span class="_ _f"> </span>PL G<span class="_ _0"></span>eneral Purpose User Reset<span class="_ _2"></span>s<span class="fc0 ls63 ws95">. Updated </span></span></div><div class="t m0 x7 hc y60 ff5 fs6 fc0 sc0 ls3e ws52">register dat<span class="_ _2"></span>abase in sections <span class="fc1 ls72 ws96">B.3<span class="_ _f"> </span>Module Summary</span><span class="ls2c ws28"> through <span class="fc1 ls73 ws97">B.34<span class="_ _f"> </span>USB Contr<span class="_ _3"></span>oller (usb<span class="_ _3"></span>)<span class="fc0 ls5 ws0"> </span></span></span></div><div class="t m0 x7 hc y61 ff5 fs6 fc0 sc0 ls45 ws0">in <span class="fc1 ls62">Appendix<span class="_"> </span>B</span><span class="ls5">.</span></div><div class="t m0 x6 hc y62 ff5 fs6 fc0 sc0 ls2d ws98">11/16/2012<span class="_ _a"> </span>1.4<span class="_ _b"> </span>Changed second bullet under <span class="fc1 ls74 ws99">NAND Flash Int<span class="_ _3"></span>erface<span class="fc0 ls30 ws9a"> from “</span></span></div><div class="t m0 x10 ha y63 ff5 fs2 fc0 sc0 ls33 ws9b">Up to a 4 GB device” to <span class="fs6 ls5 ws0">“<span class="_ _6"></span><span class="fs2 ls75">Up </span></span></div><div class="t m0 x7 ha y64 ff5 fs2 fc0 sc0 ls76 ws9c">to a 1<span class="_ _6"></span> GB dev<span class="_ _6"></span>ice” in<span class="_ _6"></span> </div><div class="t m0 x11 hc y65 ff5 fs6 fc1 sc0 ls3f ws91">Chapter<span class="_"> </span>11, St<span class="_ _2"></span>atic Memor<span class="_ _6"></span>y Controller<span class="fc0 ls5 ws0">.</span></div><div class="t m0 x5 h5 y66 ff3 fs2 fc0 sc0 ls2a ws0">Date<span class="_ _8"> </span>V<span class="_ _2"></span>ersion<span class="_ _9"> </span>Revision</div><div class="c xb y3a w2 he"><div class="t m1 xc hf y3b ff7 fs7 fc2 sc0 ls5 ws0"><span class="fc3 sc0">Send F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">edback</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622bada83d2fbb0007d19d48/bg4.jpg"><div class="t m0 x2 h5 y5 ff3 fs2 fc0 sc0 ls3 ws3">Zynq-7<span class="_ _2"></span>000 AP SoC T<span class="_ _2"></span>echnical R<span class="_ _2"></span>eference Man<span class="_ _3"></span>ual<span class="_ _4"> </span><span class="ff4 fc1 ls4 ws0">www<span class="_ _0"></span>.xilinx<span class="_ _3"></span>.co<span class="_ _3"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls5">4</span></span></div><div class="t m0 x2 h6 y6 ff4 fs2 fc0 sc0 ls6 ws4">U<span class="_ _3"></span>G585 (v1.10) Febru<span class="_ _3"></span>ary 23, 2015</div><div class="t m0 x6 hc y1 ff5 fs6 fc0 sc0 ls6a ws79">03/07/2013<span class="_ _a"> </span>1.5<span class="_ _b"> </span>Added 7z100 device and <span class="ws81">made minor clarif<span class="_ _6"></span>ications to <span class="fc1 ls77 ws9d">Chapter<span class="_"> </span>1, I<span class="_ _3"></span>ntrod<span class="_ _3"></span>uction<span class="_ _3"></span><span class="fc0 ls35 ws5d">. Made </span></span></span></div><div class="t m0 x7 hc y67 ff5 fs6 fc0 sc0 ls54 ws9e">minor clarif<span class="_ _6"></span>ications to <span class="fc1 ls48 ws42">Chap<span class="_ _6"></span>ter<span class="_ _10"> </span>2, Signals, Int<span class="_ _3"></span>erfaces, and Pins<span class="fc0 ls3e ws0">, </span><span class="ls5b ws71">Chapter<span class="_"> </span>3, Application </span></span></div><div class="t m0 x7 hc y68 ff5 fs6 fc1 sc0 ls62 ws82">Processing Unit<span class="fc0 ls3e ws0">, </span><span class="ls5e ws9f">Chapter<span class="_"> </span>4, S<span class="_ _2"></span>ystem Addresses<span class="fc0 ls48 ws42">, and </span><span class="ls40 ws38">Chapter<span class="_"> </span>5, Interconnect<span class="fc0 ls2f ws51">. Clarif<span class="_ _6"></span>ied </span></span></span></div><div class="t m0 x7 hc y69 ff5 fs6 fc0 sc0 ls5d ws0">section <span class="fc1 ls78">6.1<span class="_ _e"> </span>Introduction</span><span class="ls3e wsa0"> and other sections, and added <span class="fc1 ls56 wsa1">PS Independent JT<span class="_ _0"></span>AG </span></span></div><div class="t m0 x7 hc y6a ff5 fs6 fc1 sc0 ls2e wsa2">Non-Secure Boot<span class="_ _6"></span><span class="fc0 ls5b ws4c"> section in </span><span class="ls62 ws82">Chapter<span class="_"> </span>6, Boot and Conf<span class="_ _6"></span>iguration<span class="fc0 ls64 wsa3">. Made minor </span></span></div><div class="t m0 x7 hc y6b ff5 fs6 fc0 sc0 ls5e ws92">clarif<span class="_ _6"></span>ications to <span class="fc1 ls79 wsa4">Chapte<span class="_ _6"></span>r<span class="_"> </span>7, Interru<span class="_ _6"></span>pts</span><span class="ls3e ws0">, <span class="fc1 ls7a wsa5">Chapter<span class="_"> </span>8, T<span class="_ _6"></span>imer<span class="_ _6"></span>s</span>, <span class="fc1 ls54 ws9e">Chapter<span class="_"> </span>9, DMA Controller</span>, </span></div><div class="t m0 x7 hc y6c ff5 fs6 fc1 sc0 ls60 ws2a">Chapter<span class="_"> </span>10, DDR Memor<span class="_ _6"></span>y Controller<span class="fc0 ls3e ws0">, </span><span class="ls45 ws69">Chapter<span class="_"> </span>11, Static Memory Controller<span class="fc0 ls3b ws4a">, and </span></span></div><div class="t m0 x7 hc y6d ff5 fs6 fc1 sc0 ls69 ws70">Chapter<span class="_"> </span>12, Quad-SPI Flash Controller<span class="fc0 ls72 ws93">. Expa<span class="_ _3"></span>nded <span class="fc1 ls2f ws57">12.2<span class="_ _f"> </span>Functional Description</span><span class="ls2c ws43"> in </span></span></div><div class="t m0 x7 hc y6e ff5 fs6 fc1 sc0 ls2c ws70">Chapter<span class="_"> </span>12, Quad-SPI Flash Controller<span class="fc0 ls41 ws4b">. Made minor<span class="_ _3"></span> clarif<span class="_ _6"></span>ications to <span class="fc1 ls7b ws0">Chapter<span class="_"> </span>13, </span></span></div><div class="t m0 x7 hc y6f ff5 fs6 fc1 sc0 ls3e wsa6">SD/SDIO Controller<span class="fc0 ls5b wsa7">. Ma<span class="_ _3"></span>de major clarif<span class="_ _6"></span>ications/updat<span class="_ _3"></span>es to <span class="fc1 ls7c wsa8">Chapter<span class="_"> </span>1<span class="_ _6"></span>4, G<span class="_ _d"></span>eneral Purp<span class="_ _6"></span>ose </span></span></div><div class="t m0 x7 hc y70 ff5 fs6 fc1 sc0 ls7d wsa9">I/O (GPIO)<span class="fc0 ls36 wsaa">. Rework<span class="_ _2"></span>ed and expanded <span class="fc1 ls7e wsab">Chapter<span class="_ _13"> </span>15, USB Host,<span class="_ _6"></span> <span class="_ _3"></span>Device, an<span class="_ _6"></span>d O<span class="_ _2"></span>T<span class="_ _2"></span>G Cont<span class="_ _6"></span>r<span class="_ _3"></span>oller<span class="_ _6"></span><span class="fc0 ls3e ws0">. </span></span></span></div><div class="t m0 x7 hc y71 ff5 fs6 fc0 sc0 ls3e wsac">Made minor clarif<span class="_ _6"></span>ications to <span class="fc1 ls2d ws60">Chapter<span class="_"> </span>16, Gigabit Ethernet Controller</span><span class="ls5e ws92">. R<span class="_ _2"></span>eworked and </span></div><div class="t m0 x7 hc y72 ff5 fs6 fc0 sc0 ls63 ws0">expanded <span class="_ _3"></span><span class="fc1 ls30 ws72">Chapter<span class="_"> </span>17, SPI <span class="_ _6"></span>Contr<span class="_ _3"></span>oller<span class="fc0 ls49 wsad">. Made minor cla<span class="_ _6"></span>rif<span class="_ _6"></span>ications to </span><span class="ls40 ws38">Chap<span class="_ _6"></span>t<span class="_ _3"></span>er<span class="_"> </span>18, CAN </span></span></div><div class="t m0 x7 hc y73 ff5 fs6 fc1 sc0 ls60 ws0">Controller<span class="fc0 ls63 ws95">, and </span><span class="ls69 ws70">Chapter<span class="_"> </span>19, UAR<span class="_ _2"></span>T Con<span class="_ _6"></span>tr<span class="_ _3"></span>oller<span class="fc0 ls2f ws57">. Made major clarif<span class="_ _6"></span>ications/updat<span class="_ _3"></span>es to </span></span></div><div class="t m0 x7 hc y74 ff5 fs6 fc1 sc0 ls30 wsae">Chapter<span class="_ _13"> </span>20, I2C Controller<span class="fc0 ls2f wsaf"> (a<span class="_ _3"></span>dded new sections, <span class="fc1 ls39 wsb0">20.3<span class="_ _f"> </span>Programmer<span class="_ _6"></span>’<span class="_ _2"></span>s Guide<span class="fc0 ls3e ws0">, <span class="_ _0"></span><span class="fc1 ls74">20.4<span class="_ _e"> </span>System </span></span></span></span></div><div class="t m0 x7 hc y75 ff5 fs6 fc1 sc0 ls6a ws0">Functions<span class="fc0 ls48 ws42">, and </span><span class="ls7f wsb1">20.5<span class="_ _f"> </span>I/O Interface<span class="fc0 ls5b ws71">). Made minor cla<span class="_ _3"></span>rif<span class="_ _6"></span>ications to <span class="fc1 ls7b ws0">Chapter<span class="_"> </span>21, </span></span></span></div><div class="t m0 x7 hc y76 ff5 fs6 fc1 sc0 ls6b wsb2">Programm<span class="_ _3"></span>able Logic Description<span class="fc0 ls41 wsb3"> and added<span class="_ _3"></span> new sections <span class="fc1 ls3e wsb4">21.1.2<span class="_ _f"> </span>PL Resources by De<span class="_ _3"></span>vice </span></span></div><div class="t m0 x7 hc y77 ff5 fs6 fc1 sc0 ls80 ws0">Ty<span class="_ _6"></span>p<span class="_ _6"></span>e<span class="_ _6"></span><span class="fc0 ls3b wsb5"> and </span><span class="ls4e">21.1.3<span class="_ _e"> </span>Notices<span class="fc0 ls42 wsb6">. <span class="_ _6"></span>Ma<span class="_ _3"></span>de minor clarif<span class="_ _6"></span>ications to <span class="_ _3"></span><span class="fc1 ls36 wsb7">Chapter<span class="_ _13"> </span>22, Pr<span class="_ _3"></span>ogrammable Logic </span></span></span></div><div class="t m0 x7 hc y78 ff5 fs6 fc1 sc0 ls3e ws52">Design Guide<span class="fc0 ls42 ws8e"> and </span><span class="ls36 ws3a">Chapter<span class="_"> </span>23, Pr<span class="_ _3"></span>ogrammable Logic T<span class="_ _d"></span>est and Debug<span class="fc0 ls62 ws94">. Rework<span class="_ _3"></span>ed and </span></span></div><div class="t m0 x7 hc y79 ff5 fs6 fc0 sc0 ls63 ws0">expanded <span class="_ _3"></span><span class="fc1 ls78 wsb8">Chapter<span class="_"> </span>24, Power Management<span class="fc0 ls49 wsad">. Made minor clarif<span class="_ _7"></span>ications to </span><span class="ws0">Chapter<span class="_"> </span>25, </span></span></div><div class="t m0 x7 hc y7a ff5 fs6 fc1 sc0 ls55 ws0">Clocks<span class="fc0 ls3e">, </span><span class="ls81 wsb9">Chapter<span class="_"> </span>2<span class="_ _3"></span>6, R<span class="_ _2"></span>eset System<span class="_ _3"></span><span class="fc0 ls3e ws0">, <span class="fc1 ls6b wsba">Chapter<span class="_"> </span>27, JT<span class="_ _0"></span>AG and DAP Subsystem<span class="_ _3"></span><span class="fc0 ls3e ws0">, <span class="fc1 ls78">Chapter<span class="_"> </span>28, </span></span></span></span></span></div><div class="t m0 x7 hc y7b ff5 fs6 fc1 sc0 ls82 wsbb">Sy<span class="_ _3"></span>stem T<span class="_ _d"></span>est and Debug<span class="fc0 ls48 ws46">, and </span><span class="ls83 wsbc">Chapter<span class="_ _10"> </span>29, On-<span class="_ _3"></span>Chip Mem<span class="_ _3"></span>or<span class="_ _6"></span>y (<span class="_ _3"></span>OCM)<span class="fc0 ls84 ws9f">. R<span class="_ _3"></span>eworked and </span></span></div><div class="t m0 x7 hc y7c ff5 fs6 fc0 sc0 ls63 ws0">expanded <span class="_ _3"></span><span class="fc1 ls85 ws60">Chap<span class="_ _6"></span>ter<span class="_"> </span>30,<span class="_ _6"></span> XADC Inte<span class="_ _6"></span>rface<span class="_ _6"></span><span class="fc0 ls66 wsac">. Made minor clar<span class="_ _3"></span>if<span class="_ _6"></span>ications to <span class="fc1 ls86 wsbd">Chapter<span class="_"> </span>3<span class="_ _3"></span>1, PCI </span></span></span></div><div class="t m0 x7 hc y7d ff5 fs6 fc1 sc0 ls35 ws0">Express<span class="fc0 ls66 wsbe">. R<span class="_ _2"></span>eworked and expanded <span class="fc1 ls45 wsbf">Chapter<span class="_ _10"> </span>32, Device Secure Boot</span><span class="ls48 wsc0">. Updat</span></span></div><div class="t m0 x12 hc y7e ff5 fs6 fc0 sc0 ls48 wsc0">ed</div><div class="t m0 x13 hc y7f ff5 fs6 fc0 sc0 ls48 wsc0"> <span class="fc1 ws0">Appendix<span class="_"> </span>A<span class="_ _6"></span>, </span></div><div class="t m0 x7 hc y80 ff5 fs6 fc1 sc0 ls87 wsc1">Additional<span class="_ _3"></span> R<span class="_ _2"></span>esources<span class="fc0 ls41 ws39">. Updated r<span class="_ _3"></span>egister datab<span class="_ _2"></span>ase in sections <span class="fc1 ls30 ws2c">B.3<span class="_ _e"> </span>Module Summar<span class="_ _6"></span>y</span><span class="ls5 ws0"> </span></span></div><div class="t m0 x7 hc y81 ff5 fs6 fc0 sc0 ls88 ws0">thr<span class="_ _3"></span>ough <span class="fc1 ls67 wsc2">B.34<span class="_ _f"> </span>USB Contr<span class="_ _3"></span>oller (usb)<span class="_ _3"></span><span class="fc0 ls2c ws43"> in <span class="fc1 ls66 ws0">Appendix<span class="_"> </span>B<span class="fc0 ls5">.</span></span></span></span></div><div class="t m0 x6 hc y82 ff5 fs6 fc0 sc0 ls6e wsc3">06/28/2013<span class="_ _a"> </span>1.6<span class="_ _b"> </span>Added icons where applicab<span class="ls39 wsc4">le. Enhanced f<span class="_ _6"></span>irs<span class="_ _6"></span>t sentence under <span class="_ _3"></span><span class="fc1 ls54 wsc5">Quad-SPI Controller<span class="_ _6"></span><span class="fc0 ls66 wsc6"> in c. </span></span></span></div><div class="t m0 x7 hc y83 ff5 fs6 fc0 sc0 ls36 ws77">Clarif<span class="_ _6"></span>ied f<span class="_ _6"></span>irst paragraph, added step<span class="_ _3"></span> 2, and clarif<span class="_ _6"></span>ied step 5 in section <span class="fc1 ls35 wsc7">2.4<span class="_ _f"> </span>PS–PL V<span class="_ _2"></span>oltage </span></div><div class="t m0 x7 hc y84 ff5 fs6 fc1 sc0 ls36 ws3a">Level Shifter Enables<span class="fc0 ls3e wsa0">. Changed “<span class="_ _2"></span>drive strength” to “<span class="_ _2"></span>slew rate” in section <span class="fc1 ls65 ws67">2.5.7<span class="_ _e"> </span>MIO Pin<span class="_ _3"></span> </span></span></div><div class="t m0 x7 hc y85 ff5 fs6 fc1 sc0 ls55 wsc8">Electrical P<span class="_ _3"></span>arameters<span class="fc0 ls66 ws6f">. Added second sent<span class="_ _3"></span>ence and updat<span class="_ _3"></span>ed <span class="fc1 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _7"></span>-<span class="_ _7"></span>1<span class="_ _7"></span>1<span class="_ _11"> </span></span><span class="ls36 ws4e"> in section </span></span></div><div class="t m0 x7 hc y86 ff5 fs6 fc1 sc0 ls39 ws5e">2.7.4<span class="_ _e"> </span>Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals<span class="fc0 ls89 ws6f">. Corre<span class="_ _6"></span>cted Note 4 <span class="_ _6"></span>in </span><span class="ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>4<span class="_ _7"></span>-<span class="_ _7"></span>1<span class="_ _11"> </span><span class="fc0 ls5"> </span></span></div><div class="t m0 x7 hc y87 ff5 fs6 fc0 sc0 ls36 ws0">and <span class="fc1 ls3d">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>4<span class="_ _11"> </span>-<span class="_ _7"></span>2<span class="_ _7"></span></span><span class="ls49 wsad">. Made mino<span class="_ _6"></span>r clarif<span class="_ _6"></span>icati<span class="_ _6"></span>ons and added new <span class="fc1 ls2c ws43">RSA Authentication T<span class="_ _6"></span>ime<span class="_ _6"></span></span></span><span class="ls5"> </span></div><div class="t m0 x7 hc y88 ff5 fs6 fc0 sc0 ls5d wsc9">section to <span class="fc1 ls41 ws39">Chapter<span class="_"> </span>6, Boot and Conf<span class="_ _6"></span>iguration</span><span class="ls2c ws28">. Made minor clarif<span class="_ _6"></span>ications to sections </span></div><div class="t m0 x7 hc y89 ff5 fs6 fc1 sc0 ls6a ws79">7.2.2<span class="_ _e"> </span>CPU Private <span class="_ _3"></span>P<span class="_ _3"></span>eripheral Interrupts (PPI)<span class="fc0 ls36 ws3a"> and </span>7.2.3<span class="_ _e"> </span>Shared P<span class="_ _2"></span>eripheral Interrupts </div><div class="t m0 x7 hc y8a ff5 fs6 fc1 sc0 ls60 ws0">(SPI)<span class="fc0 ls44 wsca">, and upd<span class="_ _6"></span>ated </span><span class="ls3d">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>7<span class="_ _7"></span>-<span class="_ _11"> </span>4<span class="_ _7"></span><span class="fc0 ls3b ws4a"> and </span>Ta<span class="_ _11"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>7<span class="_ _7"></span>-<span class="_ _7"></span>5<span class="_ _11"> </span><span class="fc0 ls36 ws3a">. Clarif<span class="_ _6"></span>ied f<span class="_ _6"></span>irst row in </span>Ta<span class="_ _11"> </span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>9<span class="_ _7"></span>-<span class="_ _11"> </span>1<span class="_ _7"></span>2<span class="_ _7"></span><span class="fc0 ls3a ws35">. Added tip </span></span></div><div class="t m0 x7 hc y8b ff5 fs6 fc0 sc0 ls2b wscb">to section <span class="fc1 ls39 wscc">10.4.3<span class="_ _f"> </span>Aging Counter</span><span class="ls3e wscd">, added sentence to <span class="fc1 ls8a wsce">Write Leveling</span><span class="ls55 wscf">, and step 2 in section </span></span></div><div class="t m0 x7 hc y8c ff5 fs6 fc1 sc0 ls60 wsd0">10.9.2<span class="_ _e"> </span>Changing Clock Frequencies<span class="fc0 ls39 ws68">, and moved section </span><span class="ls2c ws28">10.9.6<span class="_ _f"> </span>DDR Power R<span class="_ _2"></span>eduction<span class="_ _6"></span><span class="fc0 ls5 ws0"> </span></span></div><div class="t m0 x7 hc y8d ff5 fs6 fc0 sc0 ls30 ws0">from <span class="fc1 ls45 ws69">Chapter<span class="_"> </span>24, P<span class="_ _3"></span>ower Management<span class="fc0 ls2f ws57"> to this chapter<span class="_ _0"></span>. Added tip to section </span></span></div><div class="t m0 x7 hc y8e ff5 fs6 fc1 sc0 ls70 ws0">11.2.2<span class="_ _e"> </span>Clocks<span class="fc0 ls5b wsd1">. Added </span><span class="ls3d">Ta<span class="_ _11"> </span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>1<span class="_ _7"></span>2<span class="_ _7"></span>-<span class="_ _11"> </span>8<span class="_ _7"></span><span class="fc0 ls48 wsd2">. Added </span></span></div><div class="t m0 x14 ha y8f ff5 fs2 fc0 sc0 ls8b wsd3">MMC3.31 standard information to section </div><div class="t m0 x7 hc y90 ff5 fs6 fc1 sc0 ls55 ws0">13.1<span class="_ _e"> </span>Introduction<span class="_ _6"></span><span class="fc0 ls36 ws3a">. Added step 6 to section </span><span class="ls30 ws2c">14.3.1<span class="_ _f"> </span>Start<span class="_ _2"></span>-up Sequen<span class="_ _6"></span>ce<span class="fc0 ls41 ws4b">, a<span class="_ _2"></span>dded section </span></span></div><div class="t m0 x7 hc y91 ff5 fs6 fc1 sc0 ls2c ws43">14.3.5<span class="_ _e"> </span>GPIO as Wak<span class="_ _2"></span>e<span class="_ _6"></span>-up Event<span class="fc0 ls35 ws61">, a<span class="_ _3"></span>dded second paragraph to <span class="fc1 ls62 ws0">14.4.1<span class="_ _f"> </span>Clocks<span class="_ _6"></span></span><span class="ls5b ws4c">. Added </span></span></div><div class="t m0 x7 hc y92 ff5 fs6 fc0 sc0 ls5d ws0">section <span class="fc1 ls46 ws59">16.7<span class="_ _e"> </span>Known Issues</span><span class="ls6b wsba">. Added note to </span><span class="fc1 ls63">17.4.2<span class="_ _f"> </span>Clocks</span><span class="ls64 wsa3">. Changed value o<span class="_ _3"></span>f 107<span class="_"> </span>Mb to </span></div><div class="t m0 x7 hc y93 ff5 fs6 fc0 sc0 ls30 ws72">140<span class="_"> </span>Mb in second sent<span class="ws70">en<span class="_ _6"></span>ce under <span class="_ _3"></span>section <span class="fc1 ls7d ws0">21.4<span class="_ _e"> </span>Conf<span class="_ _6"></span>igu<span class="_ _6"></span>ration</span><span class="ls49 ws45">. Ad<span class="_ _6"></span>ded values for the </span></span></div><div class="t m0 x7 hc y94 ff5 fs6 fc0 sc0 ls46 ws54">7z100 device in <span class="fc1 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _11"> </span>e<span class="_ _12"> </span>2<span class="_ _7"></span>1<span class="_ _7"></span>-<span class="_ _7"></span>2<span class="_ _11"> </span></span><span class="ls2f ws57">. Clarif<span class="_ _6"></span>ied f<span class="_ _6"></span>irst paragraph in section <span class="fc1 ls64 wsa3">24.2.2<span class="_ _f"> </span>PL Power<span class="_ _0"></span>-down </span></span></div><div class="t m0 x7 hc y95 ff5 fs6 fc1 sc0 ls7c ws0">Control<span class="_ _6"></span><span class="fc0 ls6b wsd4"> a<span class="_ _3"></span>nd updated <span class="fc1 ls3d ws0">Ta<span class="_ _6"></span>b<span class="_ _11"> </span>l<span class="_ _7"></span>e<span class="_ _12"> </span>2<span class="_ _7"></span>4<span class="_ _11"></span>-<span class="_ _7"></span>2<span class="_ _7"></span></span><span class="ls78 ws90">. Added note to section <span class="fc1 ws27">25.6.1<span class="_ _f"> </span>USB Clocks</span><span class="ls4f ws53">, clarif<span class="_ _6"></span>ied </span></span></span></div><div class="t m0 x7 hc y96 ff5 fs6 fc0 sc0 ls2c ws43">second paragraph in section <span class="_ _6"></span><span class="fc1 ls62 ws0">25.10.4<span class="_ _f"> </span>PLLs</span><span class="ls45 wsd5">, and added sentence <span class="_ _3"></span>to steps 2 and 3 in </span></div><div class="t m0 x7 hc y97 ff5 fs6 fc1 sc0 ls38 ws44">Software-Contr<span class="_ _3"></span>olled PLL Update<span class="fc0 ls62 ws94"> section. Changed “RESET_REASON” to </span></div><div class="t m0 x7 hc y98 ff5 fs6 fc0 sc0 ls55 wsd6">“REBOO<span class="_ _2"></span>T_ST<span class="_ _2"></span>A<span class="_ _0"></span>TUS in <span class="_ _6"></span>section <span class="fc1 ls2c wsd7">26.2.3<span class="_ _f"> </span>System Software R<span class="_ _2"></span>e<span class="_ _6"></span>set<span class="fc0 ls5b wsd8">, a<span class="_ _3"></span>dded section <span class="fc1 ws0">26.5<span class="_ _f"> </span>Register </span></span></span></div><div class="t m0 x7 hc y99 ff5 fs6 fc1 sc0 ls45 ws0">Over<span class="_ _6"></span>view<span class="fc0 ls5b wsd9">, delet<span class="_ _3"></span>ed f<span class="_ _6"></span>irst two rows from <span class="fc1 ls3d ws0">Ta<span class="_ _7"></span>b<span class="_ _7"></span>l<span class="_ _7"></span>e<span class="_ _12"> </span>2<span class="_ _7"></span>6<span class="_ _7"></span>-<span class="_ _11"> </span>2<span class="_ _7"></span></span><span class="ls59 wsda"> an<span class="_ _6"></span>d modif<span class="_ _6"></span>ied las<span class="_ _6"></span>t paragraph in se<span class="_ _6"></span>ction </span></span></div><div class="t m0 x7 hc y9a ff5 fs6 fc1 sc0 ls5b wsd9">26.5.1<span class="_ _f"> </span>Persistent R<span class="_ _2"></span>egis<span class="_ _6"></span>t<span class="_ _3"></span>ers<span class="fc0 ws88">. Clarif<span class="_ _6"></span>ied section </span><span class="ls2d ws0">29.1<span class="_ _f"> </span>Introduction<span class="fc0 ls51 wsdb">, added three paragraph<span class="_ _6"></span>s </span></span></div><div class="t m0 x7 hc y9b ff5 fs6 fc0 sc0 ls8c ws0">to <span class="_ _2"></span><span class="fc1 ls6f wsdc">St<span class="_ _6"></span>ar<span class="_ _7"></span>va<span class="_ _6"></span>ti<span class="_ _6"></span>o<span class="_ _6"></span>n<span class="_ _6"></span> Sc<span class="_ _6"></span>e<span class="_ _6"></span>na<span class="_ _6"></span>ri<span class="_ _6"></span>o<span class="_ _6"></span>s<span class="fc0 ls49 wsdd"> se<span class="_ _6"></span>ction, and added </span><span class="ls3f wsde">29.2.5<span class="_ _f"> </span>Address Mapping<span class="fc0 ls8d wsdf"> h<span class="_ _6"></span>eading. Corrected<span class="_ _6"></span> </span></span></span></div><div class="t m0 x7 hc y9c ff5 fs6 fc0 sc0 ls38 ws37">spelling of <span class="_ _3"></span>“MCTRL<span class="_ _2"></span>” to “MCTL<span class="_ _2"></span>” in sections <span class="fc1 ls4f ws53">30.4<span class="_ _f"> </span>Program<span class="_ _3"></span>ming Guide for the PS-XADC </span></div><div class="t m0 x7 hc y9d ff5 fs6 fc1 sc0 ls45 ws0">Interface<span class="_ _6"></span><span class="fc0 ls3b ws4a"> and </span><span class="ls59">30.7.2<span class="_ _e"> </span>Resets<span class="fc0 ls3e">. </span></span></div><div class="t m0 x5 h5 y9e ff3 fs2 fc0 sc0 ls2a ws0">Date<span class="_ _8"> </span>V<span class="_ _2"></span>ersion<span class="_ _9"> </span>Revision</div><div class="c xb y3a w2 he"><div class="t m1 xc hf y3b ff7 fs7 fc2 sc0 ls5 ws0"><span class="fc3 sc0">Send F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">edback</span></div></div><a class="l" rel='nofollow' onclick='return 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622bada83d2fbb0007d19d48/bg5.jpg"><div class="t m0 x2 h5 y5 ff3 fs2 fc0 sc0 ls3 ws3">Zynq-7<span class="_ _2"></span>000 AP SoC T<span class="_ _2"></span>echnical R<span class="_ _2"></span>eference Man<span class="_ _3"></span>ual<span class="_ _4"> </span><span class="ff4 fc1 ls4 ws0">www<span class="_ _0"></span>.xilinx<span class="_ _3"></span>.co<span class="_ _3"></span>m<span class="_ _5"> </span><span class="ff3 fc0 ls5">5</span></span></div><div class="t m0 x2 h6 y6 ff4 fs2 fc0 sc0 ls6 ws4">U<span class="_ _3"></span>G585 (v1.10) Febru<span class="_ _3"></span>ary 23, 2015</div><div class="t m0 x6 hc y1 ff5 fs6 fc0 sc0 ls30 ws0">06/28/2013<span class="_ _a"> </span>1.6</div><div class="t m0 xd hc y67 ff5 fs6 fc0 sc0 ls5 ws0">(<span class="_ _6"></span><span class="ff6 ls58">Cont’<span class="_ _0"></span>d<span class="ff5 ls5">)</span></span></div><div class="t m0 x7 hc y1 ff5 fs6 fc0 sc0 ls3f wse0"> Added section <span class="fc1 ls8e wse1">31.5<span class="_ _f"> </span>Root<span class="_ _3"></span> Complex Us<span class="_ _3"></span>e Case<span class="fc0 ls66 wse2">. Added FIPS standa<span class="_ _3"></span>rds and clarif<span class="_ _6"></span>ied section </span></span></div><div class="t m0 x7 hc y67 ff5 fs6 fc1 sc0 ls4e ws0">32.1.2<span class="_ _e"> </span>Features<span class="fc0 ls48 ws42">, updated conf<span class="_ _6"></span>iguration <span class="_ _3"></span>f<span class="_ _6"></span>ile and secure boot pr<span class="_ _2"></span>ocess s<span class="_ _6"></span>t<span class="_ _3"></span>eps in </span></div><div class="t m0 x7 hc y68 ff5 fs6 fc1 sc0 ls45 ws0">Figure<span class="_"> </span>32-1<span class="fc0 ls2d wse3">, added boot time penalty to </span><span class="ls8f wse4">Pow<span class="_ _6"></span>e<span class="_ _6"></span>r o<span class="_ _6"></span>n<span class="_ _6"></span> Re<span class="_ _6"></span>se<span class="_ _6"></span>t<span class="_ _6"></span><span class="fc0 ls66 wse5"> section, changed “Secur<span class="_ _3"></span>e Boot” </span></span></div><div class="t m0 x7 hc y69 ff5 fs6 fc0 sc0 ls55 wse6">heading to ”<span class="fc1 ls6e wse7">Secure F<span class="_ _3"></span>SBL Decr<span class="_ _6"></span>yption<span class="fc0 wse8">”<span class="_ _2"></span>, changed “ROM code” to “OCM R<span class="_ _3"></span>OM Memor<span class="_ _6"></span>y” in </span></span></div><div class="t m0 x7 hc y6a ff5 fs6 fc1 sc0 ls6e ws0">Figure<span class="_"> </span>32-2<span class="fc0 ls55 wsc8"> and “ROM” to “OCM R<span class="_ _3"></span>OM” in <span class="fc1 ls7d ws0">T<span class="_ _d"></span>able<span class="_"> </span>32-3<span class="fc0 ls90 wsb1">,<span class="_ _6"></span> updated sectio<span class="_ _6"></span>ns </span><span class="ls69">32.2.7<span class="_ _f"> </span>Boot </span></span></span></div><div class="t m0 x7 hc y6b ff5 fs6 fc1 sc0 ls47 ws50">Image and Bi<span class="_ _6"></span>t<span class="_ _3"></span>stream Decr<span class="_ _6"></span>yp<span class="ls6a ws81">tion<span class="_ _6"></span> and Authentication<span class="fc0 ls3e ws0">, </span><span class="ls48 ws46">32.2.8<span class="_ _f"> </span>HMAC Signature<span class="fc0 ls3e ws0">, </span></span></span></div><div class="t m0 x7 hc y6c ff5 fs6 fc1 sc0 ls6a ws81">32.2.9<span class="_ _e"> </span>AES Key Management<span class="fc0 ls3e ws0">, </span><span class="ls54 ws9e">32.3.1<span class="_ _e"> </span>Non-Secure Boot St<span class="_ _2"></span>ate<span class="fc0 ls3e ws0">, </span><span class="ls2d ws60">32.3.4<span class="_ _e"> </span>Bo<span class="_ _6"></span>ot P<span class="_ _2"></span>ar<span class="_ _6"></span>tition </span></span></div><div class="t m0 x7 hc y6d ff5 fs6 fc1 sc0 ls42 ws0">Search<span class="fc0 ls48 ws42">, and <span class="_ _3"></span><span class="fc1 ls55 ws80">32.3.7<span class="_ _f"> </span>Secure Boot Modes of Operation<span class="_ _6"></span><span class="fc0 ls48 ws42"> (delet<span class="_ _3"></span>ed T<span class="_ _d"></span>able 32-4, “Non-secure </span></span></span></div><div class="t m0 x7 hc y6e ff5 fs6 fc0 sc0 ls54 ws9e">Boot Options”). Updated register database in sections <span class="fc1 ls65 ws67">B.3<span class="_ _f"> </span>Module Summar<span class="_ _6"></span>y<span class="_ _3"></span><span class="fc0 ls54 ws58"> through </span></span></div><div class="t m0 x7 hc y6f ff5 fs6 fc1 sc0 ls40 wse9">B.34<span class="_ _e"> </span>USB Controller (usb)<span class="fc0 ls41 ws4b"> in </span><span class="ls62 ws0">Appen<span class="_ _6"></span>dix<span class="_"> </span>B<span class="_ _3"></span><span class="fc0 ls5">.</span></span></div><div class="t m0 x6 hc y9f ff5 fs6 fc0 sc0 ls78 wsea">02/11/2014<span class="_ _a"> </span>1.7<span class="_ _b"> </span>Added 7z015 device, updated device not<span class="ls2f wseb">ices, and made minor cl<span class="ls2b wsec">arif<span class="_ _6"></span>ications throughout </span></span></div><div class="t m0 x7 hc ya0 ff5 fs6 fc0 sc0 ls64 ws66">document (denoted with change bars). Added section <span class="fc1 ls2e ws0">3.10<span class="_ _e"> </span>Implementation-Def<span class="_ _6"></span>ined </span></div><div class="t m0 x7 hc ya1 ff5 fs6 fc1 sc0 ls73 ws0">Conf<span class="_ _6"></span>igurat<span class="_ _3"></span>ions<span class="fc0 ls64 wsed">. Added sections </span><span class="ls64">5.7<span class="_ _e"> </span>Loopback<span class="fc0 ls36 wsee"> and </span><span class="ls2d wsef">5.8<span class="_ _f"> </span>Exclusive AXI Accesses<span class="fc0 ls6b wsb2">. R<span class="_ _3"></span>ework<span class="_ _3"></span>ed </span></span></span></div><div class="t m0 x7 hc ya2 ff5 fs6 fc1 sc0 ls36 wsaa">Chapter<span class="_ _13"> </span>6, Boot and Conf<span class="_ _6"></span>iguration<span class="_ _3"></span><span class="fc0 ls3e wsf0">. Added section <span class="fc1 ls7e wsab">7.2.4<span class="_ _e"> </span>Interr<span class="_ _6"></span>upt Sensitiv<span class="_ _6"></span>ity<span class="_ _2"></span>, T<span class="_ _0"></span>argeting<span class="_ _6"></span> </span></span></div><div class="t m0 x7 hc ya3 ff5 fs6 fc1 sc0 ls66 wsf1">and Handling<span class="fc0 ls4f wsf2">. Added sections </span><span class="ls8a wsf3">8.4.6<span class="_ _e"> </span>Clock Input Op<span class="_ _6"></span>tion for SWD<span class="_ _2"></span>T<span class="fc0 ls36 ws75"> and </span><span class="ls78 wsea">8.5.6<span class="_ _e"> </span>Clock Input </span></span></div><div class="t m0 x7 hc ya4 ff5 fs6 fc1 sc0 ls70 wsf4">Option fo<span class="_ _6"></span>r Counter/T<span class="_ _6"></span>imer<span class="fc0 ls45 wsd5">. Updated section </span><span class="ls35 ws5d">10.7<span class="_ _f"> </span>Register Ov<span class="_ _3"></span>er<span class="_ _6"></span>view<span class="fc0 ls52 ws56">. Added sectio<span class="_ _6"></span>n </span></span></div><div class="t m0 x7 hc ya5 ff5 fs6 fc1 sc0 ls37 wsf5">11.7<span class="_ _f"> </span>NOR Flas<span class="_ _3"></span>h Bandwid<span class="_ _2"></span>th<span class="fc0 ls66 wsac">. Added sections </span><span class="ls5f wsf6">AXI<span class="_ _6"></span> R<span class="_ _2"></span>ead Comm<span class="_ _6"></span>and Processing<span class="fc0 ls36 ws3a"> and </span></span></div><div class="t m0 x7 hc ya6 ff5 fs6 fc1 sc0 ls91 wsf7">12.2.7<span class="_ _e"> </span>Sup<span class="_ _6"></span>ported Memo<span class="_ _6"></span>ry Read and Write Comman<span class="_ _6"></span>ds<span class="fc0 ls35 ws5d">. Added section <span class="_ _3"></span><span class="fc1 ws0">16.1.4<span class="_ _e"> </span>Clock </span></span></div><div class="t m0 x7 hc ya7 ff5 fs6 fc1 sc0 ls59 ws0">Domains<span class="fc0 ws55"> an<span class="_ _6"></span>d rework<span class="_ _3"></span>ed sectio<span class="_ _6"></span>n <span class="fc1 ls78 wsb8">16.7<span class="_ _f"> </span>Known Issues</span><span class="ls2c ws43"> (previously titled “Limitations”<span class="_ _3"></span>. </span></span></div><div class="t m0 x7 hc ya8 ff5 fs6 fc0 sc0 ls5b ws4c">Updated section <span class="_ _3"></span><span class="fc1 ls35 ws61">21.1.2<span class="_ _f"> </span>PL <span class="_ _6"></span>R<span class="_ _2"></span>esources by Device T<span class="_ _2"></span>ype<span class="fc0 ws5d"> and added section </span><span class="ls42 ws0">21.3.4<span class="_ _f"> </span>GTP </span></span></div><div class="t m0 x7 hc ya9 ff5 fs6 fc1 sc0 ls8a wsf8">Low-P<span class="_ _3"></span>ower Serial T<span class="_ _0"></span>r<span class="_ _6"></span>ansceivers<span class="fc0 ls41 ws39">. Added </span><span class="ls65 ws67">P<span class="_ _2"></span>eripheral Clock G<span class="_ _d"></span>ating<span class="fc0 ls55 wsc8"> subsection. Updated </span></span></div><div class="t m0 x7 hc yaa ff5 fs6 fc1 sc0 ls7d ws0">T<span class="_ _d"></span>able<span class="_ _13"> </span>26-1<span class="fc0 ls3b wsf9"> and </span><span class="ls54">T<span class="_ _0"></span>able<span class="_"> </span>26-<span class="_ _6"></span>4<span class="fc0 ls48 wsfa">. Updat<span class="_ _3"></span>ed register dat<span class="_ _2"></span>abase in sections <span class="fc1 ls45 wsfb">B.3<span class="_ _f"> </span>Module Summar<span class="_ _6"></span>y</span><span class="ls5 ws0"> </span></span></span></div><div class="t m0 x7 hc yab ff5 fs6 fc0 sc0 ls88 ws0">thr<span class="_ _3"></span>ough <span class="fc1 ls67 wsc2">B.34<span class="_ _f"> </span>USB Contr<span class="_ _3"></span>oller (usb)<span class="_ _3"></span><span class="fc0 ls2c ws43"> in <span class="fc1 ls66 ws0">Appendix<span class="_"> </span>B<span class="fc0 ls5">.</span></span></span></span></div><div class="t m0 x6 hc yac ff5 fs6 fc0 sc0 ls6a ws0">09/16/2014<span class="_ _a"> </span>1.8<span class="_ _b"> </span>Added </div><div class="t m0 x15 ha yad ff5 fs2 fc0 sc0 ls29 wsfc">position informatio<span class="_ _6"></span>n for av<span class="_ _2"></span>ailable de<span class="ls92 wsfd">vice and package combinations for </span></div><div class="t m0 x7 ha yae ff5 fs2 fc0 sc0 ls93 wsfe">the signals associated with each G<span class="_ _2"></span>T se<span class="ls94 wsff">rial transceiver ch<span class="ls95 ws9c">annel to sectio<span class="_ _6"></span>ns </span></span></div><div class="t m0 x7 hc yaf ff5 fs6 fc1 sc0 ls8a wsf8">21.3.3<span class="_ _e"> </span>GTX Low-P<span class="_ _2"></span>ower Seria<span class="_ _6"></span>l T<span class="_ _d"></span>ran<span class="_ _6"></span>sceivers<span class="fc0 ls42 ws8e"> and </span><span class="ls35 ws61">21.3.4<span class="_ _e"> </span>GTP Low-P<span class="_ _2"></span>ower Serial </span></div><div class="t m0 x7 hc yb0 ff5 fs6 fc1 sc0 ls96 ws0">Tr<span class="_ _7"></span>a<span class="_ _6"></span>n<span class="_ _7"></span>s<span class="_ _7"></span>c<span class="_ _7"></span>e<span class="_ _7"></span>i<span class="_ _6"></span>v<span class="_ _7"></span>e<span class="_ _7"></span>r<span class="_ _7"></span>s<span class="_ _7"></span><span class="fc0 ls5">.</span></div><div class="t m0 x6 hc yb1 ff5 fs6 fc0 sc0 ls6a ws79">09/19/2014<span class="_ _b"> </span>1.8<span class="_ _6"></span>.1<span class="_ _15"> </span>R<span class="_ _3"></span>emoved err<span class="_ _3"></span>oneous banner from <span class="fc1 ls4f ws100">Chapter<span class="_"> </span>2<span class="_ _3"></span>1, Program<span class="_ _3"></span>mable Logic Descri<span class="_ _3"></span>ption<span class="fc0 ls3e ws0">. </span></span></div><div class="t m0 x7 hc yb2 ff5 fs6 fc0 sc0 ls64 ws0">Corrected <span class="ff6 ls56 ws5f">se<span class="_ _3"></span>nd feedback<span class="ff5 ls3e wsa0"> button clarity issue in footers.</span></span></div><div class="t m0 x6 hc yb3 ff5 fs6 fc0 sc0 ls78 wsea">11/17/2014<span class="_ _a"> </span>1.9<span class="_ _b"> </span>Added 7z035 device, updated device not<span class="ls2f wseb">ices, and made minor cl<span class="ls2b wsec">arif<span class="_ _6"></span>ications throughout </span></span></div><div class="t m0 x7 hc yb4 ff5 fs6 fc0 sc0 ls48 ws46">document (denoted with change bars).</div><div class="t m0 x6 hc yb5 ff5 fs6 fc0 sc0 ls46 ws59">11/19/2014<span class="_ _b"> </span>1.9<span class="_ _6"></span>.1<span class="_ _15"> </span>Corrected document date.</div><div class="t m0 x6 hc yb6 ff5 fs6 fc0 sc0 ls6a ws79">02/23/2015<span class="_ _16"> </span>1.10<span class="_ _17"> </span>Added clarif<span class="_ _6"></span>ication on the </div><div class="t m0 x16 ha yb7 ff5 fs2 fc0 sc0 ls97 ws101">timing relationship between PL power up and <span class="fs6 ls98 ws102">the PS </span></div><div class="t m0 x7 ha yb8 ff5 fs2 fc0 sc0 ls99 ws103">POR reset signal t<span class="_ _3"></span>o section <span class="fc1 ls9a ws104">2.2<span class="_ _14"> </span>Power Pins</span><span class="ls9b ws105"> and section <span class="fc1 ls9c ws0">6.3.3<span class="_ _c"> </span>BootROM </span></span></div><div class="t m0 x7 ha yb9 ff5 fs2 fc1 sc0 ls9d ws0">Pe<span class="_ _6"></span>r<span class="_ _6"></span>f<span class="_ _6"></span>o<span class="_ _6"></span>rm<span class="_ _6"></span>a<span class="_ _6"></span>n<span class="_ _6"></span>ce<span class="_ _6"></span><span class="fc0 ls95">: <span class="fc1 ws106">PS_PO<span class="_ _6"></span>R_B De-assertion Guidelines<span class="_ _6"></span></span><span class="ls5">.</span></span></div><div class="t m0 x5 h5 yba ff3 fs2 fc0 sc0 ls2a ws0">Date<span class="_ _8"> </span>V<span class="_ _2"></span>ersion<span class="_ _9"> </span>Revision</div><div class="c xb y3a w2 he"><div class="t m1 xc hf y3b ff7 fs7 fc2 sc0 ls5 ws0"><span class="fc3 sc0">Send F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">edback</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a 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