七人表决器VHDL.zip

  • hhdnob
    了解作者
  • VHDL
    开发工具
  • 29KB
    文件大小
  • zip
    文件格式
  • 0
    收藏次数
  • 10 积分
    下载积分
  • 0
    下载次数
  • 2020-07-01 10:35
    上传日期
这是一个七人表决器的模板,可以完成四人及以上同意的时候即为通过
七人表决器VHDL.zip
  • 七人表决器
  • 11.png
    23.6KB
  • bench.png
    7.2KB
  • 编译之后.txt
    3.4KB
  • decision.vhd
    2KB
内容介绍
-- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to -- suit user's needs .Comments are provided in each section to help the user -- fill out necessary details. -- *************************************************************************** -- Generated on "06/20/2020 15:45:01" -- Vhdl Test Bench template for design : decision -- -- Simulation tool : ModelSim-Altera (VHDL) -- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY decision_vhd_tst IS END decision_vhd_tst; ARCHITECTURE decision_arch OF decision_vhd_tst IS -- constants -- signals SIGNAL k1 : STD_LOGIC:='1'; SIGNAL K2 : STD_LOGIC:='1'; SIGNAL K3 : STD_LOGIC:='1'; SIGNAL K4 : STD_LOGIC:='1'; SIGNAL K5 : STD_LOGIC:='0'; SIGNAL K6 : STD_LOGIC:='1'; SIGNAL K7 : STD_LOGIC:='1'; SIGNAL ledag : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL m_Result : STD_LOGIC; COMPONENT decision PORT ( k1 : IN STD_LOGIC; K2 : IN STD_LOGIC; K3 : IN STD_LOGIC; K4 : IN STD_LOGIC; K5 : IN STD_LOGIC; K6 : IN STD_LOGIC; K7 : IN STD_LOGIC; ledag : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_Result : OUT STD_LOGIC ); END COMPONENT; BEGIN i1 : decision PORT MAP ( -- list connections between master ports and signals k1 => k1, K2 => K2, K3 => K3, K4 => K4, K5 => K5, K6 => K6, K7 => K7, ledag => ledag, m_Result => m_Result ); init : PROCESS -- variable declarations BEGIN -- code that executes only once WAIT; END PROCESS init; always : PROCESS -- optional sensitivity list -- ( ) -- variable declarations BEGIN -- code executes for every event on sensitivity list WAIT; END PROCESS always; END decision_arch;
评论
    相关推荐
    • 七人表决器 VHDL程序
      VHDL程序 EDA 七人表决器 七人表决器VHDL程序 EDA
    • 基于fpga的七人表决器
      基于alter公司cycloneII开发平台下的VHDL编程,实现了七人表决的功能,七个按键分别对应七个人,当有人同意时,按键按下,置“1”,当有人不同意时按键挑起,置“0”,同时LED灯会随着对应的按键按下变亮或者熄灭,...
    • VHDL 7人表决器
      这是一个基于VHDL语言的FPGA程序。它的功能就是实现7人表决。如果4或者4以上就通过。
    • 基于VHDL七人表决器的设计
      个开关作为表决器的7个输入变量,输入变量为逻辑“1”时表示表决者“赞同”;输入变量为逻辑“0”时,表示表决者“不赞同”。输出逻辑“1”时,表示表决“通过”;输出逻辑“0”时,表示表决“不通过”。当表决...
    • 七人表决器VHDL语言
      制作的七人表决器vhdl语言,有需要的朋友可以拿来看看呢,难度不大,计算机初学者可以做参考,简单的课程作业
    • VHDL语言实现四人表决器
      数字电路与逻辑设计实验,用Quartus 2软件VHDL语言实现的四人表决器
    • 人表决器VHDL语言编写
      人表决器VHDL语言编写,校园实验使用的,很好
    • 人表决器(VHDL)
      VHDL编写的五人表决器实验程序。三人以上同意通过,则结果为通过,否则不通过。
    • VHDL七人表决器.zip
      VHDL七人表决器含报告,四人及以上同意才算同意
    • Proteus7.12.rar
      Proteus7.12完美破解版.rar电路仿真软件很好用可以仿真单片数字模拟电路