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XC6SLX9数据手册,英文版,对该芯片的电气特性进行了说明。
XC6SLX9_datasheet.zip
  • XC6SLX9_datasheet.eeworld.com.cn_xilinx_xc6slx150t-n3fgg676c.pdf
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/6257598160196e4b84a5f3b9/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6257598160196e4b84a5f3b9/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">DS160 (v2.0) October 25, 2011<span class="_ _0"> </span><span class="fc1 ls1 ws1">www<span class="_ _1"></span>.xilinx.com</span></div><div class="t m0 x1 h2 y2 ff2 fs0 fc0 sc0 ls2 ws2">Product Specification<span class="_ _2"> </span><span class="ff1 ls3 ws1">1</span></div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls4 ws3">&#169; 2009&#8211;2011 Xilinx, I<span class="_ _3"></span>nc. Xilinx, the Xilinx logo<span class="_ _1"></span>, Ar<span class="_ _4"></span>tix, ISE, Ki<span class="_ _3"></span><span class="ls5 ws4">ntex<span class="_ _3"></span>, Spartan, Vir<span class="_ _4"></span>tex, Zynq, an<span class="_ _1"></span>d <span class="_ _4"></span>other designated br<span class="_ _3"></span>ands includ<span class="ls6 ws5">ed herein<span class="_ _3"></span> are tradema<span class="_ _1"></span>r<span class="_ _4"></span>ks of Xilinx in the Uni<span class="_ _3"></span>ted States </span></span></div><div class="t m0 x1 h3 y4 ff1 fs1 fc0 sc0 ls7 ws6">and other countries<span class="_ _3"></span>. PCI, PCIe and PCI Expre<span class="_ _3"></span>ss are trademarks of <span class="ws7">PCI-SIG and used under<span class="_ _1"></span> <span class="_ _4"></span>license. All ot<span class="_ _3"></span>her trademarks are the p<span class="ls6 ws8">roperty of their respectiv<span class="_ _3"></span>e owners<span class="_ _3"></span>.</span></span></div><div class="t m0 x1 h4 y5 ff2 fs2 fc0 sc0 ls8 ws9">General Description</div><div class="t m0 x1 h2 y6 ff1 fs0 fc0 sc0 ls9 wsa">The Spar<span class="_ _4"></span>tan&#174;-6<span class="_ _4"></span> f<span class="_ _1"></span>a<span class="_ _4"></span>mily provides leading system integration capabili<span class="lsa wsb">ties with the lowest total cost f<span class="_ _1"></span>or high-volume applications.<span class="lsb wsc"> The </span></span></div><div class="t m0 x1 h2 y7 ff1 fs0 fc0 sc0 lsc wsd">thir<span class="_ _4"></span>teen-membe<span class="_ _4"></span>r family deliv<span class="_ _1"></span>ers expanded densities ranging fro<span class="_ _4"></span>m <span class="lsb wse">3,840 to 147,44<span class="_ _4"></span>3 logic cells, with half the<span class="_ _4"></span> power consumption o<span class="lsd wsf">f previous </span></span></div><div class="t m0 x1 h2 y8 ff1 fs0 fc0 sc0 ls9 wsa">Spar<span class="_ _4"></span>tan families, <span class="_ _3"></span>and faster<span class="_ _1"></span>, more comprehensive connectivity<span class="_ _5"></span>. Built on a mature 45<span class="_"> </span>nm low-power copper process technology that </div><div class="t m0 x1 h2 y9 ff1 fs0 fc0 sc0 lsc ws10">delivers the optimal balance of cost, power<span class="_ _1"></span>, and perf<span class="_ _1"></span>o<span class="_ _4"></span>rman<span class="_ _4"></span>ce, the <span class="ls9 ws11">Spar<span class="_ _4"></span>tan-6 family off<span class="_ _1"></span>ers a new<span class="_ _1"></span>, more efficient, dual-regi<span class="_ _4"></span>ster <span class="lsa ws12">6-input look-</span></span></div><div class="t m0 x1 h2 ya ff1 fs0 fc0 sc0 ls9 wsa">up table (LUT) logic and a rich selection of built-in system-lev<span class="_ _1"></span>el<span class="lse ws13"> blocks<span class="_ _3"></span>. These include 18<span class="_"> </span>Kb (2<span class="_"> </span>x<span class="_"> </span>9<span class="_"> </span>Kb) bloc<span class="_ _1"></span>k RAMs, second genera<span class="lsf ws1">tion </span></span></div><div class="t m0 x1 h2 yb ff1 fs0 fc0 sc0 ls10 ws14">DSP48A1 slices, SDRAM memor<span class="_ _4"></span>y controllers, enhanced mixed-mode clock management bloc<span class="_ _1"></span>ks, SelectIO&#8482; technolog<span class="_ _4"></span>y<span class="_ _5"></span>, power-</div><div class="t m0 x1 h2 yc ff1 fs0 fc0 sc0 ls11 ws15">optimized high-speed serial transceiver bloc<span class="_ _1"></span>ks, PCI Express&#174; <span class="ws16">compatible Endpoint blocks<span class="_ _3"></span>, advanced system-le<span class="_ _1"></span>vel power management<span class="ls3 ws1"> </span></span></div><div class="t m0 x1 h2 yd ff1 fs0 fc0 sc0 lse ws17">modes, auto-detect configuration options<span class="_ _3"></span>, and enhanced IP secur<span class="_ _4"></span>ity<span class="ls11 ws18"> with AES <span class="_ _4"></span>and Device DNA protec<span class="ls12 ws19">tion. These features provide a<span class="ls13 ws1a"> low-</span></span></span></div><div class="t m0 x1 h2 ye ff1 fs0 fc0 sc0 ls1 ws1b">cost programmab<span class="_ _3"></span>le alter<span class="_ _4"></span>native to custom ASIC products with unprec<span class="_ _4"></span><span class="lse ws17">edented ease <span class="_ _4"></span>of use. Spar<span class="_ _4"></span>tan-6 <span class="ls0 ws1c">FPGAs offer the best solution f<span class="_ _1"></span><span class="ls14 ws1">or </span></span></span></div><div class="t m0 x1 h2 yf ff1 fs0 fc0 sc0 ls15 ws1d">high-volume logic designs, consumer-oriented DSP designs, and <span class="ls11 ws15">cost-sensitive embedded applicatio<span class="ls16 ws1e">ns. Spar<span class="_ _4"></span>tan-6 FPGAs are the </span></span></div><div class="t m0 x1 h2 y10 ff1 fs0 fc0 sc0 lse ws13">programmab<span class="_ _3"></span>le silicon foundation f<span class="_ _1"></span>or T<span class="_ _5"></span>argeted Design Platforms t<span class="ls1 ws1b">hat deliver integrated softw<span class="_ _1"></span>are <span class="_ _4"></span>and hardware components that en<span class="_ _4"></span>a<span class="ls17 ws1">bl<span class="_ _4"></span>e </span></span></div><div class="t m0 x1 h2 y11 ff1 fs0 fc0 sc0 ls9 ws16">designers to focus on innovation as soon as their dev<span class="_ _1"></span>elopment cycle <span class="_ _4"></span>begins.</div><div class="t m0 x1 h4 y12 ff2 fs2 fc0 sc0 ls18 ws1f">Summary of Spar<span class="_ _4"></span>ta<span class="_ _4"></span><span class="ls19 ws20">n-6 FPGA Features</span></div><div class="t m0 x1 h2 y13 ff1 fs0 fc0 sc0 ls12 ws19">&#8226;<span class="_ _6"> </span>Spar<span class="_ _4"></span>tan-6 Family:</div><div class="t m0 x2 h2 y14 ff1 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _6"> </span>Spar<span class="_ _4"></span>tan-6 LX FPGA: L<span class="_ _4"></span>ogic optimized</div><div class="t m0 x2 h2 y15 ff1 fs0 fc0 sc0 ls1a ws21">&#8226;<span class="_ _6"> </span>Spar<span class="_ _4"></span>tan-6 LXT FPGA: High-speed ser<span class="_ _4"></span>ial connectivity</div><div class="t m0 x1 h2 y16 ff1 fs0 fc0 sc0 ls1b ws22">&#8226;<span class="_ _6"> </span>Designed for low cost</div><div class="t m0 x2 h2 y17 ff1 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _6"> </span>Multiple efficient integrated bloc<span class="_ _1"></span>ks</div><div class="t m0 x2 h2 y18 ff1 fs0 fc0 sc0 ls0 ws0">&#8226;<span class="_ _6"> </span>Optimized selection of I/O standards</div><div class="t m0 x2 h2 y19 ff1 fs0 fc0 sc0 ls1c ws23">&#8226;<span class="_ _6"> </span>Staggered pads</div><div class="t m0 x2 h2 y1a ff1 fs0 fc0 sc0 ls12 ws19">&#8226;<span class="_ _6"> </span>High-volume plastic wire-bonded p<span class="_ _4"></span>ackages</div><div class="t m0 x1 h2 y1b ff1 fs0 fc0 sc0 ls11 ws15">&#8226;<span class="_ _6"> </span>Low static and dynamic powe<span class="_ _3"></span>r</div><div class="t m0 x2 h2 y1c ff1 fs0 fc0 sc0 ls10 ws24">&#8226;<span class="_ _6"> </span>45<span class="_"> </span>nm process optimized f<span class="_ _1"></span>or cost and low power</div><div class="t m0 x2 h2 y1d ff1 fs0 fc0 sc0 ls10 ws13">&#8226;<span class="_ _6"> </span>Hibern<span class="_ _4"></span>ate power-do<span class="_ _1"></span>wn mode<span class="_ _4"></span> f<span class="_ _1"></span>o<span class="_ _4"></span>r zero po<span class="_ _1"></span>wer</div><div class="t m0 x2 h2 y1e ff1 fs0 fc0 sc0 ls1d ws25">&#8226;<span class="_ _6"> </span>Suspend mode mainta<span class="_ _4"></span>ins stat<span class="ls1e ws26">e and configuration<span class="_ _4"></span> with </span></div><div class="t m0 x3 h2 y1f ff1 fs0 fc0 sc0 ls1 ws27">multi-pin wak<span class="_ _1"></span>e-up, control enhancement</div><div class="t m0 x2 h2 y20 ff1 fs0 fc0 sc0 ls1 ws27">&#8226;<span class="_ _6"> </span>Lower-po<span class="_ _1"></span>wer 1.0V core voltage (LX FPGAs, -1L only)</div><div class="t m0 x2 h2 y21 ff1 fs0 fc0 sc0 ls1a ws21">&#8226;<span class="_ _6"> </span>High perf<span class="_ _3"></span>or<span class="_ _4"></span>mance 1.2V core vo<span class="_ _3"></span>ltage (LX and LXT </div><div class="t m0 x3 h2 y22 ff1 fs0 fc0 sc0 lsa wsb">FPGAs, -2, -3, and -3N speed gr<span class="_ _3"></span>ades)</div><div class="t m0 x1 h2 y23 ff1 fs0 fc0 sc0 ls16 ws28">&#8226;<span class="_ _6"> </span>Multi-voltage, m<span class="_ _3"></span>ulti-standard SelectIO&#8482; in<span class="_ _4"></span>terface banks</div><div class="t m0 x2 h2 y24 ff1 fs0 fc0 sc0 ls15 ws1d">&#8226;<span class="_ _6"> </span>Up to 1,080<span class="_"> </span>Mb/s data transf<span class="_ _3"></span>er rate per diff<span class="_ _3"></span>erential I/O</div><div class="t m0 x2 h2 y25 ff1 fs0 fc0 sc0 ls9 ws1d">&#8226;<span class="_ _6"> </span>Selectable output drive, up to 24<span class="_ _7"> </span>mA per pin</div><div class="t m0 x2 h2 y26 ff1 fs0 fc0 sc0 ls10 ws24">&#8226;<span class="_ _6"> </span>3.3V to 1.2V I/O standards and protocols</div><div class="t m0 x2 h2 y27 ff1 fs0 fc0 sc0 ls1f ws29">&#8226;<span class="_ _6"> </span>Low-cost HSTL and SSTL memory interf<span class="_ _3"></span>aces</div><div class="t m0 x2 h2 y28 ff1 fs0 fc0 sc0 ls10 ws24">&#8226;<span class="_ _6"> </span>Hot s<span class="_ _1"></span>wap compliance</div><div class="t m0 x2 h2 y29 ff1 fs0 fc0 sc0 ls3 ws2a">&#8226;<span class="_ _6"> </span>Adjustable I<span class="_ _3"></span>/O slew<span class="_ _3"></span> rates to im<span class="_ _3"></span>prov<span class="_ _1"></span>e signal integrity</div><div class="t m0 x1 h2 y2a ff1 fs0 fc0 sc0 ls15 ws1d">&#8226;<span class="_ _6"> </span>High-speed GTP seri<span class="_ _4"></span>al transceivers in the LXT FPGAs</div><div class="t m0 x2 h2 y2b ff1 fs0 fc0 sc0 lsa wsb">&#8226;<span class="_ _6"> </span>Up to 3.2<span class="_"> </span>Gb/s</div><div class="t m0 x2 h2 y2c ff1 fs0 fc0 sc0 ls20 ws2b">&#8226;<span class="_ _6"> </span>High-speed interfaces including: Serial A<span class="_ _5"></span>T<span class="_ _5"></span>A, A<span class="_ _1"></span>urora, </div><div class="t m0 x3 h2 y2d ff1 fs0 fc0 sc0 ls20 ws2b">1G<span class="_"> </span>Etherne<span class="_ _4"></span>t, PCI Express, OBSAI, CPRI, EPON, </div><div class="t m0 x3 h2 y2e ff1 fs0 fc0 sc0 ls21 ws2c">GPON, Displa<span class="_ _1"></span>yPort, and XA<span class="_ _3"></span>UI</div><div class="t m0 x1 h2 y2f ff1 fs0 fc0 sc0 lsa wsb">&#8226;<span class="_ _6"> </span>Integrated Endpoint bloc<span class="_ _1"></span>k for PCI Express designs (LXT)</div><div class="t m0 x1 h2 y30 ff1 fs0 fc0 sc0 ls15 ws2d">&#8226;<span class="_ _6"> </span>Low-cost PCI&#174; technology suppor<span class="_ _8"></span>t compatible with the </div><div class="t m0 x2 h2 y31 ff1 fs0 fc0 sc0 ls16 ws1e">33<span class="_"> </span>MHz, 32- and 64-bit specification.</div><div class="t m0 x1 h2 y32 ff1 fs0 fc0 sc0 ls1 ws1b">&#8226;<span class="_ _6"> </span>Efficient DSP48A1 slices</div><div class="t m0 x2 h2 y33 ff1 fs0 fc0 sc0 ls15 ws2d">&#8226;<span class="_ _6"> </span>High-performance ar<span class="_ _4"></span>ithmetic and sign<span class="_ _4"></span>al processing</div><div class="t m0 x2 h2 y34 ff1 fs0 fc0 sc0 ls9 ws16">&#8226;<span class="_ _6"> </span>F<span class="_ _1"></span>ast 18<span class="_"> </span>x<span class="_"> </span>18<span class="_ _4"></span> multiplier and 48-bit a<span class="_ _4"></span>ccumulator</div><div class="t m0 x2 h2 y35 ff1 fs0 fc0 sc0 ls16 ws28">&#8226;<span class="_ _6"> </span>Pipelining and casca<span class="_ _4"></span>ding capability</div><div class="t m0 x2 h2 y36 ff1 fs0 fc0 sc0 lsa wsb">&#8226;<span class="_ _6"> </span>Pre-adder to assist filter applications</div><div class="t m0 x4 h2 y37 ff1 fs0 fc0 sc0 lsc ws2e">&#8226;<span class="_ _6"> </span>Integrated Memor<span class="_ _4"></span>y Controller blocks</div><div class="t m0 x5 h2 y38 ff1 fs0 fc0 sc0 ls15 ws1d">&#8226;<span class="_ _6"> </span>DDR, DDR2, DDR3, and LPDDR suppor<span class="_ _8"></span>t</div><div class="t m0 x5 h2 y39 ff1 fs0 fc0 sc0 ls16 ws28">&#8226;<span class="_ _6"> </span>Data rates up to </div><div class="t m0 x6 h2 y3a ff1 fs3 fc0 sc0 ls22 ws2f">800<span class="_"> </span>Mb/s (<span class="fs0 ls9 wsa">12.8<span class="_"> </span>Gb/s peak bandwidth)</span></div><div class="t m0 x5 h2 y3b ff1 fs0 fc0 sc0 ls9 ws30">&#8226;<span class="_ _6"> </span>Multi-por<span class="_ _4"></span>t bus structure with<span class="_ _4"></span> independent FIFO to reduce </div><div class="t m0 x7 h2 y3c ff1 fs0 fc0 sc0 ls12 ws31">design timing issues</div><div class="t m0 x4 h2 y3d ff1 fs0 fc0 sc0 ls11 ws15">&#8226;<span class="_ _6"> </span>Abundant logic resources with increased logic capacity</div><div class="t m0 x5 h2 y3e ff1 fs0 fc0 sc0 ls16 ws1e">&#8226;<span class="_ _6"> </span>Optional shift register or<span class="ls12 ws31"> distr<span class="_ _4"></span>ibuted RAM suppor<span class="_ _4"></span>t</span></div><div class="t m0 x5 h2 y3f ff1 fs0 fc0 sc0 ls9 ws16">&#8226;<span class="_ _6"> </span>Efficient 6-input <span class="_ _4"></span>LUTs<span class="fc2 ls3 ws1"> </span><span class="wsa">improv<span class="_ _1"></span>e performan<span class="_ _4"></span>ce and </span></div><div class="t m0 x7 h2 y40 ff1 fs0 fc0 sc0 ls23 ws32">minimize power</div><div class="t m0 x5 h2 y41 ff1 fs0 fc0 sc0 lse ws13">&#8226;<span class="_ _6"> </span>LUT with dual flip-flops fo<span class="ls1 ws27">r pipeline centric applications</span></div><div class="t m0 x4 h2 y42 ff1 fs0 fc0 sc0 ls9 wsa">&#8226;<span class="_ _6"> </span>Block RAM with a wide range of g<span class="_ _3"></span>ranularity</div><div class="t m0 x5 h2 y43 ff1 fs0 fc0 sc0 ls1 ws1b">&#8226;<span class="_ _6"> </span>F<span class="_ _1"></span>ast block RAM with byte write enable</div><div class="t m0 x5 h2 y44 ff1 fs0 fc0 sc0 ls1 wsb">&#8226;<span class="_ _6"> </span>18<span class="_"> </span>Kb bloc<span class="_ _1"></span>ks that can be opti<span class="_ _4"></span>onally programmed as two </div><div class="t m0 x7 h2 y45 ff1 fs0 fc0 sc0 ls9 wsa">independent 9<span class="_"> </span>Kb block RAMs</div><div class="t m0 x4 h2 y46 ff1 fs0 fc0 sc0 ls9 wsa">&#8226;<span class="_ _6"> </span>Clock Management Tile (CMT) f<span class="_ _3"></span>or enhanced performance</div><div class="t m0 x5 h2 y47 ff1 fs0 fc0 sc0 ls9 ws33">&#8226;<span class="_ _6"> </span>Low noise, fle<span class="_ _1"></span>xible clocking</div><div class="t m0 x5 h2 y48 ff1 fs0 fc0 sc0 ls1 ws27">&#8226;<span class="_ _6"> </span>Digital Clock Managers (DCMs) eliminate clock sk<span class="_ _3"></span>ew </div><div class="t m0 x7 h2 y49 ff1 fs0 fc0 sc0 ls3 ws34">and duty cycle distor<span class="_ _4"></span>tion</div><div class="t m0 x5 h2 y4a ff1 fs0 fc0 sc0 lsa wsb">&#8226;<span class="_ _6"> </span>Phase-Lock<span class="_ _3"></span>ed Loops (PLLs) for lo<span class="_ _1"></span>w-jitter clocking</div><div class="t m0 x5 h2 y4b ff1 fs0 fc0 sc0 ls24 ws35">&#8226;<span class="_ _6"> </span>F<span class="_ _1"></span>requency synthesis with si<span class="ls12 ws31">multaneous multiplication, </span></div><div class="t m0 x7 h2 y4c ff1 fs0 fc0 sc0 ls16 ws1e">division, and phase shifting</div><div class="t m0 x5 h2 y4d ff1 fs0 fc0 sc0 ls16 wsc">&#8226;<span class="_ _6"> </span>Sixteen low-ske<span class="_ _3"></span>w global clock networks</div><div class="t m0 x4 h2 y4e ff1 fs0 fc0 sc0 lsa wsb">&#8226;<span class="_ _6"> </span>Simplified configuration, <span class="lse ws17">suppor<span class="_ _4"></span>ts l<span class="_ _4"></span>ow-cost standards</span></div><div class="t m0 x5 h2 y4f ff1 fs0 fc0 sc0 ls1 ws27">&#8226;<span class="_ _6"> </span>2-pin auto-detect configuration</div><div class="t m0 x5 h2 y50 ff1 fs0 fc0 sc0 ls1 ws36">&#8226;<span class="_ _6"> </span>Broad third-par<span class="_ _4"></span>ty SPI (up<span class="_ _4"></span> to x4) and NOR <span class="_ _4"></span>flash suppor<span class="_ _8"></span>t</div><div class="t m0 x5 h2 y51 ff1 fs0 fc0 sc0 ls25 ws37">&#8226;<span class="_ _6"> </span>Feature rich Xilin<span class="_ _4"></span>x Platform Flash with JT<span class="_ _5"></span>AG</div><div class="t m0 x5 h2 y52 ff1 fs0 fc0 sc0 ls1 ws1b">&#8226;<span class="_ _6"> </span>MultiBoot suppor<span class="_ _8"></span>t f<span class="_ _1"></span>o<span class="_ _4"></span>r remote upgrade with multiple </div><div class="t m0 x7 h2 y53 ff1 fs0 fc0 sc0 ls1 wsb">bitstreams, using watchdog protection</div><div class="t m0 x4 h2 y54 ff1 fs0 fc0 sc0 ls15 ws1d">&#8226;<span class="_ _6"> </span>Enhanced secur<span class="_ _4"></span>ity f<span class="_ _3"></span>or design protection</div><div class="t m0 x5 h2 y55 ff1 fs0 fc0 sc0 ls16 ws1e">&#8226;<span class="_ _6"> </span>Unique Device DNA identifier f<span class="_ _1"></span>or design authenti<span class="_ _4"></span>cation</div><div class="t m0 x5 h2 y56 ff1 fs0 fc0 sc0 ls26 ws38">&#8226;<span class="_ _6"> </span>AES bitstream encryption in the larger <span class="_ _4"></span>devices</div><div class="t m0 x4 h2 y57 ff1 fs0 fc0 sc0 ls1a ws21">&#8226;<span class="_ _6"> </span>F<span class="_ _1"></span>aster embedded processing with enhance<span class="_ _4"></span>d, low cost, </div><div class="t m0 x5 h2 y58 ff1 fs0 fc0 sc0 ls21 ws39">MicroBlaze&#8482; soft process<span class="_ _3"></span>or</div><div class="t m0 x4 h2 y59 ff1 fs0 fc0 sc0 ls1 ws27">&#8226;<span class="_ _6"> </span>Industr<span class="_ _4"></span>y-leading IP and reference designs</div><div class="t m0 x8 h5 y5a ff1 fs4 fc3 sc0 ls27 ws1">11</div><div class="t m0 x9 h6 y5b ff2 fs5 fc0 sc0 ls28 ws3a">Spar<span class="_ _4"></span>tan-6 Famil<span class="_ _1"></span>y Over<span class="_ _4"></span>view</div><div class="t m0 x1 h5 y5c ff1 fs4 fc0 sc0 ls29 ws3b">DS160 (v2.0) Octobe<span class="_ _3"></span>r 25, 2011<span class="_ _9"> </span><span class="ff2 ls2a">Product Specific<span class="_ _1"></span>ation</span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>
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