LPC4350_30_20_10.pdf.zip

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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM, advanced configurable peripherals such as the State Configurable Timer/PWM (SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO) interface, two high-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. The LPC4350/30/20/10 operate at CPU frequencies of up to 204 MHz.
LPC4350_30_20_10.pdf.zip
  • LPC4350_30_20_10.pdf
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/62572d9e60196e4b849cbc0c/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62572d9e60196e4b849cbc0c/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h3 y2 ff2 fs1 fc1 sc0 ls1 ws1">1. General <span class="_ _0"></span>description</div><div class="t m0 x1 h4 y3 ff1 fs2 fc2 sc0 ls2 ws2">The LPC4350/30/2<span class="_ _1"></span>0/10 are ARM Cor<span class="_ _1"></span>tex-M<span class="ls3 ws3">4 based microcontroller<span class="_ _1"></span>s for embedded </span></div><div class="t m0 x1 h4 y4 ff1 fs2 fc2 sc0 ls4 ws4">applications which include an ARM Cortex<span class="ls5 ws5">-M0 coprocessor<span class="_ _1"></span>, up to 26<span class="_ _1"></span>4 kB of SRAM, </span></div><div class="t m0 x1 h4 y5 ff1 fs2 fc2 sc0 ls5 ws5">advanced configurable pe<span class="_ _1"></span>ripherals such<span class="ls6 ws6"> <span class="_ _1"></span>as the S<span class="_ _2"></span>tate Co<span class="_ _1"></span>nfigurable T<span class="_ _2"></span>imer/PWM </span></div><div class="t m0 x1 h4 y6 ff1 fs2 fc2 sc0 ls7 ws7">(SCT<span class="_ _2"></span>imer/PWM) and the Se<span class="_ _2"></span>rial General-Purp<span class="ls8 ws8">ose I/O (SGPIO)<span class="_ _1"></span> interface, two hi<span class="_ _1"></span>gh-speed </span></div><div class="t m0 x1 h4 y7 ff1 fs2 fc2 sc0 ls9 ws9">USB controllers, Ethernet, L<span class="_ _2"></span>C<span class="_ _3"></span>D, an external <span class="lsa wsa">memory controller<span class="_ _2"></span>, and multiple digital and </span></div><div class="t m0 x1 h4 y8 ff1 fs2 fc2 sc0 lsb wsb">analog peripherals. The LPC4<span class="ls8 wsc">3<span class="_ _1"></span>50/30/20/10 operate at CPU frequencies of up to 204 </span></div><div class="t m0 x1 h4 y9 ff1 fs2 fc2 sc0 lsa ws0">MHz.</div><div class="t m0 x1 h4 ya ff1 fs2 fc2 sc0 ls5 wsd">The ARM Cortex-M4 <span class="_ _1"></span>is a 32-bit core that<span class="_ _1"></span> offers <span class="_ _2"></span>system enhancements such as low <span class="_ _1"></span>power </div><div class="t m0 x1 h4 yb ff1 fs2 fc2 sc0 ls5 wse">consumption, enhanced deb<span class="_ _2"></span>ug features, and a <span class="_ _3"></span>hi<span class="ls6 wsf">gh level of suppo<span class="_ _2"></span>rt block integration. The </span></div><div class="t m0 x1 h4 yc ff1 fs2 fc2 sc0 lsc ws10">ARM Cortex-M<span class="_ _3"></span>4 CPU incorp<span class="_ _3"></span>orates a 3-<span class="_ _3"></span>stage pi<span class="lsd ws11">peline, uses a Harvard architecture with </span></div><div class="t m0 x1 h4 yd ff1 fs2 fc2 sc0 ls8 wsc">separate local<span class="_ _1"></span> instruction and data<span class="_ _2"></span> <span class="_ _3"></span>buses as well as a third bus for peripherals, an<span class="_ _1"></span>d </div><div class="t m0 x1 h4 ye ff1 fs2 fc2 sc0 lsb wsb">includes an internal pr<span class="_ _1"></span>efetch unit that<span class="ls5 ws5"> support<span class="_ _2"></span>s speculative branching. The ARM </span></div><div class="t m0 x1 h4 yf ff1 fs2 fc2 sc0 lse ws12">Cortex-M4 supp<span class="_ _3"></span>orts single-cycle digital si<span class="ls8 wsc">gnal processing and SIMD instructions. A </span></div><div class="t m0 x1 h4 y10 ff1 fs2 fc2 sc0 lsf ws13">hardware floating-<span class="_ _1"></span>point processor <span class="_ _2"></span>is integrated in the core. </div><div class="t m0 x1 h4 y11 ff1 fs2 fc2 sc0 ls10 wse">The ARM Cortex-M0 coprocessor is an energ<span class="_ _2"></span>y-eff<span class="ls6 wsf">icient and easy-t<span class="_ _1"></span>o-use 32-bit core which </span></div><div class="t m0 x1 h4 y12 ff1 fs2 fc2 sc0 ls3 ws3">is code- and tool-comp<span class="_ _2"></span>atible with the Cortex<span class="ls11 ws14">-M4 core. <span class="_ _3"></span>The Cortex<span class="_ _3"></span>-M0 coproc<span class="_ _3"></span>essor offers </span></div><div class="t m0 x1 h4 y13 ff1 fs2 fc2 sc0 lsf ws15">up to 204 MHz performance with a simple instruction set and redu<span class="_ _2"></span>ced code size. In </div><div class="t m0 x1 h4 y14 ff1 fs2 fc2 sc0 lsc ws10">LPC43x0, th<span class="_ _3"></span>e Cortex-M0<span class="_ _3"></span> coprocessor <span class="_ _3"></span>hardware m<span class="_ _3"></span>ultiply is implem<span class="_ _3"></span>ented as a <span class="_ _3"></span>32-cycle </div><div class="t m0 x1 h4 y15 ff1 fs2 fc2 sc0 ls12 ws16">iterative multiplier<span class="_ _2"></span>. </div><div class="t m0 x1 h4 y16 ff1 fs2 fc2 sc0 ls13 ws0">See <span class="fc3 lsb wsb">Section 17 &#8220;</span></div><div class="t m0 x3 h4 y17 ff1 fs2 fc3 sc0 ls14 ws0">References<span class="_ _1"></span><span class="ls0">&#8221;<span class="fc2 ls8 wsc"> for additional document<span class="_ _2"></span>ation.</span></span></div><div class="t m0 x2 h3 y18 ff2 fs1 fc1 sc0 ls15 ws17">2. <span class="_ _4"> </span>Features and benefit<span class="_ _2"></span>s</div><div class="t m0 x1 h4 y19 ff3 fs2 fc1 sc0 ls0 ws0">&#61550;<span class="_ _5"> </span><span class="ff1 fc2 lse ws12">Cortex-M4 Proce<span class="_ _3"></span>ssor core</span></div><div class="t m0 x4 h4 y1a ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls8 wsc">ARM Cortex-M4 processor<span class="_ _2"></span>, running<span class="_ _2"></span> <span class="_ _3"></span>at frequencies of up to 204<span class="_"> </span>MHz.</span></div><div class="t m0 x4 h4 y1b ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls8 wsc">Built-in Memory Protection Unit (MPU) su<span class="_ _2"></span>pporting eight regions.</span></div><div class="t m0 x4 h4 y1c ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls16 ws18">Built-in Nested V<span class="_ _2"></span>ectored In<span class="ls17 ws19">terrupt Controller (NVIC).</span></span></div><div class="t m0 x4 h4 y1d ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls12 ws16">Hardware floatin<span class="lse ws1a">g-point u<span class="_ _3"></span>nit.</span></span></div><div class="t m0 x4 h4 y1e ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls4 ws4">Non-maskable Inte<span class="ls18 ws1b">rrupt (NM<span class="_ _3"></span>I) input.</span></span></div><div class="t m0 x4 h4 y1f ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls19 ws1c">JT<span class="_ _2"></span>AG and Ser<span class="_ _2"></span>ial Wire Debug (SWD), serial <span class="ls1a ws1d">trace, eight breakpo<span class="_ _2"></span>ints, and four watch<span class="_ _2"></span> </span></span></div><div class="t m0 x5 h4 y20 ff1 fs2 fc2 sc0 lse ws0">points.</div><div class="t m0 x4 h4 y21 ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls1b ws1e">Enhanced Trace Module (ET<span class="_ _3"></span>M) and Enha<span class="_ _3"></span>nced Trace Buffer (ETB) support.</span></div><div class="t m0 x4 h4 y22 ff3 fs2 fc1 sc0 ls0 ws0">&#61557;<span class="_ _6"> </span><span class="ff1 fc2 ls13 ws1f">System tick timer<span class="_ _2"></span>.</span></div><div class="t m0 x6 h5 y23 ff2 fs3 fc1 sc0 ls1c ws0">LPC4350/30/20/10</div><div class="t m0 x6 h6 y24 ff2 fs4 fc1 sc0 ls1d ws20">32-bit ARM Cortex-M4/M<span class="ls1e ws21">0 flashless M<span class="_ _3"></span>CU; up to 264 kB SRAM; </span></div><div class="t m0 x6 h6 y25 ff2 fs4 fc1 sc0 ls1f ws22">Ethernet; two HS US<span class="ls1d ws23">Bs; advanced confi<span class="ls20 ws24">gurable peripherals</span></span></div><div class="t m0 x6 h7 y26 ff2 fs5 fc1 sc0 ls21 ws25">Rev<span class="_ _7"></span>. 4.6 &#8212; 14 March 2016<span class="_ _8"> </span>Product dat<span class="_ _2"></span>a sheet</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>
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