MASTER_RWOK_07131900.rar

Release 14.7 - par P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Sat Jul 13 10:51:37 2019 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: 1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. 2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. 3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator. INPUT FILE: MASTER_map.ncd OUTPUT FILE: MASTER_pad.txt PART TYPE: xa7a100t SPEED GRADE: -2i PACKAGE: csg324 Pinout by Pin Number: +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |A1 | |IOB33S |IO_L9N_T1_DQS_AD7N_35 |UNUSED | |35 | | | | | | | | | |A2 | | |GND | | | | | | | | | | | | |A3 | |IOB33S |IO_L8N_T1_AD14N_35 |UNUSED | |35 | | | | | | | | | |A4 |I_rst_n |IOB |IO_L8P_T1_AD14P_35 |INPUT |LVCMOS18* |35 | | | |NONE | |UNLOCATED |NO |NONE | |A5 |I_cmd_code<6> |IOB |IO_L3N_T0_DQS_AD5N_35 |INPUT |LVCMOS18* |35 | | | |NONE | |UNLOCATED |NO |NONE | |A6 |I_cmd_code<4> |IOB |IO_L3P_T0_DQS_AD5P_35 |INPUT |LVCMOS18* |35 | | | |NONE | |UNLOCATED |NO |NONE | |A7 | | |VCCO_35 | | |35 | | | | |1.80 | | | | |A8 | |IOB33S |IO_L12N_T1_MRCC_16 |UNUSED | |16 | | | | | | | | | |A9 | |IOB33S |IO_L14N_T2_SRCC_16 |UNUSED | |16 | | | | | | | | | |A10 | |IOB33M |IO_L14P_T2_SRCC_16 |UNUSED | |16 | | | | | | | | | |A11 |I_qspi_addr<8> |IOB |IO_L4N_T0_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |A12 | | |GND | | | | | | | | | | | | |A13 |I_qspi_addr<17> |IOB |IO_L9P_T1_DQS_AD3P_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |A14 |I_qspi_addr<18> |IOB |IO_L9N_T1_DQS_AD3N_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |A15 |I_qspi_addr<15> |IOB |IO_L8P_T1_AD10P_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |A16 |I_qspi_addr<16> |IOB |IO_L8N_T1_AD10N_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |A17 | | |VCCO_15 | | |15 | | | | |1.80 | | | | |A18 |I_qspi_addr<20> |IOB |IO_L10N_T1_AD11N_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |B1 | |IOB33M |IO_L9P_T1_DQS_AD7P_35 |UNUSED | |35 | | | | | | | | | |B2 |O_read_byte_valid|IOB |IO_L10N_T1_AD15N_35 |OUTPUT |LVCMOS18* |35 |12 |SLOW | | | |UNLOCATED |NO |NONE | |B3 | |IOB33M |IO_L10P_T1_AD15P_35 |UNUSED | |35 | | | | | | | | | |B4 | |IOB33S |IO_L7N_T1_AD6N_35 |UNUSED | |35 | | | | | | | | | |B5 | | |GND | | | | | | | | | | | | |B6 |I_cmd_code<1> |IOB |IO_L2N_T0_AD12N_35 |INPUT |LVCMOS18* |35 | | | |NONE | |UNLOCATED |NO |NONE | |B7 |I_cmd_code<3> |IOB |IO_L2P_T0_AD12P_35 |INPUT |LVCMOS18* |35 | | | |NONE | |UNLOCATED |NO |NONE | |B8 | |IOB33M |IO_L12P_T1_MRCC_16 |UNUSED | |16 | | | | | | | | | |B9 | |IOB33S |IO_L11N_T1_SRCC_16 |UNUSED | |16 | | | | | | | | | |B10 | | |VCCO_16 | | |16 | | | | |any******| | | | |B11 |I_qspi_addr<7> |IOB |IO_L4P_T0_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |B12 |I_qspi_addr<6> |IOB |IO_L3N_T0_DQS_AD1N_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |B13 |I_qspi_addr<3> |IOB |IO_L2P_T0_AD8P_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |B14 |I_qspi_addr<4> |IOB |IO_L2N_T0_AD8N_15 |INPUT |LVCMOS18* |15 | | | |NONE | |UNLOCATED |NO |NONE | |B15 | | |GND | | | | | | | |