QMC5883L_compass_STM8L.rar

#include "eeprom.h" unsigned char retry,ret_ep[4],*i2c_rx, *i2c_rx_raw, c=0; char Grg_EEPROM_write(unsigned char slave_addr, unsigned char mem_addr, unsigned char data) { retry=3; start: if(!Grg_i2c_bus_status()) { //Grg_usart_tx_string(3,"\nI2C bus is free\n"); if(Grg_i2c_addr(slave_addr,WRITE)) //EEPROM IC adderss { //Grg_usart_tx_string(3,"\nI2C device addr write success\n"); if(Grg_i2c_write(mem_addr)) //page adderss { //Grg_usart_tx_string(3,"\nI2C page addr write success\n"); if(Grg_i2c_write(data)) //data { //Grg_usart_tx_string(3,"\nI2C data write success\n"); if(Grg_i2c_stop()) { //Grg_usart_tx_string(3,"\nI2C stop success\n"); ret_ep[0] = 0; } else{ //Grg_usart_tx_string(3,"\nI2C stop fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=4;} } else{ //Grg_usart_tx_string(3,"\nI2C data write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=3;} } else{ //Grg_usart_tx_string(3,"\nI2C page addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=3;} } else{ //Grg_usart_tx_string(3,"\nI2C device addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=2;} } else{ //Grg_usart_tx_string(3,"\nI2C bus is busy\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=1; } return ret_ep[0]; } char *Grg_EEPROM_read_single(unsigned char slave_addr, unsigned char mem_addr) { retry=3; start: if(!Grg_i2c_bus_status()) { for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C bus is free\n"); if(Grg_i2c_addr(slave_addr,WRITE)) //EEPROM IC adderss and write option { for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C device addr write success\n"); if(Grg_i2c_write(mem_addr)) //page adderss { for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C page addr write success\n"); if(Grg_i2c_addr(slave_addr,READ)) //EEPROM IC adderss and read option { for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C device addr write success\n"); i2c_rx=Grg_i2c_read(); if(i2c_rx[0]) { for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C read success\n"); ret_ep[1]=i2c_rx[1]; Grg_i2c_acknowledge(DISABLE); I2C1_SR3; // Clear ADDR Flag if(Grg_i2c_stop()) //stop communication { for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C stop success\n"); ret_ep[0]=0; } else{ for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C stop fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=4;} } else{ for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C read fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=3;} } else{ for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C device addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=2;} } else{ for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C page addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=3;} } else{ for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C page addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=2;} } else{ for(c=0;c<10;c++); //Grg_usart_tx_string(3,"\nI2C bus is busy\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=1;} return ret_ep; } char *Grg_EEPROM_read(unsigned char slave_addr, unsigned char mem_addr, unsigned char byte_count) { retry=3; start: if(!Grg_i2c_bus_status()) { //Grg_usart_tx_string(3,"\nI2C bus is free\n"); if(Grg_i2c_addr(slave_addr,WRITE)) //EEPROM IC adderss and write option { //Grg_usart_tx_string(3,"\nI2C device addr write success\n"); if(Grg_i2c_write(mem_addr)) //page adderss { //Grg_usart_tx_string(3,"\nI2C page addr write success\n"); if(Grg_i2c_addr(slave_addr,READ)) //EEPROM IC adderss and read option { //Grg_usart_tx_string(3,"\nI2C device addr write success\n"); for(c=0;c<byte_count;c++) { i2c_rx_raw = Grg_i2c_read(); i2c_rx[c+1] = i2c_rx_raw[1]; // use i2c_rx[0] for error checking purpose Grg_i2c_ack(); //Grg_i2c_acknowledge(DISABLE); } if(i2c_rx_raw[0]) { //Grg_usart_tx_string(3,"\nI2C read success\n"); ret_ep[1]=i2c_rx[1]; ret_ep[2]=i2c_rx[2]; ret_ep[3]=i2c_rx[3]; //Grg_i2c_acknowledge(DISABLE); I2C1_SR3; // Clear ADDR Flag if(Grg_i2c_stop()) //stop communication { //Grg_usart_tx_string(3,"\nI2C stop success\n"); ret_ep[0]=0; } else{ //Grg_usart_tx_string(3,"\nI2C stop fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=4;} } else{ //Grg_usart_tx_string(3,"\nI2C read fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=3;} } else{ //Grg_usart_tx_string(3,"\nI2C device addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=2;} } else{ //Grg_usart_tx_string(3,"\nI2C page addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=3;} } else{ //Grg_usart_tx_string(3,"\nI2C page addr write fail\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=2;} } else{ //Grg_usart_tx_string(3,"\nI2C bus is busy\n"); if(Grg_i2c_error()){goto start;} ret_ep[0]=1;} return ret_ep; } char Grg_i2c_error() { if(retry) { retry--; Grg_i2c(DISABLE); if(I2C1_SR2 & 0x80) { //Grg_usart_tx_string(3,"\n SMBAlert event occurred on pin\n"); I2C1_SR2 &=0x7F; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x40) { //Grg_usart_tx_string(3,"\nTimeout or Tlow error\n"); I2C1_SR2 &=0xBF; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x20) { //Grg_usart_tx_string(3,"\n7-bit address or header match in Halt mode\n"); I2C1_SR2 &=0xDF; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x10) { //Grg_usart_tx_string(3,"\nPEC error\n"); I2C1_SR2 &=0xEF; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x08) { //Grg_usart_tx_string(3,"\nOverrun or underrun\n"); I2C1_SR2 &=0xF7; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x04) { //Grg_usart_tx_string(3,"\nAcknowledge failure\n"); I2C1_SR2 &=0xFB; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x02) { //Grg_usart_tx_string(3,"\nArbitration lost detect\n"); I2C1_SR2 &=0xFD; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR2 & 0x01) { //Grg_usart_tx_string(3,"\nMisplaced Start or Stop\n"); I2C1_SR2 &= 0xFE; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } else if(I2C1_SR3 & 0x02) { //Grg_usart_tx_string(3,"\nbus busy\n"); I2C1_SR2 &= 0xFE; Grg_i2c_stop(); Grg_i2c_software_reset(ENABLE); } Grg_i2c(ENABLE); } return retry; }