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ac701 fpga开发板的vip代码用于板子测试
************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ � Copyright 2018�2019 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 1.1 Date Last Modified: 28JUNE2019 Date Created: 04APR2018 Associated Filename: XILINX_VIP_2019_1.zip Associated Documents: PG267, PG277, PG291, and PG298 Supported Device(s): UltraScale+, UltraScale, Zynq-7000 AP SoC, 7 series FPGAs ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. OTHER INFORMATION (OPTIONAL) 7. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 28JUNE2019 1.1 Updated for 2019.1 release. - Improved API definitions for clarity. - New pre_load_mem API added to xil_axi_slv_mem_model class in 2019.1 04APR2018 1.0 Initial Xilinx release. ========================================================================= 2. OVERVIEW This readme describes how to use the Verification IP API files that come with PG267, PG277, PG291, and PG298. It has four Xilinx VIPs which are AXI VIP, AXI4-STREAM VIP, CLOCK VIP and RESET VIP. User should follow below list for usage of APIs: * For usage of AXI VIP, refer file axi_vip_pkg.sv, axi_vip_if.sv * For usage of AXI4STREAM VIP, refer file axi4stream_vip_pkg.sv, axi4stream_vip_if.sv * For usage of CLK VIP, refer file clk_vip_if.sv * For usage of RST VIP, refer file rst_vip_if.sv 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * Xilinx VIVADO 2019.1 or higher 4. DESIGN FILE HIERARCHY * AXI VIP axi_vip_pkg.sv axi_vip_if.sv * AXI4STREAM VIP axi4stream_vip_pkg.sv axi4stream_vip_if.sv * RST VIP rst_vip_if.sv * CLK VIP clk_vip_if.sv 5. INSTALLATION AND OPERATING INSTRUCTIONS * Install the Xilinx Vivado 2019.1 or later tools. 6. OTHER INFORMATION (OPTIONAL) *To view the API docs, go to Documentation/index.html 7. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database.