ug975-vivado-quick-reference.rar

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xilinx doc vivado quit reference
ug975-vivado-quick-reference.rar
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/624f05a36caf596192b823d9/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/624f05a36caf596192b823d9/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> <span class="_ _0"> </span><span class="ff2">Vivado Design Suite Quick Reference <span class="_ _1"> </span>Vivado Design Suite Quick Reference <span class="_ _1"> </span>Vivado Design Suite Quick Reference</span> </div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">UG975 (v201<span class="ls1">6.</span>4<span class="ls2">) </span>No<span class="_ _2"></span>vember <span class="ls1">30</span>, 2016<span class="_ _2"></span> </div><div class="c x2 y3 w2 h4"><div class="t m0 x3 h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Getting Help </div></div><div class="c x2 y5 w3 h6"><div class="t m0 x4 h7 y6 ff3 fs2 fc0 sc0 ls0 ws0">For the most up-<span class="ls3">to</span>-date infor<span class="_ _3"></span>mation on ever<span class="_ _3"></span>y command avail<span class="_ _3"></span>able in the Vi<span class="_ _3"></span>vado<span class="_ _3"></span>&#174; Design Suite </div><div class="t m0 x4 h8 y7 ff3 fs2 fc0 sc0 ls0 ws0">use the built-in hel<span class="_ _3"></span>p system. At th<span class="_ _3"></span>e Tcl prompt ty<span class="_ _3"></span>pe: <span class="ff4 ls4">help</span><span class="ff5"> </span></div></div><div class="c x2 y8 w2 h9"><div class="t m0 x4 h7 y9 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 ya ff3 fs2 fc0 sc0 ls0 ws0">This will list all the c<span class="_ _3"></span>ategories of com<span class="_ _3"></span>mands availabl<span class="_ _3"></span>e in the Vivado<span class="_ _3"></span> tool. You can the<span class="_ _3"></span>n query </div><div class="t m0 x4 h7 yb ff3 fs2 fc0 sc0 ls0 ws0">the specific catego<span class="_ _3"></span>ry of interest <span class="_ _3"></span>for a list of the co<span class="_ _3"></span>mmands in th<span class="_ _3"></span>at category. For<span class="_ _3"></span> example, to </div><div class="t m0 x4 h7 yc ff3 fs2 fc0 sc0 ls0 ws0">see the list of XDC c<span class="_ _3"></span>ommands you w<span class="_ _3"></span>ould type:<span class="ff4"> <span class="ls4">help </span>-<span class="_ _3"></span><span class="ls4">category XDC</span></span> </div><div class="t m0 x4 h7 yd ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 ha ye ff3 fs2 fc0 sc0 ls0 ws0">See the <span class="ff6">Vivado De<span class="_ _3"></span>sign Suite Tcl Co<span class="_ _3"></span>mmand Refe<span class="_ _3"></span>rence Guide</span> <span class="_ _3"></span>(<span class="fc2">UG835)</span> for <span class="_ _3"></span>more informati<span class="_ _3"></span>on. </div><div class="t m0 x4 h8 yf ff3 fs2 fc0 sc0 ls0 ws0">For Vivado tools vid<span class="_ _3"></span>eo tutorials refe<span class="_ _3"></span>r to: <span class="fc2">htt<span class="_ _3"></span>p://www.xilinx.co<span class="_ _3"></span>m/training/viva<span class="_ _3"></span>do/index.htm<span class="_ _3"></span></span><span class="ff5"> </span></div></div><div class="c x2 y10 w2 hb"><div class="t m0 x4 h8 y11 ff5 fs2 fc0 sc0 ls0 ws0"> </div></div><div class="t m0 x1 h7 y12 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="c x2 y13 w4 hc"><div class="t m0 x5 h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Simulation Commands </div></div><div class="c x2 y14 w5 hd"><div class="t m0 x4 h7 y15 ff3 fs2 fc0 sc0 ls0 ws0">The Vivado simulato<span class="_ _3"></span>r is an ev<span class="_ _3"></span>ent-driven Hardw<span class="_ _3"></span>are Description<span class="_ _3"></span> Language (HD<span class="_ _3"></span>L) simulator <span class="_ _3"></span>for </div><div class="t m0 x4 h7 y16 ff3 fs2 fc0 sc0 ls0 ws0">behavioral, functio<span class="_ _3"></span>nal, and timin<span class="_ _3"></span>g simulations <span class="ls5">of</span> VHDL, Ve<span class="_ _3"></span>rilog, SystemV<span class="_ _3"></span>erilog, and <span class="_ _3"></span>mixed-</div><div class="t m0 x4 h7 y17 ff3 fs2 fc0 sc0 ls0 ws0">language designs.<span class="_ _3"></span> </div></div><div class="c x2 y18 w4 he"><div class="t m0 x4 h7 y19 ff3 fs2 fc0 sc0 ls0 ws0"> </div></div><div class="c x1 y1a w6 hf"><div class="t m0 x6 h10 y1b ff7 fs1 fc0 sc0 ls0 ws0">Command </div></div><div class="c x7 y1a w7 hf"><div class="t m0 x8 h10 y1b ff7 fs1 fc0 sc0 ls0 ws0">Purpose </div></div><div class="c x9 y1a w8 hf"><div class="t m0 x1 h10 y1b ff7 fs1 fc0 sc0 ls0 ws0">Example </div></div><div class="c xa y1a w9 hf"><div class="t m0 xb h10 y1b ff7 fs1 fc0 sc0 ls0 ws0">Output </div></div><div class="c x1 y1c w6 h11"><div class="t m0 xc h12 y1d ff7 fs2 fc0 sc0 ls0 ws0">xvlog </div><div class="t m0 xc h12 y1e ff7 fs2 fc0 sc0 ls0 ws0">xvhdl </div></div><div class="c x7 y1c w7 h11"><div class="t m0 x4 h7 y1d ff3 fs2 fc0 sc0 ls0 ws0">Compile Verilog </div><div class="t m0 x4 h7 y1f ff3 fs2 fc0 sc0 ls0 ws0">and VHDL files<span class="_ _3"></span> </div></div><div class="c x9 y1c wa h13"><div class="t m0 x4 h7 y1d ff3 fs2 fc0 sc0 ls0 ws0">xvlog file1.v file2.v<span class="_ _3"></span> </div></div><div class="c x9 y1c wb h14"><div class="t m0 x4 h7 y1f ff3 fs2 fc0 sc0 ls0 ws0">xvhdl f1.vhd f2.vhd<span class="_ _3"></span> </div></div><div class="c xa y1c w9 h11"><div class="t m0 x4 h7 y1d ff3 fs2 fc0 sc0 ls0 ws0">Parsed dump into <span class="_ _3"></span>HDL </div><div class="t m0 x4 h7 y1f ff3 fs2 fc0 sc0 ls0 ws0">library on disk.<span class="_ _3"></span> </div></div><div class="c x1 y20 w6 h15"><div class="t m0 xc h12 y21 ff7 fs2 fc0 sc0 ls0 ws0">xelab </div></div><div class="c x7 y20 w7 h15"><div class="t m0 x4 h7 y22 ff3 fs2 fc0 sc0 ls0 ws0">Compile and </div><div class="t m0 x4 h7 y23 ff3 fs2 fc0 sc0 ls0 ws0">Elaborate </div></div><div class="c x9 y20 w8 h15"><div class="t m0 x4 h7 y22 ff3 fs2 fc0 sc0 ls0 ws0">xelab work.top1 wo<span class="_ _3"></span>rk.top2 </div><div class="t m0 x4 h7 y23 ff3 fs2 fc0 sc0 ls0 ws0">-s cpusim </div></div><div class="c xa y20 w9 h15"><div class="t m0 x4 h7 y24 ff3 fs2 fc0 sc0 ls0 ws0">Creates a snapsh<span class="_ _3"></span>ot. </div></div><div class="c x1 y25 w6 h16"><div class="t m0 xd h12 y26 ff7 fs2 fc0 sc0 ls0 ws0">xsim </div></div><div class="c x7 y25 w7 h16"><div class="t m0 x4 h7 y27 ff3 fs2 fc0 sc0 ls0 ws0">Run simulation </div><div class="t m0 x4 h7 y28 ff3 fs2 fc0 sc0 ls0 ws0">on the </div><div class="t m0 x4 h7 y29 ff3 fs2 fc0 sc0 ls0 ws0">executable </div><div class="t m0 x4 h7 y2a ff3 fs2 fc0 sc0 ls0 ws0">snapshot </div></div><div class="c x9 y25 w8 h16"><div class="t m0 x4 ha y27 ff3 fs2 fc0 sc0 ls0 ws0">xsim <span class="ff6">&lt;options&gt; &lt;ex<span class="_ _3"></span>e&gt;</span> </div></div><div class="c xa y25 w9 h16"><div class="t m0 x4 h7 y2b ff3 fs2 fc0 sc0 ls0 ws0">The xsim command </div><div class="t m0 x4 h7 y2c ff3 fs2 fc0 sc0 ls0 ws0">loads a simulation </div><div class="t m0 x4 h7 y2d ff3 fs2 fc0 sc0 ls0 ws0">snapshot to perfor<span class="_ _3"></span>m <span class="ls5">a </span></div><div class="t m0 x4 h7 y2e ff3 fs2 fc0 sc0 ls0 ws0">batch mode </div><div class="t m0 x4 h7 y2f ff3 fs2 fc0 sc0 ls0 ws0">simulation, or run<span class="_ _3"></span> </div><div class="t m0 x4 h7 y30 ff3 fs2 fc0 sc0 ls0 ws0">simulation interactiv<span class="_ _3"></span>ely </div><div class="t m0 x4 h7 y31 ff3 fs2 fc0 sc0 ls0 ws0">in a GUI and/or a Tcl<span class="_ _3"></span>-</div><div class="t m0 x4 h7 y32 ff3 fs2 fc0 sc0 ls0 ws0">based environment.<span class="_ _3"></span> </div></div><div class="c x2 y18 w4 he"><div class="t m0 x4 h7 y33 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 y34 ff3 fs2 fc0 sc0 ls0 ws0">To create a simulatio<span class="_ _3"></span>n script fr<span class="_ _3"></span>om Vivado IDE<span class="_ _3"></span>: <span class="ff4 ls4">launch_simulation<span class="ls0"> <span class="ff8">&#8211;</span>script<span class="_ _3"></span>s_only <span class="_ _3"></span></span></span> </div><div class="t m0 x4 ha y35 ff3 fs2 fc0 sc0 ls0 ws0">For details, see t<span class="_ _3"></span>he <span class="ff6">Vivado Design<span class="_ _3"></span> Suite User Guid<span class="_ _3"></span>e: Logic Si<span class="_ _3"></span>mulation </span><span class="fc2">(<span class="ls6">UG<span class="_ _3"></span></span>900</span>)<span class="fc3"> </span></div></div><div class="c x2 y36 w4 hb"><div class="t m0 x4 h17 y11 ff3 fs1 fc1 sc0 ls0 ws0"> </div></div><div class="t m0 x1 h7 y37 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="c x2 y38 w2 hc"><div class="t m0 xe h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Vivado Hardware Manager </div></div><div class="c x2 y39 w3 h18"><div class="t m0 x4 h7 y3a ff3 fs2 fc0 sc0 ls0 ws0">The Hardware Man<span class="_ _3"></span>ager lets you i<span class="_ _3"></span>nteract with de<span class="_ _3"></span>bug cores that <span class="_ _3"></span>are implement<span class="_ _3"></span>ed on Xilinx </div><div class="t m0 x4 h7 y3b ff3 fs2 fc0 sc0 ls0 ws0">FPGA devices. Tcl c<span class="_ _3"></span>ommands us<span class="_ _3"></span>ed to access fe<span class="_ _3"></span>atures of the Ha<span class="_ _3"></span>rdware Mana<span class="_ _3"></span>ger include<span class="_ _3"></span>: </div></div><div class="c x2 y39 w2 h18"><div class="t m0 x4 h12 y3c ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">open_hw</span> - Open<span class="_ _3"></span>s the Hardware <span class="_ _3"></span>Manager in the Viv<span class="_ _3"></span>ado Desig<span class="_ _3"></span>n Suite.<span class="_ _3"></span> </span></div><div class="t m0 x4 h12 y3d ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">connect_hw_ser<span class="_ _3"></span>ver</span> - Makes a c<span class="_ _3"></span>onnection to <span class="_ _3"></span>a local or remot<span class="_ _3"></span>e hardware s<span class="_ _3"></span>erver </span></div><div class="t m0 xf h7 y3e ff3 fs2 fc0 sc0 ls0 ws0">application. </div><div class="t m0 x4 h12 y3f ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">open_hw_target<span class="_ _3"></span></span> - Opens a c<span class="_ _3"></span>onnection to the <span class="_ _3"></span>hardware target.<span class="_ _3"></span> </span></div><div class="t m0 x4 h12 y40 ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">current_hw_device<span class="_ _3"></span></span> <span class="ffa">&#8211;</span> Sets or <span class="_ _3"></span>returns the Xilinx FP<span class="_ _3"></span>GA device to <span class="_ _3"></span>program and deb<span class="_ _3"></span>ug. </span></div><div class="t m0 x4 h12 y41 ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">get_hw_ilas</span> <span class="ffa">&#8211;</span> Ge<span class="_ _3"></span>t the Integrate<span class="_ _3"></span>d Logic Analyzer de<span class="_ _3"></span>bug core objects <span class="_ _3"></span>that are u<span class="_ _3"></span>sed to </span></div><div class="t m0 xf h7 y42 ff3 fs2 fc0 sc0 ls0 ws0">monitor signals in t<span class="_ _3"></span>he design, trigg<span class="_ _3"></span>er on hardware<span class="_ _3"></span> events, and cap<span class="_ _3"></span>ture system <span class="_ _3"></span>data in </div><div class="t m0 xf h7 y43 ff3 fs2 fc0 sc0 ls7 ws0">real<span class="ls0">-time. U<span class="_ _3"></span>se any of the<span class="_ _3"></span> <span class="ff4 ls4">*_hw_ila*</span> TCL co<span class="_ _3"></span>mmands to inte<span class="_ _3"></span>ract with the I<span class="_ _3"></span>LA core. <span class="_ _3"></span> </span></div><div class="t m0 x4 h12 y44 ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">get_hw_vios</span> - <span class="ls3">Ge</span>t the Virtual I<span class="_ _3"></span>/O debug co<span class="_ _3"></span>re objects that a<span class="_ _3"></span>re used to drive<span class="_ _3"></span> control </span></div><div class="t m0 xf h7 y45 ff3 fs2 fc0 sc0 ls0 ws0">signals and/or mo<span class="_ _3"></span>nitor design stat<span class="_ _3"></span>us signals. <span class="_ _3"></span> </div><div class="t m0 x4 h12 y46 ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">get_hw_axis</span> - G<span class="_ _3"></span>et the AXI debug c<span class="_ _3"></span>ore objects that <span class="_ _3"></span>are used t<span class="_ _3"></span>o generate AXI </span></div><div class="t m0 xf h7 y47 ff3 fs2 fc0 sc0 ls0 ws0">transactions to int<span class="_ _3"></span>eract with various AXI<span class="_ _3"></span> full and AXI lite<span class="_ _3"></span> slave c<span class="_ _3"></span>ores in a syste<span class="_ _3"></span>m running </div><div class="t m0 xf h7 y48 ff3 fs2 fc0 sc0 ls0 ws0">on Xilinx FPGA devices<span class="_ _3"></span>. </div><div class="t m0 x4 h12 y49 ff9 fs2 fc0 sc0 ls0 ws0">&#61623;<span class="ff3"> <span class="_ _4"> </span><span class="ff7">get_hw_sio_iber<span class="_ _3"></span>ts</span> - Get the S<span class="_ _3"></span>IO debug cores <span class="_ _3"></span>that are us<span class="_ _3"></span>ed to measure <span class="_ _3"></span>and optimize </span></div><div class="t m0 xf h7 y4a ff3 fs2 fc0 sc0 ls0 ws0">high-speed serial <span class="_ _3"></span>I/O transmit/rec<span class="_ _3"></span>eive settings, and m<span class="_ _3"></span>easure t<span class="_ _3"></span>ransmission bit <span class="_ _3"></span>error rates.<span class="_ _3"></span> </div><div class="t m0 x4 ha y4b ff3 fs2 fc0 sc0 ls0 ws0">For more information<span class="_ _3"></span>, see t<span class="ls8">he </span><span class="ff6">V<span class="_ _3"></span>ivado D<span class="_ _3"></span>esign Suite User <span class="_ _3"></span>Guide: Programmi<span class="_ _3"></span>ng and De<span class="_ _3"></span>bugging </span></div><div class="t m0 x4 ha y4c ff3 fs2 fc2 sc0 ls0 ws0">(UG908<span class="fc0">). <span class="ff6"> </span></span></div></div><div class="c x2 y4d w2 h19"><div class="t m0 x4 h17 y4e ff3 fs1 fc1 sc0 ls0 ws0"> </div></div><div class="c x10 y3 wc h4"><div class="t m0 x11 h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Vivado IDE Launch Modes </div></div><div class="c x10 y4f wc h1a"><div class="t m0 x4 h17 y50 ff3 fs1 fc0 sc0 ls0 ws0"> </div></div><div class="c x10 y4f wd h1a"><div class="t m0 x4 h17 y51 ff3 fs1 fc0 sc0 ls0 ws0">When launching Vi<span class="_ _2"></span>vado from the<span class="_ _2"></span> command l<span class="_ _2"></span>ine there are thre<span class="_ _2"></span>e modes: </div><div class="t m0 x4 h17 y52 ff3 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h10 y53 ff7 fs1 fc0 sc0 ls0 ws0">1. GUI Mode<span class="ff3"> <span class="ffa">&#8211;</span> The<span class="_ _2"></span> default mode<span class="_ _2"></span>. Launche<span class="_ _2"></span>s the Vivado <span class="_ _2"></span>IDE. </span></div><div class="t m0 x4 h1b y54 ff3 fs1 fc0 sc0 ls0 ws0"> <span class="ff6">Usage:</span> <span class="ff4 ls9">vivado </span>OR <span class="ff4 ls9">vivado<span class="_ _2"></span><span class="ls0"> -<span class="ls9">mode gui </span> </span></span></div><div class="t m0 x4 h17 y55 ff3 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h10 y56 ff7 fs1 fc0 sc0 ls0 ws0">2. Tcl Shell Mode<span class="_ _2"></span><span class="ff3"> - Launches<span class="_ _2"></span> the Vivado De<span class="_ _2"></span>sign Suite<span class="_ _2"></span> Tcl shell. </span></div><div class="t m0 x4 h1b y57 ff3 fs1 fc0 sc0 ls0 ws0"> <span class="ff6">Usage:</span><span class="lsa"> <span class="ff4 ls9">vivado <span class="ls0">-</span>mode tcl</span></span> <span class="_ _2"></span><span class="ff4"> </span></div><div class="t m0 x4 h1b y58 ff6 fs1 fc0 sc0 ls0 ws0"> Note:<span class="ff3"> U<span class="lsb">se</span> <span class="ff4 ls9">start<span class="ls0">_</span>gui<span class="_ _2"></span><span class="ff3 ls0"> <span class="lsc">and </span><span class="ff4">stop_<span class="ls9">gui</span></span> Tcl com<span class="_ _2"></span>mands to open a<span class="_ _2"></span>nd close the <span class="_ _2"></span> </span></span></span></div><div class="t m0 x4 h17 y59 ff3 fs1 fc0 sc0 ls0 ws0"> Vivado IDE fro<span class="_ _2"></span>m the Tcl she<span class="_ _2"></span>ll. </div><div class="t m0 x4 h17 y5a ff3 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h10 y5b ff7 fs1 fc0 sc0 ls0 ws0">3. Batch Mode<span class="ff3"> - Lau<span class="_ _2"></span>nches the <span class="_ _2"></span>Tcl shell, run<span class="_ _2"></span>s a Tcl script,<span class="_ _2"></span> and then exits the <span class="_ _2"></span>tool. </span></div><div class="t m0 x4 h1b y5c ff3 fs1 fc0 sc0 ls0 ws0"> <span class="ff6">Usage:</span><span class="lsa"> <span class="ff4 ls9">vivado <span class="ls0">-</span>mode batc<span class="_ _2"></span>h <span class="ff8 ls0">&#8211;</span>source <span class="ffb">&lt;file.tcl&gt;<span class="ff6 ls0"> <span class="ffc"> </span></span></span></span></span></div><div class="t m0 x4 h17 y5d ff3 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h10 y5e ff7 fs1 fc0 sc0 ls0 ws0">Vivado Comma<span class="_ _2"></span>nd Options: </div></div><div class="c x12 y5f we hb"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-mode </div></div><div class="c x13 y5f wf hb"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Invocation mode:<span class="_ _2"></span> gui, tcl, <span class="lsc">or</span> batch<span class="_ _2"></span>. Default: gui </div></div><div class="c x12 y60 we h1c"><div class="t m0 x4 h17 y32 ff3 fs1 fc0 sc0 ls0 ws0">-init </div></div><div class="c x13 y60 wf h1c"><div class="t m0 x4 h17 y32 ff3 fs1 fc0 sc0 ls0 ws0">Source vivado.<span class="_ _2"></span>tcl file during in<span class="_ _2"></span>itialization<span class="_ _2"></span>. </div></div><div class="c x12 y61 we h1d"><div class="t m0 x4 h17 y62 ff3 fs1 fc0 sc0 ls0 ws0">-source </div></div><div class="c x13 y61 wf h1d"><div class="t m0 x4 h17 y62 ff3 fs1 fc0 sc0 ls0 ws0">Source the speci<span class="_ _2"></span>fied Tcl file.<span class="_ _2"></span> Required for bat<span class="_ _2"></span>ch mode. </div></div><div class="c x12 y63 we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-nojourna<span class="_ _2"></span>l </div></div><div class="c x13 y63 wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Do not write a jour<span class="_ _2"></span>nal file. </div></div><div class="c x12 y64 we h1c"><div class="t m0 x4 h17 y65 ff3 fs1 fc0 sc0 ls0 ws0">-appjourn<span class="_ _2"></span>al </div></div><div class="c x13 y64 wf h1c"><div class="t m0 x4 h17 y65 ff3 fs1 fc0 sc0 ls0 ws0">Append to the <span class="_ _2"></span>journal file in<span class="_ _2"></span>stead of overwriting i<span class="_ _2"></span>t. </div></div><div class="c x12 y66 we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-journal </div></div><div class="c x13 y66 wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Journal file name<span class="_ _2"></span><span class="lsa">. <span class="ls0">The defaul<span class="_ _2"></span>t <span class="lsd">is</span> vivado.jou. </span></span></div></div><div class="c x12 y67 we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-nolog </div></div><div class="c x13 y67 wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Do not write a log<span class="_ _2"></span> file. </div></div><div class="c x12 y68 we h1c"><div class="t m0 x4 h17 y65 ff3 fs1 fc0 sc0 ls0 ws0">-<span class="lsc">applog</span> </div></div><div class="c x13 y68 wf h1c"><div class="t m0 x4 h17 y65 ff3 fs1 fc0 sc0 ls0 ws0">Append to the <span class="_ _2"></span>log file instead<span class="_ _2"></span> of overw<span class="_ _2"></span>riting it. </div></div><div class="c x12 y69 we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-log </div></div><div class="c x13 y69 wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Log file name. The<span class="_ _2"></span> default is <span class="_ _2"></span>vivado.log. </div></div><div class="c x12 y6a we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-version </div></div><div class="c x13 y6a wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Output version in<span class="_ _2"></span>formation an<span class="_ _2"></span>d exit </div></div><div class="c x12 y6b we h1c"><div class="t m0 x4 h17 y65 ff3 fs1 fc0 sc0 ls0 ws0">-tclargs </div></div><div class="c x13 y6b wf h1c"><div class="t m0 x4 h17 y65 ff3 fs1 fc0 sc0 ls0 ws0">Arguments pa<span class="_ _2"></span>ssed on to T<span class="_ _2"></span>cl argc arg<span class="_ _2"></span>v </div></div><div class="c x12 y6c we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-tempDir </div></div><div class="c x13 y6c wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Temporary dire<span class="_ _2"></span>ctory name </div></div><div class="c x12 y6d we h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">-verbose </div></div><div class="c x13 y6d wf h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">Suspend message<span class="_ _2"></span> limits during<span class="_ _2"></span> command e<span class="_ _2"></span>xecution </div></div><div class="c x12 y6e we h1f"><div class="t m0 x4 h1b y6f ff6 fs1 fc0 sc0 ls0 ws0">&lt;project | dcp<span class="ff3">&gt; <span class="_ _2"></span> <span class="fc4 sc0"> </span><span class="fc4 sc0"> </span></span></div></div><div class="c x13 y6e wf h1f"><div class="t m0 x4 h17 y6f ff3 fs1 fc0 sc0 lsc ws0">Load <span class="ls0">the specified proje<span class="_ _2"></span>ct file (.xpr<span class="_ _2"></span>) or Design Che<span class="_ _2"></span>ck Point </span></div><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0">(.dcp). </div></div><div class="c x10 y4f wd h1a"><div class="t m0 x4 h20 y70 ff7 fs3 fc0 sc0 ls0 ws0"> </div></div><div class="c x10 y71 wc h21"><div class="t m0 x4 h17 y72 ff3 fs1 fc0 sc0 ls0 ws0"> </div></div><div class="t m0 x12 h7 y73 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="c x10 y74 wc h22"><div class="t m0 x7 h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Main Reporting Commands </div></div><div class="c x10 y75 wc h23"><div class="t m0 x4 h7 y76 ff3 fs2 fc0 sc0 ls0 ws0">The Vivado Desig<span class="_ _3"></span>n Suite inclu<span class="_ _3"></span>des many repo<span class="_ _3"></span>rting commands w<span class="_ _3"></span>hich provid<span class="_ _3"></span>e different levels o<span class="_ _3"></span>f </div><div class="t m0 x4 h7 y77 ff3 fs2 fc0 sc0 ls0 ws0">information as th<span class="_ _3"></span>e design progresses<span class="_ _3"></span> through the d<span class="_ _3"></span>esign flow:<span class="_ _3"></span> </div></div><div class="c x12 y78 w10 h24"><div class="t m0 xd h10 y79 ff7 fs1 fc0 sc0 ls0 ws0">Category <span class="fs2"> </span></div></div><div class="c x14 y78 w11 h24"><div class="t m0 x15 h10 y79 ff7 fs1 fc0 sc0 ls0 ws0">Purpose <span class="fs2"> </span></div></div><div class="c x16 y78 w12 h24"><div class="t m0 x17 h10 y79 ff7 fs1 fc0 sc0 ls0 ws0">Examples <span class="fs2"> </span></div></div><div class="c x12 y7a w10 h25"><div class="t m0 x4 h7 y7b ff3 fs2 fc0 sc0 ls0 ws0">Timing </div></div><div class="c x14 y7a w11 h25"><div class="t m0 x4 h7 y7b ff3 fs2 fc0 sc0 ls0 ws0">Design goals </div></div><div class="c x16 y7a w13 h26"><div class="t m0 x4 h7 y7c ff3 fs2 fc0 sc0 ls0 ws0">check_timing </div></div><div class="c x16 y7d w14 h27"><div class="t m0 x4 h7 y7e ff3 fs2 fc0 sc0 ls0 ws0">report_timing </div><div class="t m0 x4 h7 y7f ff3 fs2 fc0 sc0 ls0 ws0">report_clocks<span class="_ _3"></span> </div><div class="t m0 x4 h7 y80 ff3 fs2 fc0 sc0 ls0 ws0">report_clock_inte<span class="_ _3"></span>raction </div><div class="t m0 x4 h7 y81 ff3 fs2 fc0 sc0 ls0 ws0">report_cdc </div><div class="t m0 x4 h7 y82 ff3 fs2 fc0 sc0 ls0 ws0">report_synchronizer<span class="_ _3"></span>_mtbf </div></div><div class="c x12 y83 w10 h28"><div class="t m0 x4 h7 y84 ff3 fs2 fc0 sc0 ls0 ws0">Performance </div></div><div class="c x14 y83 w11 h28"><div class="t m0 x4 h7 y84 ff3 fs2 fc0 sc0 ls0 ws0">Measurement agai<span class="_ _3"></span>nst design goal<span class="_ _3"></span>s </div></div><div class="c x16 y83 w13 h29"><div class="t m0 x4 h7 y2e ff3 fs2 fc0 sc0 ls0 ws0">report_timing_sum<span class="_ _3"></span>mary </div></div><div class="c x16 y83 w14 h29"><div class="t m0 x4 h7 y2f ff3 fs2 fc0 sc0 ls0 ws0">report_datasheet<span class="_ _3"></span> </div><div class="t m0 x4 h7 y84 ff3 fs2 fc0 sc0 ls0 ws0">report_design_anal<span class="_ _3"></span>ysis </div><div class="t m0 x4 h7 y85 ff3 fs2 fc0 sc0 ls0 ws0">report_power<span class="_ _3"></span> </div><div class="t m0 x4 h7 y62 ff3 fs2 fc0 sc0 ls0 ws0">report_pulse_width<span class="_ _3"></span> </div></div><div class="c x12 y86 w10 h2a"><div class="t m0 x4 h7 y87 ff3 fs2 fc0 sc0 ls0 ws0">Resource Utilizatio<span class="_ _3"></span>n </div></div><div class="c x14 y86 w11 h2a"><div class="t m0 x4 h7 y87 ff3 fs2 fc0 sc0 ls0 ws0">Logical to physic<span class="_ _3"></span>al resource mappin<span class="_ _3"></span>g </div></div><div class="c x16 y86 w13 h2a"><div class="t m0 x4 h7 y88 ff3 fs2 fc0 sc0 ls0 ws0">report_utilization<span class="_ _3"></span> </div></div><div class="c x16 y86 w14 h2b"><div class="t m0 x4 h7 y89 ff3 fs2 fc0 sc0 ls0 ws0">report_clock_util<span class="_ _3"></span> </div><div class="t m0 x4 h7 y87 ff3 fs2 fc0 sc0 ls0 ws0">report_io </div><div class="t m0 x4 h7 y8a ff3 fs2 fc0 sc0 ls0 ws0">report_control_sets<span class="_ _3"></span> </div><div class="t m0 x4 h7 y8b ff3 fs2 fc0 sc0 ls0 ws0">report_ram_config<span class="_ _3"></span>uration </div></div><div class="c x12 y8c w10 h2c"><div class="t m0 x4 h7 y8d ff3 fs2 fc0 sc0 ls0 ws0">Design Rule Checks<span class="_ _3"></span> </div></div><div class="c x14 y8c w11 h2c"><div class="t m0 x4 h7 y8d ff3 fs2 fc0 sc0 ls0 ws0">Physical verification <span class="_ _3"></span> </div></div><div class="c x16 y8c w13 h2c"><div class="t m0 x4 h7 y8e ff3 fs2 fc0 sc0 ls0 ws0">report_drc </div></div><div class="c x16 y8c w14 h2d"><div class="t m0 x4 h7 y8d ff3 fs2 fc0 sc0 ls0 ws0">report_methodolo<span class="_ _3"></span>gy </div><div class="t m0 x4 h7 y8f ff3 fs2 fc0 sc0 ls0 ws0">report_ssn </div></div><div class="c x12 y90 w10 h2e"><div class="t m0 x4 h7 y91 ff3 fs2 fc0 sc0 ls0 ws0">Design Data </div></div><div class="c x14 y90 w11 h2e"><div class="t m0 x4 h7 y91 ff3 fs2 fc0 sc0 ls0 ws0">Project-specific set<span class="_ _3"></span>tings </div></div><div class="c x16 y90 w13 h2e"><div class="t m0 x4 h7 y92 ff3 fs2 fc0 sc0 ls0 ws0">report_param </div></div><div class="c x16 y90 w14 h2f"><div class="t m0 x4 h7 y91 ff3 fs2 fc0 sc0 ls0 ws0">report_config_ti<span class="_ _3"></span>ming </div><div class="t m0 x4 h7 y93 ff3 fs2 fc0 sc0 ls0 ws0">report_ip_status<span class="_ _3"></span> </div></div><div class="c x10 y75 wd h30"><div class="t m0 x4 h31 y94 ff6 fs3 fc3 sc0 ls0 ws0"> </div></div><div class="c x10 y95 wc h32"><div class="t m0 x4 h17 y96 ff3 fs1 fc0 sc0 ls0 ws0"> </div></div><div class="c x18 y3 w5 h4"><div class="t m0 x19 h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Design Object Query Commands </div></div><div class="c x1a y97 w15 h33"><div class="t m0 x4 h10 y98 ff7 fs1 fc0 sc0 ls0 ws0">Command </div></div><div class="c x1b y97 w16 h33"><div class="t m0 x4 h10 y98 ff7 fs1 fc0 sc0 ls0 ws0">Description </div></div><div class="c x1a y99 w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">get_cells </div></div><div class="c x1b y99 w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Get logic cell obje<span class="_ _3"></span>cts based on na<span class="_ _3"></span>me/hierarchy o<span class="_ _3"></span>r connectivity <span class="_ _3"></span> </div></div><div class="c x1a y9a w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">get_pins </div></div><div class="c x1b y9a w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Get pin objects bas<span class="_ _3"></span>ed name/hiera<span class="_ _3"></span>rchy or con<span class="_ _3"></span>nectivity <span class="_ _3"></span> </div></div><div class="c x1a y9b w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">get_nets </div></div><div class="c x1b y9b w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Get net objects by <span class="_ _3"></span>name/hierarchy<span class="_ _3"></span> or connectivit<span class="_ _3"></span>y </div></div><div class="c x1a y9c w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">get_ports </div></div><div class="c x1b y9c w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Get t<span class="ls8">op</span>-level n<span class="_ _3"></span>etlist ports by <span class="_ _3"></span>name or c<span class="_ _3"></span>onnectivity <span class="_ _3"></span> </div></div><div class="c x1a y9d w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">all_inputs </div></div><div class="c x1b y9d w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Return a<span class="ls6">ll</span> input ports i<span class="_ _3"></span>n the current <span class="_ _3"></span>design </div></div><div class="c x1a y9e w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">all_outputs </div></div><div class="c x1b y9e w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Return a<span class="ls6">ll</span> output po<span class="_ _3"></span>rts in the curren<span class="_ _3"></span>t design <span class="_ _3"></span> </div></div><div class="c x1a y9f w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">all_ffs </div></div><div class="c x1b y9f w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Return a<span class="ls6">ll</span> flip flops in<span class="_ _3"></span> current design <span class="_ _3"></span> </div></div><div class="c x1a ya0 w15 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">all_latches </div></div><div class="c x1b ya0 w16 h34"><div class="t m0 x4 h7 y79 ff3 fs2 fc0 sc0 ls0 ws0">Return a<span class="ls6">ll</span> latches in <span class="_ _3"></span>current design <span class="_ _3"></span> </div></div><div class="c x1a ya1 w15 h35"><div class="t m0 x4 h7 ya2 ff3 fs2 fc0 sc0 ls0 ws0">all_dsps </div></div><div class="c x1b ya1 w16 h35"><div class="t m0 x4 h7 ya2 ff3 fs2 fc0 sc0 ls0 ws0">Return a<span class="ls6">ll</span> DSP cells in <span class="_ _3"></span>the current de<span class="_ _3"></span>sign<span class="_ _3"></span> </div></div><div class="c x1a ya3 w15 h34"><div class="t m0 x4 h7 y1f ff3 fs2 fc0 sc0 ls0 ws0">all_rams </div></div><div class="c x1b ya3 w16 h34"><div class="t m0 x4 h7 y1f ff3 fs2 fc0 sc0 ls0 ws0">Return a<span class="ls6">ll</span> ram cells i<span class="_ _3"></span>n the current desig<span class="_ _3"></span>n </div></div><div class="c x18 ya3 w5 h36"><div class="t m0 x4 h37 ya4 ff3 fs3 fc0 sc0 ls0 ws0"> </div></div><div class="c x18 ya5 w5 h1e"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0"> </div></div><div class="t m0 x1a h7 ya6 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="c x18 ya7 w5 h4"><div class="t m0 x19 h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Timing-based Query Commands </div></div><div class="c x1a ya8 w17 h38"><div class="t m0 x4 h10 ya9 ff7 fs1 fc0 sc0 ls0 ws0">Command </div></div><div class="c x1c ya8 w18 h38"><div class="t m0 x4 h10 ya9 ff7 fs1 fc0 sc0 ls0 ws0">Description <span class="_ _2"></span> </div></div><div class="c x1a yaa w17 h39"><div class="t m0 x4 h7 yab ff3 fs2 fc0 sc0 ls0 ws0">all_clocks </div></div><div class="c x1c yaa w18 h39"><div class="t m0 x4 h7 yab ff3 fs2 fc0 sc0 ls0 ws0">Get a list of all defin<span class="_ _3"></span>ed clocks in the<span class="_ _3"></span> current d<span class="_ _3"></span>esign<span class="_ _3"></span> </div></div><div class="c x1a yac w17 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">get_clocks </div></div><div class="c x1c yac w18 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">Get clock objects by <span class="_ _3"></span>name or obj<span class="_ _3"></span>ect traversed <span class="_ _3"></span> </div></div><div class="c x1a yae w17 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">get_generated_cloc<span class="_ _3"></span>ks </div></div><div class="c x1c yae w18 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">Get generated Cl<span class="_ _3"></span>ock objects </div></div><div class="c x1a yaf w17 h39"><div class="t m0 x4 h7 yab ff3 fs2 fc0 sc0 ls0 ws0">all_fanin </div></div><div class="c x1c yaf w18 h39"><div class="t m0 x4 h7 yab ff3 fs2 fc0 sc0 ls0 ws0">Get list of pins or c<span class="_ _3"></span>ells in fanin <span class="_ _3"></span>of specified object in<span class="_ _3"></span> timing path<span class="_ _3"></span> </div></div><div class="c x1a yb0 w17 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">all_fanout </div></div><div class="c x1c yb0 w18 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">Get list of pins or c<span class="_ _3"></span>ells in fanout of sp<span class="_ _3"></span>ecified object in<span class="_ _3"></span> timing path<span class="_ _3"></span> </div></div><div class="c x1a yb1 w17 h3a"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">all_registers <span class="_ _3"></span> </div></div><div class="c x1c yb1 w18 h3a"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">Get list of all seque<span class="_ _3"></span>ntial / latched c<span class="_ _3"></span>ells in the current<span class="_ _3"></span> design <span class="_ _3"></span> </div></div><div class="c x1a yb2 w17 h3b"><div class="t m0 x4 h7 yab ff3 fs2 fc0 sc0 ls0 ws0">get_path_groups <span class="_ _3"></span> </div></div><div class="c x1c yb2 w18 h3b"><div class="t m0 x4 h7 yab ff3 fs2 fc0 sc0 ls0 ws0">Get a list of path g<span class="_ _3"></span>roup objects <span class="_ _3"></span> </div></div><div class="c x1a yb3 w17 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">get_timing_paths <span class="_ _3"></span> </div></div><div class="c x1c yb3 w18 h38"><div class="t m0 x4 h7 yad ff3 fs2 fc0 sc0 ls0 ws0">Get timing path o<span class="_ _3"></span>bjects, equivalent t<span class="_ _3"></span>o report_timing <span class="_ _3"></span>printout <span class="_ _3"></span> </div></div><div class="c x18 yb3 w5 h3c"><div class="t m0 x4 h37 yb4 ff3 fs3 fc0 sc0 ls0 ws0"> </div></div><div class="c x18 yb5 w5 hb"><div class="t m0 x4 h17 y11 ff3 fs1 fc0 sc0 ls0 ws0"> </div></div><div class="t m0 x1a h7 y78 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="c x18 yb6 w3 hc"><div class="t m0 x1d h5 y4 ff2 fs0 fc1 sc0 ls0 ws0">Filtering </div></div><div class="c x18 yb7 w3 h3d"><div class="t m0 x4 h7 yb8 ff3 fs2 fc0 sc0 ls0 ws0"> </div></div><div class="c x18 yb7 w2 h3e"><div class="t m0 x4 h7 yb9 ff3 fs2 fc0 sc0 ls0 ws0">All get_* comman<span class="_ _3"></span>ds provide a <span class="_ _3"></span>-filter option. <span class="_ _3"></span>There is also an i<span class="_ _3"></span>ndependent filt<span class="_ _3"></span>er command. </div><div class="t m0 x4 h7 yba ff3 fs2 fc0 sc0 ls0 ws0">Filtering provi<span class="_ _3"></span>des a mechanism <span class="_ _3"></span>to reduce lists <span class="_ _3"></span>of returned o<span class="_ _3"></span>bjects based o<span class="_ _3"></span>n the object<span class="_ _3"></span> </div><div class="t m0 x4 h7 ybb ff3 fs2 fc0 sc0 ls0 ws0">properties. For ex<span class="_ _3"></span>ample, to filter o<span class="_ _3"></span>n a LIB_CELL typ<span class="_ _3"></span>e you could d<span class="_ _3"></span>o the followi<span class="_ _3"></span>ng:<span class="_ _3"></span> </div><div class="t m0 x4 h7 ybc ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 ybd ff3 fs2 fc0 sc0 ls0 ws0">&gt; get_cells -hier<span class="_ _3"></span> -filter {LIB_CEL<span class="_ _3"></span>L == FDCE}<span class="_ _3"></span> </div><div class="t m0 x4 h7 ybe ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 ybf ff3 fs2 fc0 sc0 ls0 ws0">You can combine <span class="_ _3"></span>multiple filters<span class="_ _3"></span> together:<span class="_ _3"></span> </div><div class="t m0 x4 h7 yc0 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 yc1 ff3 fs2 fc0 sc0 ls0 ws0">&gt; get_ports -filter<span class="_ _3"></span> {DIRECTION == i<span class="_ _3"></span>n &amp;&amp; NAME =~ *<span class="_ _3"></span>clk*}<span class="ff4"> <span class="_ _3"></span> </span></div><div class="t m0 x4 h3f yc2 ffc fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 yc3 ff3 fs2 fc0 sc0 ls0 ws0">You can filter directly<span class="_ _3"></span> on Boolean p<span class="_ _3"></span>roperties: </div><div class="t m0 x4 h7 yc4 ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 yc5 ff3 fs2 fc0 sc0 ls0 ws0">&gt; get_cells -filter<span class="_ _3"></span> {IS_PRIMITIVE<span class="_ _3"></span> &amp;&amp; !IS_LOC_F<span class="_ _3"></span>IXED}<span class="ff4"> </span></div><div class="t m0 x4 h12 yc6 ff7 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h7 yc7 ff3 fs2 fc0 sc0 ls0 ws0">Valid operations ar<span class="_ _3"></span>e: ==, !=, =~, !~<span class="_ _3"></span>, &lt;=, &gt;=, &gt;, &lt; as w<span class="_ _3"></span>ell as &amp;&amp; and || b<span class="_ _3"></span>etween filter <span class="_ _3"></span>patterns<span class="_ _3"></span> </div><div class="t m0 x4 h12 yc8 ff7 fs2 fc0 sc0 ls0 ws0"> </div></div><div class="c x18 yc9 w3 h19"><div class="t m0 x4 h17 y4e ff3 fs1 fc1 sc0 ls0 ws0"> </div></div><div class="t m0 x1a h40 yca ff5 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1a h40 ycb ff5 fs0 fc0 sc0 ls0 ws0"> <span class="_ _5"> </span> </div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[0.952381,0.000000,0.000000,0.952381,0.000000,0.000000]}'></div></div> </body> </html>
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