AES-VHDL-master.zip

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report aes final year project
AES-VHDL-master.zip
内容介绍
# AES-VHDL VHDL Implementation of AES Algorithm There are simple VHDL implementations of AES-128 encryption, and decryption algorithms, in this repository. This is actually my first experience in VHDL implementation! ## What is AES? There might be few people who deal with computers, and hardwares, but have not heard the name of AES, which is a famous symmetric block cipher. If you have not knew this algorithm yet, [1] is a good reference, to understand how this algorithm works. This implementation is also based on [1]. ## Pipelined VS Loop Unrolled Two famous kinds of hardware implementation techniques, are pipelining, and loop-unrolling techniques. In pipelining, registers are inserted between each combinational processing element, so that each input data block can be processed simultaneously in each processing element. An overview of a pipelined implementation of AES encryption algorithm is depicted in the following shape, where the round-i depicts the i'th round of AES encryption algorithm. ![AES-pipelined-picture](/Images/pipelined_aes.svg) The number of rounds of AES-128 encryption is 10, and an architecture implementing this cipher, is called fully pipelined, when all data blocks of 10 rounds can be processed simultaneously. For a fully pipelined implementation of AES-128, ten 128-bit data registers are needed. The more data block we want to process simultaneously, the more registers, and therefore the more area we need for implementation. In contrast to pipelining, in a loop-unrolling technique, one, or multiple rounds of the algorithm are processed in the same clock cycle. In the smallest case of a loop-unrolled implementation of AES, which is depicted in the following shape, only one round of the algorithm is implemented as a combinational processing element, and a data register is also used to store the result obtained in the previous clock cycle. ![AES-loop-unrolled-picture](/Images/loop_unrolled_aes.svg) Therefore the next plaintext must be entered after 10 clock cycles, while in a fully pipelined architecture, in each clock cycle one new plaintext can be entered to the process of encryption. Although pipelined architecture has more throughput than the loop-unrolled architecture, it uses more area than the loop-unrolled one. Therefore fully pipelined architecture offer the highest performance, and is suitable for the cases which in the area is not constrained. In contrast to fully pipelined architecture, the smallest case of loop-unrolled, which is sometimes called the round based implementation, uses the lowest area, and is suitable for area constrained applications. This implementation is a loop-unrolled one, however, converting it to it's pipelined alternative is not too hard. ## Encryption For each round of AES encryption, a different subkey is used as the round key, which is produced by the keyschedule algorithm. The following shape represents one round of keyschedule algorithm. ![keyschedule-aes](/Images/keyschedule_round_function.svg) If someone wants to use a fixed key, it is preferable to calculate all subkeys once, and use a lookup table to store subkeys, instead of implementing keyschedule algorithm, and recalculate the subkeys frequently. This strategy is especially suitable for software implementations, where memory is not as constrained as hardware implementations. However, in this repository, the keyschedule is implemented based on the loop-unrolled technique to calculate the subkeys on the fly. In other words, there is a dedicated part implementing keyschedule algorithm based on the loop-unrolled technique, to produce the required subkey for each round on the fly. ### Architecture ![AES-Encryption-Architecture](/Images/aes_enc.svg) ### Synthesis Report (Spartan6-xc6slx75-3fgg676) You can find the details here : [report](https://github.com/hadipourh/AES-VHDL/blob/master/AES-ENC/SynthesisReports/Spartan6/Spartan6-xc6slx75-3fgg676.txt). #### Advanced HDL Synthesis Report ``` ========================================================================= Macro Statistics # RAMs : 20 256x8-bit single-port block Read Only RAM : 4 256x8-bit single-port distributed Read Only RAM : 16 # Registers : 264 Flip-Flops : 264 # Multiplexers : 4 128-bit 2-to-1 multiplexer : 3 8-bit 2-to-1 multiplexer : 1 # Xors : 68 128-bit xor2 : 1 24-bit xor2 : 1 32-bit xor2 : 3 8-bit xor2 : 47 8-bit xor3 : 16 ========================================================================= ``` #### Device Utilization Summary ``` --------------------------- Selected Device : 6slx75fgg676-3 Slice Logic Utilization: Number of Slice Registers: 264 out of 93296 0% Number of Slice LUTs: 1104 out of 46648 2% Number used as Logic: 1104 out of 46648 2% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 1104 Number with an unused Flip Flop: 840 out of 1104 76% Number with an unused LUT: 0 out of 1104 0% Number of fully used LUT-FF pairs: 264 out of 1104 23% Number of unique control sets: 1 IO Utilization: Number of IOs: 387 Number of bonded IOBs: 387 out of 408 94% Specific Feature Utilization: Number of Block RAM/FIFO: 1 out of 172 0% Number using Block RAM only: 1 Number of BUFG/BUFGCTRLs: 1 out of 16 6% ``` #### Timing Summary ``` --------------- Speed Grade: -3 Minimum period: 5.813ns (Maximum Frequency: 172.031MHz) Minimum input arrival time before clock: 4.823ns Maximum output required time after clock: 5.588ns Maximum combinational path delay: No path found ``` ### Throughput According to the synthesis report produced by the ISE Designe Suite, The minimum clock period for our implementation, when Spartan6-xc6slx75-3fgg676 is used as the target device, is 5.813 nano seconds. Therefore the throughput is equal to: ```128 bits/(10*5.813 ns) = 2.2 Gb/s``` ### Synthesis Report (Artix7-xc7a200t-3-ffg1156) You can find the details here: [report](https://github.com/hadipourh/AES-VHDL/blob/master/AES-ENC/SynthesisReports/Artix7/Artix7-xc7a200t-3-ffg1156.txt) ### Advanced HDL Synthesis Report ``` ========================================================================= Macro Statistics # RAMs : 20 256x8-bit single-port block Read Only RAM : 4 256x8-bit single-port distributed Read Only RAM : 16 # Registers : 264 Flip-Flops : 264 # Multiplexers : 4 128-bit 2-to-1 multiplexer : 3 8-bit 2-to-1 multiplexer : 1 # Xors : 68 128-bit xor2 : 1 24-bit xor2 : 1 32-bit xor2 : 3 8-bit xor2 : 47 8-bit xor3 : 16 ========================================================================= ``` #### Device Utilization Summary ``` --------------------------- Selected Device : 7a200tffg1156-3 Slice Logic Utilization: Number of Slice Registers: 264 out of 2692
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