PCIE参考设计

  • h9_803658
    了解作者
  • C/C++
    开发工具
  • 41.6MB
    文件大小
  • zip
    文件格式
  • 0
    收藏次数
  • VIP专享
    资源类型
  • 0
    下载次数
  • 2022-02-21 17:05
    上传日期
关于Altera FPGA的PCIE参考设计代码。
PCIe_hiperf_a2gx.zip
内容介绍
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"> <HTML> <HEAD> <STYLE type="text/css"> A.h:hover { color: "#FF0000"; } A.menu:link { text-decoration: none} A.menu:visited{ text-decoration: none} A.menu:hover {color: #EE9B06;} A.submenu:link { text-decoration: none;} A.submenu:visited { text-decoration: none} A.submenu:hover {color: #EE9B06;} div.category { border-bottom: 5px, solid, black; } br.submenu { line-height: 1em;} br.submenu { line-height: 7px;} BODY, H1, H2, H3, H4, TD, TH, UL, OL, LI, P, DD, DT, DL, INPUT, SELECT, SPAN { font-family : SansSerif, Verdana, Helvetica, Arial, San-sarif; } BODY { background-color : #e0e0e0; } TD, UL, OL, LI, P, DD, DT, DL, SPAN { font-size: 11pt; color : black; } BLOCKQUOTE { font-size: 10pt; color : #000099; } TH { font-size : 11pt; font-weight : bold; font-style : normal; color : black; } H1 { font-size : 18pt; color : black; } H2 { font-size : 14pt; color : black; } H3 { font-size : 12pt; color : black; } H4 { font-size : 11pt; font-weight : bold; color : black; } </style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - PCI Express Compiler v9.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>altpcie_hip_pipen1b</TD></TR><TR><TD><B>Ordering Code</B></TD><TD>IP-PCIE/4</TD></TR><TR><TD><B>Variation Name</B></TD><TD>top</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>/data/pmolson/source/depot/dev_kits/pcie_hw_devkit_img/hip_a2gx_gen1_x8</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>top.v</TD><TD>This Verilog HDL file instantiates the parameterized PCI Express MegaCore function and the logic required to support the specific PHY selected. It is used for both simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_core.v</TD><TD>This Verilog HDL file configures the PCI Express MegaCore function with the parameters specified. It is used for compilation in the Quartus II software.</TD></TR><TR><TD>top_core.vo</TD><TD>This Verilog HDL file is the parameterized IP Functional Simulation model of the MegaCore function. It is used for simulation.</TD></TR><TR><TD>top_examples</TD><TD>This directory contains PCI Express example design and testbench files.</TD></TR><TR><TD>top_examples | chaining_dma</TD><TD>This directory contains the chaining DMA example design and testbench.</TD></TR><TR><TD>top_examples | chaining_dma | altpcie_dma_descriptor.v</TD><TD>This Verilog HDL file contains the altpcie_dma_descriptor module that retrieves DMA read or write descriptors from the root port memory and stores them in a descriptor FIFO. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | altpcie_dma_dt.v</TD><TD>This Verilog HDL file contains the altpcie_dma_dt module that arbitrates between PCI Express packets issued by the altpcie_dma_prg_reg, altpcie_read_dma_requester, altpcie_write_dma_requester and altpcie_dma_descriptor modules. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | altpcie_dma_prg_reg.v</TD><TD>This Verilog HDL file implements the descriptor header table registers. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | altpcie_rc_slave.v</TD><TD>This Verilog HDL file contains the altpcie_rc_slave module that is used by the host software application to retrieve the DMA Performance counter values and directly access the Endpoint memory. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | altpcie_read_dma_requester.v</TD><TD>This Verilog HDL file contains the altpcie_read_dma_requester module that manages DMA read data transfer from the Root Complex memory to the Endpoint memory. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | altpcie_write_dma_requester.v</TD><TD>This Verilog HDL file contains the altpcie_write_dma_requester module that manages DMA write data transfer from the Endpoint memory to the Root Complex memory. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | altpcierd_example_app_chaining.v</TD><TD>This Verilog HDL file contains the altpcierd_example_app_chaining module that is the top level application layer of the chaining DMA example design. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | init_ram.hex</TD><TD>This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in simulation.</TD></TR><TR><TD>top_examples | chaining_dma | init_ram.mif</TD><TD>This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in compilation in the Quartus II software. </TD></TR><TR><TD>top_examples | chaining_dma | testbench</TD><TD>This directory contains files required for simulation of the chaining DMA example design and testbench.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | altpcie_dma_dt_cst_sim.v</TD><TD>This Verilog HDL file contains constants used in the testbench for the chaining DMA example design. It is used in simulation.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | altpcietb_bfm_driver_chaining.v</TD><TD>This Verilog HDL file contains the altpcietb_bfm_driver_chaining module that drives the testing of the chaining DMA example design. This file is used in simulation.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | init_ram.hex</TD><TD>This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in simulation.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | init_ram.mif</TD><TD>This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in compilation in the Quartus II software. </TD></TR><TR><TD>top_examples | chaining_dma | testbench | runtb.bat</TD><TD>This Windows batch file launches the simulation of the chaining DMA example design and testbench.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | runtb.do</TD><TD>This Modelsim simulator TCL script file launches the simulation of the chaining DMA example design and testbench.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | runtb.sh</TD><TD>This shell script file launches the simulation of the chaining DMA example design and testbench. </TD></TR><TR><TD>top_examples | chaining_dma | testbench | sim_filelist</TD><TD>This file is used for simulation of the chaining DMA example design. It contains the list of all the files necessary for compilation in the simulator.</TD></TR><TR><TD>top_examples | chaining_dma | testbench | top_chaining_testbench.v</TD><TD>This Verilog HDL file implements the top level of the testbench for the chaining DMA example design.</TD></TR><TR><TD>top_examples | chaining_dma | top_example_chaining_pipen1b.v</TD><TD>This Verilog HDL file instantiates the chaining DMA example application layer and the PCI Express MegaCore function variation. It is used for simulation and compilation in the Quartus II software.</TD></TR><TR><TD>top_examples | chaining_dma | top_example_chaining_top.qpf</TD><TD>This is the Quartus II project file used for compiling the chaining DMA example design.</TD></TR><TR><TD>top_examples | chaining_dm
评论
    相关推荐
    • FPGA开发电子书
      FPGA开发全攻略,能够从基础开始,深入开发FPGA,并应用于现在最流行的技术领域。
    • FPGA
      EDA程序设计,用FPGA设计一个流水灯,以满足生活中的各种需求
    • FPGA开发资料
      上课时就用的这个PPT,这本书可以说是入门FPGA的经典书籍,这里仅仅上传参考资料,有机会的推荐各位去阅读数字系统设计与Verlog HDL
    • FPGA rs232
      FPGA实现UART 波特率可以自己设置 有详细说明
    • FPGA小球弹跳
      使用FPGA实现操控VGA实现的一个小实验,主要实现的功能是在VGA上显示一个弹跳的小球,其中包含MATLAB的相关仿真,和FPGA实现的代码。
    • FPGA计算器
      VHDL语言撰写的FPGA计算器,共FPGA课程实验参考使用
    • Xilinx FPGA
      Xilinx FPGAXilinx FPGA
    • 学习 FPGA 书籍分享
      废话不说了,下面进入正题,学习FPGA经历了这么几个阶段: ①、Verilog语言的学习,熟悉Verilog语言的各种语法。 ②、FPGA的学习,熟悉QuartusII软件的各种功能,各种逻辑算法设计,接口模块(RS232,LCD,VGA,SPI,...
    • fpga图书 fpga之道
      FPGA之道》是一本针对FPGA技术进行全面、深入讲解的书籍,内容涵盖了数字电路相关基础理论的介绍、FPGA芯片的构成及工作原理、FPGA项目开发的全流程追踪、主流HDL与HVL语法的详细讲解与阐述等,尤其是针对FPGA项目...
    • Xilinx FPGA教程大全
      FPGA工程设计高级研修班_Xilinx.pdf (30 MB) FPGA设计高级技巧_Xilinx.pdf (2.94 MB) Xilinx ROM使用中文教程.pdf (226.08 KB) Xilinx_FPGA_Digital_System_Design_Primer.pdf (7.02 MB) Xilinx_FPGA_...