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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6246fd7f54457c44d0ad67c6/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">S32K1xx Series Reference Manual</div><div class="t m0 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">Supports S32K116, S32K118, S32K142, S32K144, S32K146, and</div><div class="t m0 x3 h3 y3 ff2 fs1 fc0 sc0 ls0 ws0">S32K148</div><div class="t m0 x4 h4 y4 ff2 fs2 fc0 sc0 ls0 ws0">Document Number: S32K1XXRM</div><div class="t m0 x5 h4 y5 ff2 fs2 fc0 sc0 ls0 ws0">Rev. 7, 04/2018</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6246fd7f54457c44d0ad67c6/bg2.jpg"><div class="t m0 x6 h5 y6 ff1 fs3 fc0 sc0 ls0 ws0">S32K1xx Series Reference Manual, Rev. 7, 04/2018</div><div class="t m0 x7 h6 y7 ff2 fs4 fc0 sc0 ls0 ws0">2<span class="_ _0"> </span>NXP Semiconductors</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6246fd7f54457c44d0ad67c6/bg3.jpg"><div class="t m0 x8 h7 y8 ff1 fs5 fc0 sc0 ls0 ws0">Contents</div><div class="t m0 x7 h8 y9 ff1 fs2 fc0 sc0 ls0 ws0">Section number<span class="_ _1"> </span>Title<span class="_ _2"> </span>Page</div><div class="t m0 x9 h8 ya ff1 fs2 fc0 sc0 ls0 ws0">Chapter 1</div><div class="t m0 xa h8 yb ff1 fs2 fc0 sc0 ls0 ws0">About This Manual</div><div class="t m0 x7 h9 yc ff3 fs3 fc1 sc0 ls0 ws0">1.1<span class="_ _3"> </span>Audience.......................................................................................................................................................................<span class="_ _4"> </span>49</div><div class="t m0 x7 h9 yd ff3 fs3 fc1 sc0 ls0 ws0">1.2<span class="_ _3"> </span>Organization..................................................................................................................................................................<span class="_ _5"></span>49</div><div class="t m0 x7 h9 ye ff3 fs3 fc1 sc0 ls0 ws0">1.3<span class="_ _3"> </span>Module descriptions......................................................................................................................................................<span class="_ _6"></span>49</div><div class="t m0 xb h9 yf ff3 fs3 fc1 sc0 ls0 ws0">1.3.1<span class="_ _7"> </span>Example: chip-specific information that clarifies content in the same chapter.............................................<span class="_ _4"> </span>50</div><div class="t m0 xb h9 y10 ff3 fs3 fc1 sc0 ls0 ws0">1.3.2<span class="_ _7"> </span>Example: chip-specific information that refers to a different chapter...........................................................<span class="_ _8"> </span>51</div><div class="t m0 x7 h9 y11 ff3 fs3 fc1 sc0 ls0 ws0">1.4<span class="_ _3"> </span>Register descriptions.....................................................................................................................................................<span class="_ _9"></span>52</div><div class="t m0 x7 h9 y12 ff3 fs3 fc1 sc0 ls0 ws0">1.5<span class="_ _3"> </span>Conventions..................................................................................................................................................................<span class="_ _8"> </span>53</div><div class="t m0 xb h9 y13 ff3 fs3 fc1 sc0 ls0 ws0">1.5.1<span class="_ _7"> </span>Notes, Cautions, and Warnings......................................................................................................................<span class="_ _6"></span>53</div><div class="t m0 xb h9 y14 ff3 fs3 fc1 sc0 ls0 ws0">1.5.2<span class="_ _7"> </span>Numbering systems........................................................................................................................................<span class="_ _6"></span>53</div><div class="t m0 xb h9 y15 ff3 fs3 fc1 sc0 ls0 ws0">1.5.3<span class="_ _7"> </span>Typographic notation.....................................................................................................................................<span class="_ _4"> </span>54</div><div class="t m0 xb h9 y16 ff3 fs3 fc1 sc0 ls0 ws0">1.5.4<span class="_ _7"> </span>Special terms..................................................................................................................................................<span class="_ _a"></span>54</div><div class="t m0 x9 h8 y17 ff1 fs2 fc0 sc0 ls0 ws0">Chapter 2</div><div class="t m0 xc h8 y18 ff1 fs2 fc0 sc0 ls0 ws0">Introduction</div><div class="t m0 x7 h9 y19 ff3 fs3 fc1 sc0 ls0 ws0">2.1<span class="_ _3"> </span>Overview.......................................................................................................................................................................<span class="_ _6"></span>57</div><div class="t m0 x7 h9 y1a ff3 fs3 fc1 sc0 ls0 ws0">2.2<span class="_ _3"> </span>S32K1xx Series introduction........................................................................................................................................<span class="_ _a"></span>57</div><div class="t m0 xb h9 y1b ff3 fs3 fc1 sc0 ls0 ws0">2.2.1<span class="_ _7"> </span>S32K14x.........................................................................................................................................................57</div><div class="t m0 xb h9 y1c ff3 fs3 fc1 sc0 ls0 ws0">2.2.2<span class="_ _7"> </span>S32K11x ........................................................................................................................................................59</div><div class="t m0 x7 h9 y1d ff3 fs3 fc1 sc0 ls0 ws0">2.3<span class="_ _3"> </span>Feature summary...........................................................................................................................................................<span class="_ _5"></span>60</div><div class="t m0 x7 h9 y1e ff3 fs3 fc1 sc0 ls0 ws0">2.4<span class="_ _3"> </span>Block diagram...............................................................................................................................................................<span class="_ _9"></span>63</div><div class="t m0 x7 h9 y1f ff3 fs3 fc1 sc0 ls0 ws0">2.5<span class="_ _3"> </span>Feature comparison.......................................................................................................................................................<span class="_ _9"></span>64</div><div class="t m0 x7 h9 y20 ff3 fs3 fc1 sc0 ls0 ws0">2.6<span class="_ _3"> </span>Applications..................................................................................................................................................................<span class="_ _a"></span>66</div><div class="t m0 x7 h9 y21 ff3 fs3 fc1 sc0 ls0 ws0">2.7<span class="_ _3"> </span>Module functional categories........................................................................................................................................<span class="_ _5"></span>67</div><div class="t m0 xb h9 y22 ff3 fs3 fc1 sc0 ls0 ws0">2.7.1<span class="_ _7"> </span>Arm Cortex-M4F Core Modules....................................................................................................................68</div><div class="t m0 xb h9 y23 ff3 fs3 fc1 sc0 ls0 ws0">2.7.2<span class="_ _7"> </span>Arm Cortex-M0+ Core Modules....................................................................................................................69</div><div class="t m0 xb h9 y24 ff3 fs3 fc1 sc0 ls0 ws0">2.7.3<span class="_ _7"> </span>System modules.............................................................................................................................................<span class="_ _8"> </span>69</div><div class="t m0 xb h9 y25 ff3 fs3 fc1 sc0 ls0 ws0">2.7.4<span class="_ _7"> </span>Memories and memory interfaces..................................................................................................................<span class="_ _9"></span>70</div><div class="t m0 x6 h5 y6 ff1 fs3 fc0 sc0 ls0 ws0">S32K1xx Series Reference Manual, Rev. 7, 04/2018</div><div class="t m0 x7 h6 y7 ff2 fs4 fc0 sc0 ls0 ws0">NXP Semiconductors<span class="_ _0"> </span>3</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6246fd7f54457c44d0ad67c6/bg4.jpg"><div class="t m0 x7 h8 y26 ff1 fs2 fc0 sc0 ls0 ws0">Section number<span class="_ _1"> </span>Title<span class="_ _2"> </span>Page</div><div class="t m0 xb h9 y27 ff3 fs3 fc1 sc0 ls0 ws0">2.7.5<span class="_ _7"> </span>Power Management........................................................................................................................................71</div><div class="t m0 xb h9 y28 ff3 fs3 fc1 sc0 ls0 ws0">2.7.6<span class="_ _7"> </span>Clocking.........................................................................................................................................................<span class="_ _a"></span>71</div><div class="t m0 xb h9 y29 ff3 fs3 fc1 sc0 ls0 ws0">2.7.7<span class="_ _7"> </span>Analog modules.............................................................................................................................................<span class="_ _8"> </span>72</div><div class="t m0 xb h9 y2a ff3 fs3 fc1 sc0 ls0 ws0">2.7.8<span class="_ _7"> </span>Timer modules...............................................................................................................................................<span class="_ _8"> </span>72</div><div class="t m0 xb h9 y2b ff3 fs3 fc1 sc0 ls0 ws0">2.7.9<span class="_ _7"> </span>Communication interfaces.............................................................................................................................<span class="_ _8"> </span>73</div><div class="t m0 xb h9 y2c ff3 fs3 fc1 sc0 ls0 ws0">2.7.10<span class="_ _b"> </span>Debug modules..............................................................................................................................................<span class="_"> </span>73</div><div class="t m0 x9 h8 y2d ff1 fs2 fc0 sc0 ls0 ws0">Chapter 3</div><div class="t m0 xd h8 y2e ff1 fs2 fc0 sc0 ls0 ws0">Memory Map</div><div class="t m0 x7 h9 y2f ff3 fs3 fc1 sc0 ls0 ws0">3.1<span class="_ _3"> </span>Introduction...................................................................................................................................................................<span class="_ _6"></span>75</div><div class="t m0 x7 h9 y30 ff3 fs3 fc1 sc0 ls0 ws0">3.2<span class="_ _3"> </span>SRAM memory map.....................................................................................................................................................<span class="_ _a"></span>75</div><div class="t m0 xb h9 y31 ff3 fs3 fc1 sc0 ls0 ws0">3.2.1<span class="_ _7"> </span>S32K14x: SRAM memory map ....................................................................................................................<span class="_ _9"></span>75</div><div class="t m0 xb h9 y32 ff3 fs3 fc1 sc0 ls0 ws0">3.2.2<span class="_ _7"> </span>S32K11x: SRAM memory map ....................................................................................................................<span class="_ _9"></span>75</div><div class="t m0 x7 h9 y33 ff3 fs3 fc1 sc0 ls0 ws0">3.3<span class="_ _3"> </span>Flash memory map........................................................................................................................................................<span class="_ _5"></span>76</div><div class="t m0 x7 h9 y34 ff3 fs3 fc1 sc0 ls0 ws0">3.4<span class="_ _3"> </span>Peripheral bridge (AIPS-Lite) memory map.................................................................................................................76</div><div class="t m0 xb h9 y35 ff3 fs3 fc1 sc0 ls0 ws0">3.4.1<span class="_ _7"> </span>Read-after-write sequence and required serialization of memory operations................................................<span class="_ _5"></span>77</div><div class="t m0 x7 h9 y36 ff3 fs3 fc1 sc0 ls0 ws0">3.5<span class="_ _3"> </span>Private Peripheral Bus (PPB) memory map..................................................................................................................78</div><div class="t m0 x7 h9 y37 ff3 fs3 fc1 sc0 ls0 ws0">3.6<span class="_ _3"> </span>Aliased bit-band regions for CM4 core........................................................................................................................<span class="_ _c"> </span>79</div><div class="t m0 x9 h8 y38 ff1 fs2 fc0 sc0 ls0 ws0">Chapter 4</div><div class="t m0 xe h8 y39 ff1 fs2 fc0 sc0 ls0 ws0">Signal Multiplexing and Pin Assignment</div><div class="t m0 x7 h9 y3a ff3 fs3 fc1 sc0 ls0 ws0">4.1<span class="_ _3"> </span>Introduction...................................................................................................................................................................<span class="_ _6"></span>81</div><div class="t m0 x7 h9 y3b ff3 fs3 fc1 sc0 ls0 ws0">4.2<span class="_ _3"> </span>Functional description...................................................................................................................................................<span class="_ _5"></span>81</div><div class="t m0 x7 h9 y3c ff3 fs3 fc1 sc0 ls0 ws0">4.3<span class="_ _3"> </span>Pad description..............................................................................................................................................................<span class="_ _6"></span>82</div><div class="t m0 x7 h9 y3d ff3 fs3 fc1 sc0 ls0 ws0">4.4<span class="_ _3"> </span>Default pad state...........................................................................................................................................................<span class="_ _c"> </span>83</div><div class="t m0 x7 h9 y3e ff3 fs3 fc1 sc0 ls0 ws0">4.5<span class="_ _3"> </span>Signal Multiplexing sheet.............................................................................................................................................<span class="_ _4"> </span>84</div><div class="t m0 xb h9 y3f ff3 fs3 fc1 sc0 ls0 ws0">4.5.1<span class="_ _7"> </span>IO Signal Table .............................................................................................................................................<span class="_ _4"> </span>84</div><div class="t m0 xb h9 y40 ff3 fs3 fc1 sc0 ls0 ws0">4.5.2<span class="_ _7"> </span>Input muxing table.........................................................................................................................................<span class="_ _4"> </span>86</div><div class="t m0 x7 h9 y41 ff3 fs3 fc1 sc0 ls0 ws0">4.6<span class="_ _3"> </span>Pinout diagrams............................................................................................................................................................<span class="_ _c"> </span>87</div><div class="t m0 x9 h8 y42 ff1 fs2 fc0 sc0 ls0 ws0">Chapter 5</div><div class="t m0 xf h8 y43 ff1 fs2 fc0 sc0 ls0 ws0">Security Overview</div><div class="t m0 x7 h9 y44 ff3 fs3 fc1 sc0 ls0 ws0">5.1<span class="_ _3"> </span>Introduction...................................................................................................................................................................<span class="_ _6"></span>89</div><div class="t m0 x6 h5 y6 ff1 fs3 fc0 sc0 ls0 ws0">S32K1xx Series Reference Manual, Rev. 7, 04/2018</div><div class="t m0 x7 h6 y7 ff2 fs4 fc0 sc0 ls0 ws0">4<span class="_ _0"> </span>NXP Semiconductors</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6246fd7f54457c44d0ad67c6/bg5.jpg"><div class="t m0 x7 h8 y26 ff1 fs2 fc0 sc0 ls0 ws0">Section number<span class="_ _1"> </span>Title<span class="_ _2"> </span>Page</div><div class="t m0 x7 h9 y27 ff3 fs3 fc1 sc0 ls0 ws0">5.2<span class="_ _3"> </span>Device security..............................................................................................................................................................89</div><div class="t m0 xb h9 y28 ff3 fs3 fc1 sc0 ls0 ws0">5.2.1<span class="_ _7"> </span>Flash memory security...................................................................................................................................<span class="_ _a"></span>89</div><div class="t m0 xb h9 y29 ff3 fs3 fc1 sc0 ls0 ws0">5.2.2<span class="_ _7"> </span>Cryptographic Services Engine (CSEc) security features..............................................................................<span class="_ _5"></span>90</div><div class="t m0 xb h9 y2a ff3 fs3 fc1 sc0 ls0 ws0">5.2.3<span class="_ _7"> </span>Device Boot modes........................................................................................................................................<span class="_ _4"> </span>91</div><div class="t m0 x7 h9 y2b ff3 fs3 fc1 sc0 ls0 ws0">5.3<span class="_ _3"> </span>Security use case examples...........................................................................................................................................<span class="_ _9"></span>91</div><div class="t m0 xb h9 y2c ff3 fs3 fc1 sc0 ls0 ws0">5.3.1<span class="_ _7"> </span>Secure boot: check bootloader for integrity and authenticity........................................................................<span class="_ _4"> </span>91</div><div class="t m0 xb h9 y45 ff3 fs3 fc1 sc0 ls0 ws0">5.3.2<span class="_ _7"> </span>Chain of trust: check flash memory for integrity and authenticity................................................................<span class="_ _4"> </span>92</div><div class="t m0 xb h9 y46 ff3 fs3 fc1 sc0 ls0 ws0">5.3.3<span class="_ _7"> </span>Secure communication...................................................................................................................................<span class="_ _9"></span>93</div><div class="t m0 xb h9 y47 ff3 fs3 fc1 sc0 ls0 ws0">5.3.4<span class="_ _7"> </span>Component protection....................................................................................................................................<span class="_ _6"></span>94</div><div class="t m0 xb h9 y48 ff3 fs3 fc1 sc0 ls0 ws0">5.3.5<span class="_ _7"> </span>Message-authentication example...................................................................................................................<span class="_ _4"> </span>95</div><div class="t m0 x7 h9 y49 ff3 fs3 fc1 sc0 ls0 ws0">5.4<span class="_ _3"> </span>Steps required before failure analysis...........................................................................................................................<span class="_ _a"></span>96</div><div class="t m0 x7 h9 y4a ff3 fs3 fc1 sc0 ls0 ws0">5.5<span class="_ _3"> </span>Security programming flow example (Secure Boot)....................................................................................................<span class="_ _4"> </span>97</div><div class="t m0 x9 h8 y4b ff1 fs2 fc0 sc0 ls0 ws0">Chapter 6</div><div class="t m0 x10 h8 y4c ff1 fs2 fc0 sc0 ls0 ws0">Safety Overview</div><div class="t m0 x7 h9 y35 ff3 fs3 fc1 sc0 ls0 ws0">6.1<span class="_ _3"> </span>Introduction...................................................................................................................................................................<span class="_ _6"></span>99</div><div class="t m0 x7 h9 y36 ff3 fs3 fc1 sc0 ls0 ws0">6.2<span class="_ _3"> </span>S32K1xx safety concept...............................................................................................................................................<span class="_ _c"> </span>100</div><div class="t m0 xb h9 y37 ff3 fs3 fc1 sc0 ls0 ws0">6.2.1<span class="_ _7"> </span>Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................<span class="_ _9"></span>101</div><div class="t m0 xb h9 y4d ff3 fs3 fc1 sc0 ls0 ws0">6.2.2<span class="_ _7"> </span>ECC on RAM and flash memory...................................................................................................................<span class="_ _9"></span>102</div><div class="t m0 xb h9 y4e ff3 fs3 fc1 sc0 ls0 ws0">6.2.3<span class="_ _7"> </span>Power supply monitoring...............................................................................................................................<span class="_ _a"></span>102</div><div class="t m0 xb h9 y4f ff3 fs3 fc1 sc0 ls0 ws0">6.2.4<span class="_ _7"> </span>Clock monitoring...........................................................................................................................................<span class="_ _8"> </span>103</div><div class="t m0 xb h9 y50 ff3 fs3 fc1 sc0 ls0 ws0">6.2.5<span class="_ _7"> </span>Temporal protection.......................................................................................................................................<span class="_ _9"></span>103</div><div class="t m0 xb h9 y51 ff3 fs3 fc1 sc0 ls0 ws0">6.2.6<span class="_ _7"> </span>Operational interference protection...............................................................................................................<span class="_"> </span>103</div><div class="t m0 xb h9 y52 ff3 fs3 fc1 sc0 ls0 ws0">6.2.7<span class="_ _7"> </span>CRC................................................................................................................................................................<span class="_ _5"></span>105</div><div class="t m0 xb h9 y53 ff3 fs3 fc1 sc0 ls0 ws0">6.2.8<span class="_ _7"> </span>Diversity of system resources........................................................................................................................<span class="_ _4"> </span>105</div><div class="t m0 x9 h8 y54 ff1 fs2 fc0 sc0 ls0 ws0">Chapter 7</div><div class="t m0 x11 h8 y55 ff1 fs2 fc0 sc0 ls0 ws0">CM4 Overview</div><div class="t m0 x7 h9 y41 ff3 fs3 fc1 sc0 ls0 ws0">7.1<span class="_ _3"> </span>Arm Cortex-M4F core configuration............................................................................................................................<span class="_ _6"></span>107</div><div class="t m0 xb h9 y56 ff3 fs3 fc1 sc0 ls0 ws0">7.1.1<span class="_ _7"> </span>Buses, interconnects, and interfaces..............................................................................................................<span class="_"> </span>108</div><div class="t m0 xb h9 y57 ff3 fs3 fc1 sc0 ls0 ws0">7.1.2<span class="_ _7"> </span>System Tick Timer.........................................................................................................................................<span class="_ _6"></span>108</div><div class="t m0 x6 h5 y6 ff1 fs3 fc0 sc0 ls0 ws0">S32K1xx Series Reference Manual, Rev. 7, 04/2018</div><div class="t m0 x7 h6 y7 ff2 fs4 fc0 sc0 ls0 ws0">NXP Semiconductors<span class="_ _0"> </span>5</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return 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