S32K144_DEMO-O.rar

  • F2_468841
    了解作者
  • C/C++
    开发工具
  • 1.2MB
    文件大小
  • rar
    文件格式
  • 0
    收藏次数
  • VIP专享
    资源类型
  • 0
    下载次数
  • 2022-02-28 14:13
    上传日期
名称:CQU_S32K144_DEV开发板/评估板---综合应用DEMO例程 * 功能:(1) 启用PLL并设定系统时钟频率为160MHz(基于芯片外部的8MHz的XOSC晶振) * (2) 运用GPIO功能,完成4个LED灯输出控制和4个按键SW的输入检测 * (3) 运用ADC模块的A/D转换功能,采集通道0的模数转换数字量 * (4) 运用LPUART串口通信功能,发送数据(9600bps) * (5) 运用FlexCAN总线通信功能,CAN0发送数据(500Kbps),CAN1中断接收数据(500Kbps) * (6) 运用LPIT定时器超时中断功能,每定时时间到(1s)读取A/D转换结果并通过CAN_0发送
S32K144_DEMO-O.rar
  • include
  • devassert.h
    4KB
  • S32K144.h
    746.7KB
  • S32K144_features.h
    80.2KB
  • s32_core_cm4.h
    6.9KB
  • startup.h
    1.7KB
  • device_registers.h
    2.3KB
  • system_S32K144.h
    3.4KB
  • .settings
  • language.settings.xml
    3KB
  • com.processorexpert.core.ide.newprojectwizard.prefs
    87B
  • org.eclipse.cdt.codan.core.prefs
    62B
  • com.freescale.s32ds.cross.wizard.prefs
    291B
  • org.eclipse.cdt.core.prefs
    1.5KB
  • src
  • LPIT.h
    172B
  • clocks_and_modes.h
    184B
  • LPUART.c
    3.7KB
  • ADC.h
    348B
  • main.c
    8.4KB
  • LPIT.c
    1.5KB
  • LPUART.h
    324B
  • FlexCAN.c
    11.1KB
  • LPSPI.c
    5.9KB
  • ADC.c
    2KB
  • LPSPI.h
    381B
  • FlexCAN.h
    490B
  • clocks_and_modes.c
    2.8KB
  • Project_Settings
  • Startup_Code
  • system_S32K144.c
    7.8KB
  • startup_S32K144.S
    31.1KB
  • startup.c
    7.9KB
  • Linker_Files
  • S32K1xx_flash.ld
    8KB
  • S32K1xx_ram.ld
    6.8KB
  • Debugger
  • S32K144_DEMO_Debug_RAM.launch
    18.1KB
  • S32K144_DEMO_Debug.launch
    19.6KB
  • S32K144_DEMO_Release.launch
    18.1KB
  • Debug
  • src
  • LPSPI.o
    538.2KB
  • main.args
    536B
  • LPSPI.d
    1.9KB
  • ADC.d
    1.8KB
  • subdir.mk
    3.4KB
  • FlexCAN.o
    545.1KB
  • clocks_and_modes.o
    540.5KB
  • LPUART.d
    1.9KB
  • ADC.o
    540.9KB
  • LPIT.args
    536B
  • clocks_and_modes.d
    2KB
  • clocks_and_modes.args
    536B
  • LPIT.d
    1.9KB
  • LPUART.o
    541.2KB
  • FlexCAN.args
    536B
  • main.d
    2KB
  • ADC.args
    536B
  • LPIT.o
    539.3KB
  • FlexCAN.d
    1.9KB
  • main.o
    547.9KB
  • LPUART.args
    536B
  • LPSPI.args
    536B
  • Project_Settings
  • Startup_Code
  • startup.d
    2.6KB
  • subdir.mk
    2.7KB
  • startup.o
    569.4KB
  • startup_S32K144.o
    9.6KB
  • system_S32K144.args
    536B
  • system_S32K144.d
    2.6KB
  • system_S32K144.o
    570.8KB
  • startup_S32K144.args
    471B
  • startup.args
    536B
  • Linker_Files
  • subdir.mk
    549B
  • sources.mk
    1.3KB
  • objects.mk
    276B
  • S32K144_DEMO.elf
    580.4KB
  • S32K144_DEMO.args
    548B
  • makefile
    2.2KB
  • makefile.local
    379B
  • S32K144_DEMO.map
    64.1KB
  • .project
    790B
  • .cproject
    65.6KB
内容介绍
/* FlexCAN.c (c) 2016 NXP * Descriptions: S32K144 CAN 2.0 A/B example.. * 2016 Jul 16 S. Mihalik: Initial version * 2016 Sep 12 SM: Updated with SBC init, Node A - B communication * 2016 Oct 31 SM: Updated for new header symbols for PCCn * 2017 Jul 03 SM: Removed code for 33903 on obsolete EVB */ #include "S32K144.h" /* include peripheral declarations S32K144 */ #include "FlexCAN.h" uint8_t CAN0_TxData[8] = {0x88,0x99,0xAA,0xBB,0xCC,0xDD,0xEE,0xFF}; /* Transmit data */ uint8_t CAN0_RxData[8] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55}; /* Received data */ uint8_t CAN1_TxData[8] = {0x88,0x99,0xAA,0xBB,0xCC,0xDD,0xEE,0xFF}; /* Transmit data */ uint8_t CAN1_RxData[8] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55}; /* Received data */ uint32_t RxCODE; /* Received message buffer code */ uint32_t RxID; /* Received message ID */ uint32_t RxLENGTH; /* Recieved message number of data bytes */ uint32_t RxDATA[2]; /* Received message data (2 words) */ uint32_t RxTIMESTAMP; /* Received message time */ void FLEXCAN0_init(void) { #define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */ uint32_t i=0; PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */ CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */ CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */ CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/ while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {} /* Good practice: wait for FRZACK=1 on freeze mode entry/exit */ CAN0->CTRL1 = 0x00DB0006; /* Configure for 500 KHz bit time */ /* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */ /* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */ /* so PRESDIV = 0 */ /* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */ /* PSEG1 = PSEG2 = 3 */ /* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */ /* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */ /* SMP = 1: use 3 bits per CAN sample */ /* CLKSRC=0 (unchanged): Fcanclk= Fosc= 8 MHz */ for(i=0; i<128; i++ ) { /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words*/ CAN0->RAMn[i] = 0; /* Clear msg buf word */ } for(i=0; i<16; i++ ) { /* In FRZ mode, init CAN0 16 msg buf filters */ CAN0->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */ } CAN0->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */ CAN0->RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */ /* EDL,BRS,ESI=0: CANFD not used */ /* CODE=4: MB set to RX inactive */ /* IDE=0: Standard ID */ /* SRR, RTR, TIME STAMP = 0: not applicable */ CAN0->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x14440000; // Msg Buf 4 to receive msg, word 1: STD ID 0x511 /* PRIO = 0: CANFD not used */ CAN0->MCR = 0x0000001F; /* Negate FlexCAN 1 halt state for 32 MBs */ while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {} /* Good practice: wait for FRZACK to clear (not in freeze mode) */ while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {} /* Good practice: wait for NOTRDY to clear (module ready) */ } void FLEXCAN0_transmit_msg(void) { /* Assumption: Message buffer CODE is INACTIVE */ CAN0->IFLAG1 = 0x00000001; /* Clear CAN0 MB 0 flag without clearing others*/ //CAN0->RAMn[ 0*MSG_BUF_SIZE + 2] = 0xA5112233; /* MB0 word 2: data word 0 */ //CAN0->RAMn[ 0*MSG_BUF_SIZE + 3] = 0x44556677; /* MB0 word 3: data word 1 */ CAN0->RAMn[ 0*MSG_BUF_SIZE + 2] = (CAN0_TxData[0]<<24) + (CAN0_TxData[1]<<16) + (CAN0_TxData[2]<<8) + (CAN0_TxData[3]<<0); /* MB0 word 2: data word 0 */ CAN0->RAMn[ 0*MSG_BUF_SIZE + 3] = (CAN0_TxData[4]<<24) + (CAN0_TxData[5]<<16) + (CAN0_TxData[6]<<8) + (CAN0_TxData[7]<<0); /* MB0 word 3: data word 1 */ CAN0->RAMn[ 0*MSG_BUF_SIZE + 1] = 0x15540000; // MB0 word 1: Tx msg with STD ID 0x555 CAN0->RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C400000 | 8 <<CAN_WMBn_CS_DLC_SHIFT; /* MB0 word 0: */ /* EDL,BRS,ESI=0: CANFD not used */ /* CODE=0xC: Activate msg buf to transmit */ /* IDE=0: Standard ID */ /* SRR=1 Tx frame (not req'd for std ID) */ /* RTR = 0: data, not remote tx request frame*/ /* DLC = 8 bytes */ } void FLEXCAN0_receive_msg(void) { /* Receive msg from ID 0x511 using msg buffer 4 */ uint8_t j; uint32_t dummy; RxCODE = (CAN0->RAMn[ 4*MSG_BUF_SIZE + 0] & 0x07000000) >> 24; /* Read CODE field */ RxID = (CAN0->RAMn[ 4*MSG_BUF_SIZE + 1] & CAN_WMBn_ID_ID_MASK) >> CAN_WMBn_ID_ID_SHIFT ; RxLENGTH = (CAN0->RAMn[ 4*MSG_BUF_SIZE + 0] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT; for (j=0; j<2; j++) { /* Read two words of data (8 bytes) */ RxDATA[j] = CAN0->RAMn[ 4*MSG_BUF_SIZE + 2 + j]; } CAN0_RxData[0]=(RxDATA[0]>>24); CAN0_RxData[1]=(RxDATA[0]>>16); CAN0_RxData[2]=(RxDATA[0]>>8); CAN0_RxData[3]=(RxDATA[0]>>0); CAN0_RxData[4]=(RxDATA[1]>>24); CAN0_RxData[5]=(RxDATA[1]>>16); CAN0_RxData[6]=(RxDATA[1]>>8); CAN0_RxData[7]=(RxDATA[1]>>0); RxTIMESTAMP = (CAN0->RAMn[ 0*MSG_BUF_SIZE + 0] & 0x000FFFF); dummy = CAN0->TIMER; /* Read TIMER to unlock message buffers */ if(dummy){}; CAN0->IFLAG1 = 0x00000010; /* Clear CAN 0 MB 4 flag without clearing others*/ } void FLEXCAN1_init(void) { #define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */ uint32_t i=0; PCC->PCCn[PCC_FlexCAN1_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN1 */ CAN1->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */ CAN1->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */ CAN1->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/ while (!((CAN1->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {} /* Good practice: wait for FRZACK=1 on freeze mode entry/exit */ CAN1->CTRL1 = 0x00DB0006; /* Configure for 500 KHz bit time */ /* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */ /* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */ /* so PRESDIV = 0 */ /* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */ /* PSEG1 = PSEG2 = 3 */ /* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */ /* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */ /* SMP = 1: use 3 bits per CAN sample */ /* CLKSRC=0 (unchanged): Fcanclk= Fosc= 8 MHz */ for(i=0; i<128; i++ ) { /* CAN1: clear 32 msg bufs x 4 words/msg buf = 128 words*/ //CAN1->RAMn[i] = 0; /* Clear msg buf word */ } for(i=0; i<16; i++ ) { /* In FRZ mode, init CAN1 16 msg buf filters */ CAN1->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */ } CAN1->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */ CAN1->RAMn[ 4*MSG_BUF_SIZE + 0
评论
    相关推荐
    • 嵌入式
      嵌入式 芝麻实验室
    • 嵌入式课件
      嵌入式课件,很详细,我们的课件 嵌入式课件,很详细,我们的课件
    • 嵌入式课件
      嵌入式课件PPT 通过讲义可了解嵌入式开发的基础内涵代码及具体操作讲解
    • 嵌入式课件
      这是学校的嵌入式课件,讲的比较详细,有问题欢迎大家到我空间留言或博客交流哦
    • 嵌入式课件
      嵌入式授课的ppt文件,是初学嵌入式的学习文件,适合初学者
    • 嵌入式课件
      大学嵌入式系统的课件,内容比较详细,学完后入门不是问题。
    • 嵌入式开发
      嵌入式开发方面的非常好的书籍,希望上传共享,请大家积极点评。
    • 嵌入式教程
      嵌入式教程,让你全面了解嵌入式,西工大出品很不错的哦~~~
    • 嵌入式
      嵌入式
    • 嵌入式开发
      ARM应用系统开发详解.pdf C&C++嵌入式系统编程.pdf 嵌入式处理器体系结构发展漫谈.pdf 嵌入式系统的C程序设计.pdf 嵌入式操作系统综述.pdf