Freescale官方 QorIQ处理器T1040RDB 原理图(ORCAD+pdf).rar

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概述 QorIQ T1040四核和T1020双核通信处理器可支持两个或4个集成式64位e5500 Power Architecture®处理器内核,提供网络和通信所需的高性能数据通路加速架构(DPAA)和网络外设接口。 T1040和T1020是业界首款集成了千兆以太网交换机的64位嵌入式处理器。T系列适用于混合控制和数据平台应用,如固定路由器、交换机、嵌入式接入设备、防火墙和其他数据包过滤应用,以及通用嵌入式计算。它具备较高的集成度,可提供卓越的性能优势,简化硬件和软件设计。 T1系列器件是业界最具可扩展性和引脚兼容性的通信处理器之一 – 为向更高性能的QorIQ T2081器件迁移提供了一条引脚兼容的途径。 T1040RDB_0116_Reversion_B.rar (492.93 KB, 下载次数: 137 ) T1040RDB_SCH0116.pdf (461.69 KB, 下载次数: 134 ) 处理器 , 防火墙 , 可扩展性 , 路由器 , 软件设计
Freescale官方 QorIQ处理器T1040RDB 原理图(ORCAD+pdf).rar
  • T1040RDB_0116_Reversion_B.rar
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  • T1040RDB_SCH0116.pdf
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内容介绍
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_0"> </span>D</div><div class="t m0 x7 h3 y7 ff2 fs1 fc0 sc0 ls0 ws0">Version Control</div><div class="t m0 x7 h4 y8 ff1 fs2 fc0 sc0 ls0 ws0">Version</div><div class="t m0 x8 h4 y9 ff1 fs2 fc0 sc0 ls0 ws0">V0.1</div><div class="t m0 x9 h4 y8 ff1 fs2 fc0 sc0 ls0 ws0">Date</div><div class="t m0 x9 h4 y9 ff1 fs2 fc0 sc0 ls0 ws0">2013/06</div><div class="t m0 xa h4 y8 ff1 fs2 fc0 sc0 ls0 ws0">Modifications</div><div class="t m0 xa h4 y9 ff1 fs2 fc0 sc0 ls0 ws0">First release of Schematics</div><div class="t m0 xb h5 ya ff1 fs3 fc0 sc0 ls0 ws0">T1040RDB</div><div class="t m0 xc h6 yb ff2 fs4 fc0 sc0 ls0 ws0">Page Description</div><div class="t m0 xd h4 yc ff1 fs2 fc0 sc0 ls0 ws0">1<span class="_ _1"> </span>SCHEMATIC PAGE LISTING</div><div class="t m0 xd h4 yd ff1 fs2 fc0 sc0 ls0 ws0">2</div><div class="t m0 xd h4 ye ff1 fs2 fc0 sc0 ls0 ws0">3</div><div class="t m0 xe h4 yd ff1 fs2 fc0 sc0 ls0 ws0">SYSTEM BLOCK DIAGRAM</div><div class="t m0 xd h4 yf ff1 fs2 fc0 sc0 ls0 ws0">4</div><div class="t m0 xd h4 y10 ff1 fs2 fc0 sc0 ls0 ws0">5</div><div class="t m0 xd h4 y11 ff1 fs2 fc0 sc0 ls0 ws0">6</div><div class="t m0 xd h4 y12 ff1 fs2 fc0 sc0 ls0 ws0">7</div><div class="t m0 xd h4 y13 ff1 fs2 fc0 sc0 ls0 ws0">8</div><div class="t m0 xd h4 y14 ff1 fs2 fc0 sc0 ls0 ws0">9</div><div class="t m0 xe h4 y15 ff1 fs2 fc0 sc0 ls0 ws0">MECHANICALs</div><div class="t m0 xf h6 y16 ff2 fs4 fc0 sc0 ls0 ws0">Variants Description</div><div class="t m0 x10 h4 y17 ff1 fs2 fc0 sc0 ls0 ws0">INTERPOSER version (normal + VIT)<span class="_ _2"></span>INTERPOSER</div><div class="t m0 x7 h4 y18 ff1 fs2 fc0 sc0 ls0 ws0">T1040/T2081 RDB<span class="_ _3"> </span>T1040RDB version (normal + VNIT)</div><div class="t m0 xc h4 y19 ff1 fs2 fc0 sc0 ls0 ws0">10</div><div class="t m0 xc h4 y1a ff1 fs2 fc0 sc0 ls0 ws0">11</div><div class="t m0 xc h4 y1b ff1 fs2 fc0 sc0 ls0 ws0">12</div><div class="t m0 xc h4 y1c ff1 fs2 fc0 sc0 ls0 ws0">13</div><div class="t m0 xc h4 y1d ff1 fs2 fc0 sc0 ls0 ws0">14</div><div class="t m0 xc h4 y1e ff1 fs2 fc0 sc0 ls0 ws0">15</div><div class="t m0 xc h4 y1f ff1 fs2 fc0 sc0 ls0 ws0">16</div><div class="t m0 xc h4 y20 ff1 fs2 fc0 sc0 ls0 ws0">17</div><div class="t m0 xc h4 y21 ff1 fs2 fc0 sc0 ls0 ws0">18</div><div class="t m0 xc h4 y22 ff1 fs2 fc0 sc0 ls0 ws0">19</div><div class="t m0 xc h4 y23 ff1 fs2 fc0 sc0 ls0 ws0">20</div><div class="t m0 xc h4 y24 ff1 fs2 fc0 sc0 ls0 ws0">21</div><div class="t m0 xc h4 y25 ff1 fs2 fc0 sc0 ls0 ws0">22</div><div class="t m0 xc h4 y26 ff1 fs2 fc0 sc0 ls0 ws0">23</div><div class="t m0 xc h4 y27 ff1 fs2 fc0 sc0 ls0 ws0">24</div><div class="t m0 xc h4 y28 ff1 fs2 fc0 sc0 ls0 ws0">25</div><div class="t m0 xc h4 y29 ff1 fs2 fc0 sc0 ls0 ws0">26</div><div class="t m0 xc h4 y2a ff1 fs2 fc0 sc0 ls0 ws0">27</div><div class="t m0 xc h4 y2b ff1 fs2 fc0 sc0 ls0 ws0">28</div><div class="t m0 xc h4 y2c ff1 fs2 fc0 sc0 ls0 ws0">29</div><div class="t m0 xc h4 y2d ff1 fs2 fc0 sc0 ls0 ws0">30</div><div class="t m0 xe h4 y2e ff1 fs2 fc0 sc0 ls0 ws0">T1040 DDR3L MEMORY INTERFACE</div><div class="t m0 xe h4 y2f ff1 fs2 fc0 sc0 ls0 ws0">T1040 IFC INTERFACE</div><div class="t m0 xe h4 y30 ff1 fs2 fc0 sc0 ls0 ws0">T1040 NOR and NAND FLASH INTERFACE</div><div class="t m0 xe h4 y31 ff1 fs2 fc0 sc0 ls0 ws0">T1040 SPI FLASH and SDHC INTERFACE</div><div class="t m0 xe h4 y32 ff1 fs2 fc0 sc0 ls0 ws0">T1040 SYSTEM LOGIC INTERFACE</div><div class="t m0 xe h4 y33 ff1 fs2 fc0 sc0 ls0 ws0">T1040 ETHERNET and SERDES INTERFACE</div><div class="t m0 xe h4 y34 ff1 fs2 fc0 sc0 ls0 ws0">T1040 USB INTERFACE</div><div class="t m0 xe h4 y35 ff1 fs2 fc0 sc0 ls0 ws0">T1040 QE INTERFACE</div><div class="t m0 xe h4 y36 ff1 fs2 fc0 sc0 ls0 ws0">T1040 POWER SUPPLY</div><div class="t m0 xe h4 y37 ff1 fs2 fc0 sc0 ls0 ws0">T1040 PLL FILTERs and GROUND</div><div class="t m0 xe h4 y38 ff1 fs2 fc0 sc0 ls0 ws0">T1040 DUART INTERFACE</div><div class="t m0 xe h4 y39 ff1 fs2 fc0 sc0 ls0 ws0">RGMII ETHERNET PORT 1</div><div class="t m0 xe h4 y3a ff1 fs2 fc0 sc0 ls0 ws0">RGMII ETHERNET PORT 2</div><div class="t m0 xe h4 y3b ff1 fs2 fc0 sc0 ls0 ws0">SGMII ETHERNET PORT</div><div class="t m0 xe h4 y3c ff1 fs2 fc0 sc0 ls0 ws0">QSGMII PHY 1</div><div class="t m0 xe h4 y3d ff1 fs2 fc0 sc0 ls0 ws0">QSGMII PHY 2</div><div class="t m0 xe h4 y3e ff1 fs2 fc0 sc0 ls0 ws0">QSGMII ETHERNET PORTs</div><div class="t m0 xe h4 y3f ff1 fs2 fc0 sc0 ls0 ws0">10G EDC PHY and SFP+ CONNECTOR</div><div class="t m0 xe h4 y40 ff1 fs2 fc0 sc0 ls0 ws0">PCIe X1/X4 SLOT, MINI PCIe and SATA CONNECTORs</div><div class="t m0 xe h4 y41 ff1 fs2 fc0 sc0 ls0 ws0">POTS 1&amp;2 INTERFACE</div><div class="t m0 xe h4 y42 ff1 fs2 fc0 sc0 ls0 ws0">POTS 3&amp;4 INTERFACE</div><div class="t m0 xe h4 y43 ff1 fs2 fc0 sc0 ls0 ws0">POTS VBAT POWER SUPPLY</div><div class="t m0 xe h4 y44 ff1 fs2 fc0 sc0 ls0 ws0">CPLD</div><div class="t m0 xe h4 y45 ff1 fs2 fc0 sc0 ls0 ws0">SYSTEM CLOCK GENERATORs</div><div class="t m0 xe h4 y46 ff1 fs2 fc0 sc0 ls0 ws0">T1040 CORE POWER CONVERTOR</div><div class="t m0 xe h4 y47 ff1 fs2 fc0 sc0 ls0 ws0">SYSTEM POWER CONVERTORs</div><div class="t m0 xe h4 y48 ff1 fs2 fc0 sc0 ls0 ws0">SYSTEM POWER INPUT</div><div class="t m0 xc h4 y49 ff1 fs2 fc0 sc0 ls0 ws0">31</div><div class="t m0 xc h4 y48 ff1 fs2 fc0 sc0 ls0 ws0">32</div><div class="t m0 xe h4 y49 ff1 fs2 fc0 sc0 ls0 ws0">SYSTEM POWER SWITCHs</div><div class="t m0 xc h4 y4a ff1 fs2 fc0 sc0 ls0 ws0">33</div><div class="t m0 xe h4 y4b ff1 fs2 fc0 sc0 ls0 ws0">SERDES MUX/DEMUX SWITCHs</div><div class="t m0 xc h4 y4c ff1 fs2 fc0 sc0 ls0 ws0">34<span class="_ _4"> </span>CHANGE LIST</div><div class="t m0 xe h4 y4d ff1 fs2 fc0 sc0 ls0 ws0">SYSTEM CLOCK GENERATORs (cont.)</div><div class="t m0 x11 h7 y4e ff1 fs5 fc1 sc0 ls0 ws0">All information is subject to change without notice.</div><div class="t m0 x11 h7 y4f ff1 fs5 fc1 sc0 ls0 ws0">No warranty, expressed or applied, is made as to the</div><div class="t m0 x11 h7 y50 ff1 fs5 fc1 sc0 ls0 ws0">accuracy of the information contained herein. This</div><div class="t m0 x11 h7 y51 ff1 fs5 fc1 sc0 ls0 ws0">schematic is provided for reference purposes only.</div><div class="t m0 x11 h7 y52 ff1 fs5 fc1 sc0 ls0 ws0">Contact your Freescale representative to obtain the</div><div class="t m0 x11 h7 y53 ff1 fs5 fc1 sc0 ls0 ws0">latest information on this product.</div><div class="t m0 x8 h4 y54 ff1 fs2 fc0 sc0 ls0 ws0">V1.0<span class="_ _5"> </span>2013/10<span class="_ _6"> </span>Released to Manufacturing</div><div class="t m0 x8 h4 y55 ff1 fs2 fc0 sc0 ls0 ws0">V2.0<span class="_ _5"> </span>2014/01</div><div class="t m0 xa h8 y56 ff1 fs6 fc0 sc0 ls0 ws0">Add SD_REFCLK1_SEL to select SerDes PLL1 input clock frequency</div><div class="t m0 xa h8 y57 ff1 fs6 fc0 sc0 ls0 ws0">Change the direction of the battery holder</div><div class="t m1 x12 h9 y58 ff1 fs7 fc0 sc0 ls0 ws0">Title</div><div class="t m1 x13 h9 y59 ff1 fs7 fc0 sc0 ls0 ws0">Size<span class="_ _7"> </span>Document Number<span class="_ _8"> </span>Rev</div><div class="t m1 x12 h9 y5a ff1 fs7 fc0 sc0 ls0 ws0">Date:<span class="_ _9"> </span>Sheet</div><div class="t m1 x14 h9 y5b ff1 fs7 fc0 sc0 ls0 ws0">of</div><div class="t m1 x15 h9 y5c ff1 fs7 fc0 sc0 ls0 ws0">Design Engineer</div><div class="t m1 x16 h9 y5d ff1 fs7 fc0 sc0 ls0 ws0">&lt;Doc&gt;<span class="_ _a"> </span>A</div><div class="t m2 x16 ha y5e ff3 fs7 fc0 sc0 ls0 ws0">T1040RDB</div><div class="t m1 x12 h9 y5d ff1 fs7 fc0 sc0 ls0 ws0">B</div><div class="t m1 x17 h9 y5f ff1 fs7 fc0 sc0 ls1 ws0">13<span class="_ _b"></span>4<span class="_ _c"></span><span class="ls0">Thursday, January 16, 2014</span></div><div class="t m1 x18 hb y5d ff4 fs7 fc0 sc0 ls0 ws0">MICETEK</div><div class="t m1 x12 h9 y60 ff1 fs7 fc0 sc0 ls0 ws0">Title</div><div class="t m1 x13 h9 y61 ff1 fs7 fc0 sc0 ls0 ws0">Size<span class="_ _7"> </span>Document Number<span class="_ _8"> </span>Rev</div><div class="t m1 x12 h9 y62 ff1 fs7 fc0 sc0 ls0 ws0">Date:<span class="_ _9"> </span>Sheet</div><div class="t m1 x14 h9 y5b ff1 fs7 fc0 sc0 ls0 ws0">of</div><div class="t m1 x15 h9 y5c ff1 fs7 fc0 sc0 ls0 ws0">Design Engineer</div><div class="t m1 x16 h9 y5d ff1 fs7 fc0 sc0 ls0 ws0">&lt;Doc&gt;<span class="_ _a"> </span>A</div><div class="t m2 x16 ha y5e ff3 fs7 fc0 sc0 ls0 ws0">T1040RDB</div><div class="t m1 x12 h9 y5d ff1 fs7 fc0 sc0 ls0 ws0">B</div><div class="t m1 x17 h9 y5f ff1 fs7 fc0 sc0 ls1 ws0">13<span class="_ _b"></span>4<span class="_ _c"></span><span class="ls0">Thursday, January 16, 2014</span></div><div class="t m1 x18 hb y5d ff4 fs7 fc0 sc0 ls0 ws0">MICETEK</div><div class="t m1 x12 h9 y60 ff1 fs7 fc0 sc0 ls0 ws0">Title</div><div class="t m1 x13 h9 y61 ff1 fs7 fc0 sc0 ls0 ws0">Size<span class="_ _7"> </span>Document Number<span class="_ _8"> </span>Rev</div><div class="t m1 x12 h9 y62 ff1 fs7 fc0 sc0 ls0 ws0">Date:<span class="_ _9"> </span>Sheet</div><div class="t m1 x14 h9 y5b ff1 fs7 fc0 sc0 ls0 ws0">of</div><div class="t m1 x15 h9 y5c ff1 fs7 fc0 sc0 ls0 ws0">Design Engineer</div><div class="t m1 x16 h9 y5d ff1 fs7 fc0 sc0 ls0 ws0">&lt;Doc&gt;<span class="_ _a"> </span>A</div><div class="t m2 x16 ha y5e ff3 fs7 fc0 sc0 ls0 ws0">T1040RDB</div><div class="t m1 x12 h9 y5d ff1 fs7 fc0 sc0 ls0 ws0">B</div><div class="t m1 x17 h9 y5f ff1 fs7 fc0 sc0 ls1 ws0">13<span class="_ _b"></span>4<span class="_ _c"></span><span class="ls0">Thursday, January 16, 2014</span></div><div class="t m1 x18 hb y5d ff4 fs7 fc0 sc0 ls0 ws0">MICETEK</div></div><div class="pi" data-data='{"ctm":[0.000000,-1.140143,1.140143,0.000000,0.000000,678.635629]}'></div></div> </body> </html>
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