lpc2364.rar_lpc2364_arm lpc2364_微处理器开发_嵌入式/单片机/硬件编程下载-pudn.com

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">1.<span class="_ _0"> </span>General description</div><div class="t m0 x2 h3 y2 ff2 fs1 fc1 sc0 ls0 ws0">The<span class="_ _1"> </span>LPC2364/66/68<span class="_ _1"> </span>microcontrollers<span class="_ _1"> </span>are<span class="_ _1"> </span>based<span class="_ _1"> </span>on<span class="_ _1"> </span>a<span class="_ _1"> </span>16-bit/32-bit<span class="_ _1"> </span>ARM7TDMI-S<span class="_ _1"> </span>CPU<span class="_ _1"> </span>with</div><div class="t m0 x2 h3 y3 ff2 fs1 fc1 sc0 ls0 ws0">real-time emulation that combines the microcontroller with up to 512<span class="_"> </span>kB of embedded</div><div class="t m0 x2 h3 y4 ff2 fs1 fc1 sc0 ls0 ws0">high-speed ﬂash memor<span class="_ _2"></span>y<span class="_ _3"></span>. A 128-bit wide memor<span class="_ _2"></span>y interf<span class="_ _4"></span>ace and a unique accelerator</div><div class="t m0 x2 h3 y5 ff2 fs1 fc1 sc0 ls0 ws0">architecture enable 32-bit code e<span class="_ _4"></span>x<span class="_ _4"></span>ecution at the maxim<span class="_ _4"></span>um clock r<span class="_ _4"></span>ate. F<span class="_ _4"></span>or critical</div><div class="t m0 x2 h3 y6 ff2 fs1 fc1 sc0 ls0 ws0">perf<span class="_ _4"></span>ormance<span class="_"> </span>in<span class="_ _1"> </span>interrupt<span class="_ _1"> </span>ser<span class="_ _2"></span>vice<span class="_ _1"> </span>routines<span class="_"> </span>and<span class="_ _1"> </span>DSP<span class="_ _1"> </span>algorithms,<span class="_ _1"> </span>this<span class="_ _1"> </span>increases<span class="_ _1"> </span>performance</div><div class="t m0 x2 h3 y7 ff2 fs1 fc1 sc0 ls0 ws0">up to 30<span class="_"> </span>% ov<span class="_ _4"></span>er Thumb mode<span class="_ _4"></span>. F<span class="_ _4"></span>or critical code size applications, the alternative 16-bit</div><div class="t m0 x2 h3 y8 ff2 fs1 fc1 sc0 ls0 ws0">Thumb mode reduces code by more than 30<span class="_"> </span>% with minimal perf<span class="_ _4"></span>ormance penalty<span class="_ _3"></span>.</div><div class="t m0 x2 h3 y9 ff2 fs1 fc1 sc0 ls0 ws0">The LPC2364/66/68 are ideal f<span class="_ _4"></span>or multi-purpose ser<span class="_ _2"></span>ial communication applications. The<span class="_ _4"></span>y</div><div class="t m0 x2 h3 ya ff2 fs1 fc1 sc0 ls0 ws0">incor<span class="_ _2"></span>porate a 10/100 Ethernet Media Access Controller (MAC), USB full speed de<span class="_ _4"></span>vice</div><div class="t m0 x2 h3 yb ff2 fs1 fc1 sc0 ls0 ws0">with 4<span class="_"> </span>kB of endpoint RAM, f<span class="_ _4"></span>our U<span class="_ _4"></span>AR<span class="_ _4"></span>Ts<span class="_ _4"></span>, two CAN channels, an SPI interf<span class="_ _4"></span>ace<span class="_ _4"></span>, two</div><div class="t m0 x2 h3 yc ff2 fs1 fc1 sc0 ls0 ws0">Synchronous Serial P<span class="_ _4"></span>or<span class="_ _2"></span>ts (SSP), three I</div><div class="t m0 x3 h4 yd ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x4 h3 yc ff2 fs1 fc1 sc0 ls0 ws0">C interf<span class="_ _4"></span>aces, and an I</div><div class="t m0 x5 h4 yd ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x6 h3 yc ff2 fs1 fc1 sc0 ls0 ws0">S interf<span class="_ _4"></span>ace. This b<span class="_ _4"></span>lend of</div><div class="t m0 x2 h3 ye ff2 fs1 fc1 sc0 ls0 ws0">serial communications interfaces combined with an on-chip 4<span class="_"> </span>MHz internal oscillator<span class="_ _4"></span>,</div><div class="t m0 x2 h3 yf ff2 fs1 fc1 sc0 ls0 ws0">SRAM of up to 32 kB, 16<span class="_"> </span>kB SRAM f<span class="_ _4"></span>or Ethernet, 8<span class="_"> </span>kB SRAM for USB and gener<span class="_ _4"></span>al</div><div class="t m0 x2 h3 y10 ff2 fs1 fc1 sc0 ls0 ws0">pur<span class="_ _2"></span>pose use, together with 2<span class="_"> </span>kB battery powered SRAM mak<span class="_ _4"></span>e these de<span class="_ _4"></span>vices v<span class="_ _4"></span>er<span class="_ _2"></span>y well</div><div class="t m0 x2 h3 y11 ff2 fs1 fc1 sc0 ls0 ws0">suited f<span class="_ _4"></span>or communication gate<span class="_ _4"></span>wa<span class="_ _4"></span>ys and protocol con<span class="_ _4"></span>v<span class="_ _4"></span>er<span class="_ _2"></span>ters. V<span class="_ _3"></span>ar<span class="_ _2"></span>ious 32-bit timers, an</div><div class="t m0 x2 h3 y12 ff2 fs1 fc1 sc0 ls0 ws0">improv<span class="_ _4"></span>ed 10-bit ADC<span class="_ _4"></span>, 10-bit D<span class="_ _4"></span>A<span class="_ _4"></span>C<span class="_ _4"></span>, one PWM unit, a CAN control unit, and up to 70 f<span class="_ _4"></span>ast</div><div class="t m0 x2 h3 y13 ff2 fs1 fc1 sc0 ls0 ws0">GPIO lines with up to 12 edge or le<span class="_ _4"></span>vel sensitiv<span class="_ _4"></span>e e<span class="_ _4"></span>xternal interrupt pins make these</div><div class="t m0 x2 h3 y14 ff2 fs1 fc1 sc0 ls0 ws0">microcontrollers par<span class="_ _2"></span>ticular<span class="_ _2"></span>ly suitable f<span class="_ _4"></span>or industrial control and medical systems.</div><div class="t m0 x1 h2 y15 ff1 fs0 fc0 sc0 ls0 ws0">2.<span class="_ _0"> </span>Features</div><div class="t m0 x2 h3 y16 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">ARM7TDMI-S processor<span class="_ _4"></span>, running at up to 72<span class="_"> </span>MHz.</span></div><div class="t m0 x2 h3 y17 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Up to 512<span class="_"> </span>kB on-chip ﬂash program memory with In-System Programming (ISP) and</span></div><div class="t m0 x7 h3 y18 ff2 fs1 fc1 sc0 ls0 ws0">In-Application Programming (IAP) capabilities<span class="_ _4"></span>. Flash program memory is on the ARM</div><div class="t m0 x7 h3 y19 ff2 fs1 fc1 sc0 ls0 ws0">local bus f<span class="_ _4"></span>or high perf<span class="_ _4"></span>ormance CPU access.</div><div class="t m0 x2 h3 y1a ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">8/32<span class="_"> </span>kB of SRAM on the ARM local bus f<span class="_ _4"></span>or high perf<span class="_ _4"></span>ormance CPU access.</span></div><div class="t m0 x2 h3 y1b ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">16<span class="_"> </span>kB SRAM f<span class="_ _4"></span>or Ethernet interface. Can also be used as gener<span class="_ _4"></span>al pur<span class="_ _2"></span>pose SRAM.</span></div><div class="t m0 x2 h3 y1c ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">8<span class="_"> </span>kB SRAM f<span class="_ _4"></span>or general purpose DMA use also accessible by the USB<span class="_ _4"></span>.</span></div><div class="t m0 x2 h3 y1d ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Dual Adv<span class="_ _4"></span>anced High-perf<span class="_ _4"></span>or<span class="_ _2"></span>mance Bus (AHB) system that provides f<span class="_ _4"></span>or sim<span class="_ _4"></span>ultaneous</span></div><div class="t m0 x7 h3 y1e ff2 fs1 fc1 sc0 ls0 ws0">Ethernet DMA, USB DMA, and program ex<span class="_ _6"></span>ecution from on-chip ﬂash with no</div><div class="t m0 x7 h3 y1f ff2 fs1 fc1 sc0 ls0 ws0">contention between those functions. A b<span class="_ _6"></span>us br<span class="_ _2"></span>idge allows the Ethernet DMA to access</div><div class="t m0 x7 h3 y20 ff2 fs1 fc1 sc0 ls0 ws0">the other AHB subsystem.</div><div class="t m0 x2 h3 y21 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Advanced V<span class="_ _3"></span>ectored Interrupt Controller (VIC), suppor<span class="_ _2"></span>ting up to 32 vectored interrupts.</span></div><div class="t m0 x2 h3 y22 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">General<span class="_"> </span>Purpose<span class="_"> </span>AHB<span class="_"> </span>DMA<span class="_"> </span>controller<span class="_"> </span>(GPDMA)<span class="_"> </span>that<span class="_"> </span>can<span class="_"> </span>be<span class="_"> </span>used<span class="_"> </span>with<span class="_"> </span>the<span class="_"> </span>SSP<span class="_ _1"> </span>ser<span class="_ _2"></span>ial</span></div><div class="t m0 x7 h3 y23 ff2 fs1 fc1 sc0 ls0 ws0">interf<span class="_ _6"></span>aces, the I</div><div class="t m0 x8 h4 y24 ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x9 h3 y23 ff2 fs1 fc1 sc0 ls0 ws0">S por<span class="_ _2"></span>t, and the Secure Digital/MultiMediaCard (SD/MMC) card por<span class="_ _2"></span>t,</div><div class="t m0 x7 h3 y25 ff2 fs1 fc1 sc0 ls0 ws0">as well as f<span class="_ _6"></span>or memor<span class="_ _2"></span>y-to-memor<span class="_ _2"></span>y transf<span class="_ _4"></span>ers.</div><div class="t m0 xa h5 y26 ff1 fs3 fc0 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 xa h6 y27 ff1 fs4 fc0 sc0 ls0 ws0">Single-chip 16-bit/32-bit micr<span class="_ _6"></span>ocontroller<span class="_ _6"></span>s; up to 512 kB ﬂash</div><div class="t m0 xa h6 y28 ff1 fs4 fc0 sc0 ls0 ws0">with ISP/IAP<span class="_ _7"></span>, Ethernet, USB 2.0, CAN, and 10-bit ADC/D<span class="_ _6"></span>A<span class="_ _6"></span>C</div><div class="t m0 xa h7 y29 ff1 fs5 fc0 sc0 ls0 ws0">Rev<span class="_ _3"></span>. 02 — 1 October 2007<span class="_ _8"> </span>Preliminary data sheet</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/bg2.jpg"><div class="t m0 x1 h8 y2a ff2 fs6 fc1 sc0 ls0 ws0">LPC2364_66_68_2<span class="_ _9"> </span>© NXP B.V<span class="_ _6"></span>. 2007. All rights reserved.</div><div class="t m0 x1 h9 y2b ff1 fs7 fc0 sc0 ls0 ws0">Preliminary data sheet<span class="_ _a"> </span>Rev<span class="_ _3"></span>. 02 — 1 October 2007<span class="_ _b"> </span>2 of 47</div><div class="t m0 x1 ha y2c ff1 fs8 fc0 sc0 ls0 ws0">NXP Semiconductors</div><div class="t m0 xb hb y2d ff1 fs9 fc0 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 x5 hc y2e ff1 fs1 fc0 sc0 ls0 ws0">Fast comm<span class="_ _6"></span>unication chip</div><div class="t m0 x2 h3 y2f ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Serial interfaces:</span></div><div class="t m0 xc h3 y30 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">Ethernet MAC with associated DMA controller<span class="_ _6"></span>. These functions reside on an</span></div><div class="t m0 xd h3 y31 ff2 fs1 fc1 sc0 ls0 ws0">independent AHB bus<span class="_ _6"></span>.</div><div class="t m0 xc h3 y32 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">USB 2.0 full-speed de<span class="_ _4"></span>vice with on-chip PHY and associated DMA controller<span class="_ _6"></span>.</span></div><div class="t m0 xc h3 y33 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">F<span class="_ _6"></span>our<span class="_"> </span>UAR<span class="_ _6"></span>Ts<span class="_"> </span>with<span class="_"> </span>fractional<span class="_"> </span>baud<span class="_ _1"> </span>rate<span class="_"> </span>generation,<span class="_"> </span>one<span class="_"> </span>with<span class="_"> </span>modem<span class="_ _1"> </span>control<span class="_"> </span>I/O<span class="_ _4"></span>,<span class="_"> </span>one</span></div><div class="t m0 xd h3 y34 ff2 fs1 fc1 sc0 ls0 ws0">with IrD<span class="_ _6"></span>A suppor<span class="_ _2"></span>t, all with FIFO.</div><div class="t m0 xc h3 y35 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">CAN controller with two channels.</span></div><div class="t m0 xc h3 y36 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">SPI controller<span class="_ _6"></span>.</span></div><div class="t m0 xc h3 y37 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">T<span class="_ _3"></span>w<span class="_ _6"></span>o<span class="_"> </span>SSP<span class="_"> </span>controllers,<span class="_"> </span>with<span class="_"> </span>FIFO<span class="_"> </span>and<span class="_"> </span>multi-protocol<span class="_"> </span>capabilities<span class="_ _6"></span>.<span class="_"> </span>One<span class="_"> </span>is<span class="_"> </span>an<span class="_"> </span>alter<span class="_ _2"></span>nate</span></div><div class="t m0 xd h3 y38 ff2 fs1 fc1 sc0 ls0 ws0">f<span class="_ _6"></span>or<span class="_"> </span>the<span class="_"> </span>SPI<span class="_ _1"> </span>por<span class="_ _2"></span>t,<span class="_"> </span>sharing<span class="_"> </span>its<span class="_ _1"> </span>interrupt<span class="_"> </span>and<span class="_ _1"> </span>pins.<span class="_"> </span>These<span class="_ _1"> </span>can<span class="_"> </span>be<span class="_ _1"> </span>used<span class="_"> </span>with<span class="_ _1"> </span>the<span class="_"> </span>GPDMA</div><div class="t m0 xd h3 y39 ff2 fs1 fc1 sc0 ls0 ws0">controller<span class="_ _6"></span>.</div><div class="t m0 xc h3 y3a ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">Three I</span></div><div class="t m0 xe h4 y3b ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 xf h3 y3a ff2 fs1 fc1 sc0 ls0 ws0">C-bus interf<span class="_ _6"></span>aces (one with open-drain and two with standard por<span class="_ _2"></span>t pins).</div><div class="t m0 xc h3 y3c ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">I</span></div><div class="t m0 x10 h4 y3d ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x11 h3 y3c ff2 fs1 fc1 sc0 ls0 ws0">S (Inter-IC Sound) interf<span class="_ _4"></span>ace f<span class="_ _6"></span>or digital audio input or output. It can be used with</div><div class="t m0 xd h3 y3e ff2 fs1 fc1 sc0 ls0 ws0">the GPDMA.</div><div class="t m0 x2 h3 y3f ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Other peripherals:</span></div><div class="t m0 xc h3 y40 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">SD/MMC memor<span class="_ _2"></span>y card interf<span class="_ _6"></span>ace (LPC2368 only).</span></div><div class="t m0 xc h3 y41 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">70 general purpose I/O pins with conﬁgurable pull-up/down resistors<span class="_ _6"></span>.</span></div><div class="t m0 xc h3 ye ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">10-bit ADC with input multiple<span class="_ _6"></span>xing among 6 pins.</span></div><div class="t m0 xc h3 y42 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">10-bit D<span class="_ _6"></span>AC<span class="_ _6"></span>.</span></div><div class="t m0 xc h3 y43 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">F<span class="_ _6"></span>our general pur<span class="_ _2"></span>pose timers/counters with a total of 8 capture inputs and 10</span></div><div class="t m0 xd h3 y44 ff2 fs1 fc1 sc0 ls0 ws0">compare outputs. Each timer b<span class="_ _6"></span>lock has an e<span class="_ _6"></span>xter<span class="_ _2"></span>nal count input.</div><div class="t m0 xc h3 y45 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">One PWM/timer bloc<span class="_ _6"></span>k with suppor<span class="_ _2"></span>t for three-phase motor control. The PWM has</span></div><div class="t m0 xd h3 y46 ff2 fs1 fc1 sc0 ls0 ws0">two e<span class="_ _6"></span>xter<span class="_ _2"></span>nal count inputs.</div><div class="t m0 xc h3 y47 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">Real-Time Clock (R<span class="_ _6"></span>TC) with separate pow<span class="_ _6"></span>er pin, clock source can be the R<span class="_ _4"></span>TC</span></div><div class="t m0 xd h3 y48 ff2 fs1 fc1 sc0 ls0 ws0">oscillator or the APB clock.</div><div class="t m0 xc h3 y49 ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">2<span class="_"> </span>kB<span class="_"> </span>SRAM<span class="_"> </span>po<span class="_ _6"></span>wered<span class="_"> </span>from<span class="_"> </span>the<span class="_"> </span>R<span class="_ _6"></span>TC<span class="_"> </span>pow<span class="_ _4"></span>er<span class="_"> </span>pin,<span class="_"> </span>allo<span class="_ _6"></span>wing<span class="_"> </span>data<span class="_"> </span>to<span class="_"> </span>be<span class="_"> </span>stored<span class="_ _1"> </span>when<span class="_"> </span>the</span></div><div class="t m0 xd h3 y4a ff2 fs1 fc1 sc0 ls0 ws0">rest of the chip is powered off<span class="_ _6"></span>.</div><div class="t m0 xc h3 y4b ff3 fs1 fc0 sc0 ls0 ws0">u<span class="_ _c"> </span><span class="ff2 fc1">W<span class="_ _6"></span>atchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator<span class="_ _6"></span>,</span></div><div class="t m0 xd h3 y4c ff2 fs1 fc1 sc0 ls0 ws0">the R<span class="_ _6"></span>TC oscillator<span class="_ _4"></span>, or the APB clock.</div><div class="t m0 x2 h3 y4d ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Standard ARM test/debug interf<span class="_ _6"></span>ace f<span class="_ _4"></span>or compatibility with existing tools<span class="_ _6"></span>.</span></div><div class="t m0 x2 h3 y4e ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Emulation trace module supports real-time trace.</span></div><div class="t m0 x2 h3 y4f ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Single 3.3<span class="_"> </span>V pow<span class="_ _4"></span>er supply (3.0<span class="_"> </span>V to 3.6<span class="_"> </span>V).</span></div><div class="t m0 x2 h3 y50 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">F<span class="_ _6"></span>our reduced power modes: idle, sleep<span class="_ _6"></span>, power-do<span class="_ _6"></span>wn, and deep power-down.</span></div><div class="t m0 x2 h3 y51 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">F<span class="_ _6"></span>our external interr<span class="_ _2"></span>upt inputs conﬁgurab<span class="_ _4"></span>le as edge/le<span class="_ _4"></span>vel sensitiv<span class="_ _6"></span>e. All pins on POR<span class="_ _6"></span>T0</span></div><div class="t m0 x7 h3 y52 ff2 fs1 fc1 sc0 ls0 ws0">and POR<span class="_ _6"></span>T2 can be used as edge sensitive interrupt sources.</div><div class="t m0 x2 h3 y53 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Processor wak<span class="_ _6"></span>e-up from P<span class="_ _6"></span>ower-down mode via an<span class="_ _6"></span>y interr<span class="_ _2"></span>upt able to operate during</span></div><div class="t m0 x7 h3 y54 ff2 fs1 fc1 sc0 ls0 ws0">P<span class="_ _6"></span>ower-do<span class="_ _6"></span>wn mode (includes external interr<span class="_ _2"></span>upts, R<span class="_ _6"></span>TC interrupt, USB activity<span class="_ _3"></span>, Ether<span class="_ _2"></span>net</div><div class="t m0 x7 h3 y55 ff2 fs1 fc1 sc0 ls0 ws0">wak<span class="_ _6"></span>e-up interr<span class="_ _2"></span>upt).</div><div class="t m0 x2 h3 y56 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">T<span class="_ _3"></span>w<span class="_ _6"></span>o independent power domains allow ﬁne tuning of po<span class="_ _6"></span>wer consumption based on</span></div><div class="t m0 x7 h3 y57 ff2 fs1 fc1 sc0 ls0 ws0">needed f<span class="_ _6"></span>eatures.</div><div class="t m0 x2 h3 y58 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Each peripheral has its own cloc<span class="_ _6"></span>k divider for fur<span class="_ _2"></span>ther power sa<span class="_ _6"></span>ving.</span></div><div class="t m0 x2 h3 y59 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Brownout detect with separate thresholds f<span class="_ _6"></span>or interrupt and forced reset.</span></div><div class="t m0 x2 h3 y5a ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">On-chip pow<span class="_ _4"></span>er-on reset.</span></div><div class="t m0 x2 h3 y5b ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">On-chip cr<span class="_ _2"></span>ystal oscillator with an operating range of 1<span class="_"> </span>MHz to 24<span class="_"> </span>MHz.</span></div><div class="t m0 x2 h3 y5c ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">4<span class="_"> </span>MHz internal RC oscillator tr<span class="_ _2"></span>immed to 1<span class="_"> </span>% accuracy that can optionally be used as</span></div><div class="t m0 x7 h3 y5d ff2 fs1 fc1 sc0 ls0 ws0">the system clock. When used as the CPU cloc<span class="_ _6"></span>k, does not allow CAN and USB to run.</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/bg3.jpg"><div class="t m0 x1 h8 y2a ff2 fs6 fc1 sc0 ls0 ws0">LPC2364_66_68_2<span class="_ _9"> </span>© NXP B.V<span class="_ _6"></span>. 2007. All rights reserved.</div><div class="t m0 x1 h9 y2b ff1 fs7 fc0 sc0 ls0 ws0">Preliminary data sheet<span class="_ _a"> </span>Rev<span class="_ _3"></span>. 02 — 1 October 2007<span class="_ _b"> </span>3 of 47</div><div class="t m0 x1 ha y2c ff1 fs8 fc0 sc0 ls0 ws0">NXP Semiconductors</div><div class="t m0 xb hb y2d ff1 fs9 fc0 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 x5 hc y2e ff1 fs1 fc0 sc0 ls0 ws0">Fast comm<span class="_ _6"></span>unication chip</div><div class="t m0 x2 h3 y2f ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">On-chip PLL allows CPU oper<span class="_ _4"></span>ation up to the maximum CPU rate without the need f<span class="_ _6"></span>or</span></div><div class="t m0 x7 h3 y5e ff2 fs1 fc1 sc0 ls0 ws0">a high frequency cr<span class="_ _2"></span>ystal. Ma<span class="_ _6"></span>y be r<span class="_ _2"></span>un from the main oscillator<span class="_ _6"></span>, the inter<span class="_ _2"></span>nal RC</div><div class="t m0 x7 h3 y5f ff2 fs1 fc1 sc0 ls0 ws0">oscillator<span class="_ _6"></span>, or the R<span class="_ _4"></span>TC oscillator<span class="_ _6"></span>.</div><div class="t m0 x2 h3 y60 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">V<span class="_ _3"></span>ersatile pin function selections allow more possibilities for using on-chip peripheral</span></div><div class="t m0 x7 h3 y61 ff2 fs1 fc1 sc0 ls0 ws0">functions.</div><div class="t m0 x1 h2 y62 ff1 fs0 fc0 sc0 ls0 ws0">3.<span class="_ _0"> </span>Applications</div><div class="t m0 x2 h3 y63 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Industrial control</span></div><div class="t m0 x2 h3 y64 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Medical systems</span></div><div class="t m0 x2 h3 y65 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Protocol conv<span class="_ _6"></span>er<span class="_ _2"></span>ter</span></div><div class="t m0 x2 h3 y66 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Communications</span></div><div class="t m0 x1 h2 y67 ff1 fs0 fc0 sc0 ls0 ws0">4.<span class="_ _0"> </span>Or<span class="_ _4"></span>dering inf<span class="_ _4"></span>ormation</div><div class="t m0 x12 ha y68 ff1 fs8 fc0 sc0 ls0 ws0">4.1<span class="_ _d"> </span>Ordering options</div><div class="t m0 x1 hd y69 ff1 fsa fc0 sc0 ls0 ws0">T<span class="_ _6"></span>ab<span class="_ _4"></span>le 1.<span class="_ _e"> </span>Ordering inf<span class="_ _6"></span>ormation</div><div class="t m0 x13 hd y6a ff1 fsa fc1 sc0 ls0 ws0">T<span class="_ _6"></span>ype number<span class="_ _f"> </span><span class="ls1">Pa<span class="_ _2"></span>ck<span class="_ _2"></span>ag<span class="_ _2"></span>e</span></div><div class="t m0 x14 hd y6b ff1 fsa fc1 sc0 ls0 ws0">Name<span class="_ _10"> </span>Description<span class="_ _11"> </span>V<span class="_ _6"></span>ersion</div><div class="t m0 x13 he y6c ff2 fsa fc1 sc0 ls0 ws0">LPC2364FBD100<span class="_ _12"> </span>LQFP100<span class="_ _13"> </span>plastic low proﬁle quad ﬂat pac<span class="_ _6"></span>kage; 100 leads; body 14<span class="_"> </span><span class="ff4">×</span> 14<span class="_"> </span><span class="ff4">×</span> 1.4 mm<span class="_ _14"> </span>SO<span class="_ _6"></span>T407-1</div><div class="t m0 x13 hf y6d ff2 fsa fc1 sc0 ls0 ws0">LPC2366FBD100</div><div class="t m0 x13 hf y6e ff2 fsa fc1 sc0 ls0 ws0">LPC2368FBD100</div><div class="t m0 x1 hd y6f ff1 fsa fc0 sc0 ls0 ws0">T<span class="_ _6"></span>ab<span class="_ _4"></span>le 2.<span class="_ _e"> </span>Ordering options</div><div class="t m0 x13 hd y70 ff1 fsa fc1 sc0 ls0 ws0">T<span class="_ _6"></span>ype number<span class="_ _15"> </span>Flash</div><div class="t m0 x15 hd y71 ff1 fsa fc1 sc0 ls0 ws0">(kB)</div><div class="t m0 xe hd y70 ff1 fsa fc1 sc0 ls0 ws0">SRAM (kB)<span class="_ _16"> </span>Ether</div><div class="t m0 x16 hd y71 ff1 fsa fc1 sc0 ls0 ws0">net</div><div class="t m0 x17 hd y70 ff1 fsa fc1 sc0 ls0 ws0">USB</div><div class="t m0 x17 hd y71 ff1 fsa fc1 sc0 ls0 ws0">device</div><div class="t m0 x17 hd y72 ff1 fsa fc1 sc0 ls2 ws0">+4<span class="_ _2"></span>k<span class="_ _17"></span>B</div><div class="t m0 x17 hd y73 ff1 fsa fc1 sc0 ls0 ws0">FIFO</div><div class="t m0 x18 hd y70 ff1 fsa fc1 sc0 ls0 ws0">SD/</div><div class="t m0 x18 hd y71 ff1 fsa fc1 sc0 ls0 ws0">MMC</div><div class="t m0 x19 hd y70 ff1 fsa fc1 sc0 ls0 ws0">GP</div><div class="t m0 x19 hd y71 ff1 fsa fc1 sc0 ls0 ws0">DMA</div><div class="t m0 x1a hd y70 ff1 fsa fc1 sc0 ls0 ws0">Channels<span class="_ _18"> </span>T<span class="_ _6"></span>emp</div><div class="t m0 x1b hd y71 ff1 fsa fc1 sc0 ls0 ws0">range</div><div class="t m0 x1c hd y74 ff1 fsa fc1 sc0 ls0 ws0">Local</div><div class="t m0 x1c hd y75 ff1 fsa fc1 sc0 ls3 ws0">bus</div><div class="t m0 x1d hd y74 ff1 fsa fc1 sc0 ls0 ws0">Ethernet</div><div class="t m0 x1d hd y75 ff1 fsa fc1 sc0 ls0 ws0">buff<span class="_ _4"></span>ers</div><div class="t m0 x9 hd y74 ff1 fsa fc1 sc0 ls0 ws0">GP/</div><div class="t m0 x9 hd y75 ff1 fsa fc1 sc0 ls0 ws0">USB</div><div class="t m0 x1e hd y74 ff1 fsa fc1 sc0 ls3 ws0">RTC<span class="_ _5"> </span><span class="ls0">T<span class="_ _6"></span>otal<span class="_ _19"> </span>CAN<span class="_ _1a"> </span>ADC<span class="_ _1a"> </span><span class="ls4">DAC</span></span></div><div class="t m0 x13 he y76 ff2 fsa fc1 sc0 ls0 ws0">LPC2364FBD100<span class="_ _1a"> </span>128<span class="_ _1b"> </span>8<span class="_ _1c"> </span>16<span class="_ _1d"> </span>8<span class="_ _18"> </span>2<span class="_ _15"> </span>34<span class="_ _1e"> </span>RMII<span class="_ _1f"> </span>yes<span class="_ _15"> </span>no<span class="_ _20"> </span>yes<span class="_ _21"> </span>2<span class="_ _15"> </span>6<span class="_ _15"> </span>1<span class="_ _15"> </span><span class="ff4">−</span>40<span class="_"> </span><span class="ff4">°</span>C</div><div class="t m0 x1b hf y77 ff2 fsa fc1 sc0 ls0 ws0">to</div><div class="t m0 x1b he y78 ff2 fsa fc1 sc0 ls0 ws0">+85<span class="_"> </span><span class="ff4">°</span>C</div><div class="t m0 x13 he y79 ff2 fsa fc1 sc0 ls0 ws0">LPC2366FBD100<span class="_ _1a"> </span>256<span class="_ _1b"> </span>32<span class="_ _22"> </span>16<span class="_ _1d"> </span>8<span class="_ _18"> </span>2<span class="_ _15"> </span>58<span class="_ _1e"> </span>RMII<span class="_ _1f"> </span>yes<span class="_ _15"> </span>no<span class="_ _20"> </span>yes<span class="_ _21"> </span>2<span class="_ _15"> </span>6<span class="_ _15"> </span>1<span class="_ _15"> </span><span class="ff4">−</span>40<span class="_"> </span><span class="ff4">°</span>C</div><div class="t m0 x1b hf y7a ff2 fsa fc1 sc0 ls0 ws0">to</div><div class="t m0 x1b he y7b ff2 fsa fc1 sc0 ls0 ws0">+85<span class="_"> </span><span class="ff4">°</span>C</div><div class="t m0 x13 he y7c ff2 fsa fc1 sc0 ls0 ws0">LPC2368FBD100<span class="_ _1a"> </span>512<span class="_ _1b"> </span>32<span class="_ _22"> </span>16<span class="_ _1d"> </span>8<span class="_ _18"> </span>2<span class="_ _15"> </span>58<span class="_ _1e"> </span>RMII<span class="_ _1f"> </span>yes<span class="_ _15"> </span>y<span class="_ _6"></span>es<span class="_ _23"> </span>yes<span class="_ _21"> </span>2<span class="_ _15"> </span>6<span class="_ _15"> </span>1<span class="_ _15"> </span><span class="ff4">−</span>40<span class="_"> </span><span class="ff4">°</span>C</div><div class="t m0 x1b hf y7d ff2 fsa fc1 sc0 ls0 ws0">to</div><div class="t m0 x1b he y7e ff2 fsa fc1 sc0 ls0 ws0">+85<span class="_"> </span><span class="ff4">°</span>C</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/bg4.jpg"><div class="t m0 x1 h8 y2a ff2 fs6 fc1 sc0 ls0 ws0">LPC2364_66_68_2<span class="_ _9"> </span>© NXP B.V<span class="_ _6"></span>. 2007. All rights reserved.</div><div class="t m0 x1 h9 y2b ff1 fs7 fc0 sc0 ls0 ws0">Preliminary data sheet<span class="_ _a"> </span>Rev<span class="_ _3"></span>. 02 — 1 October 2007<span class="_ _b"> </span>4 of 47</div><div class="t m0 x1 ha y2c ff1 fs8 fc0 sc0 ls0 ws0">NXP Semiconductors</div><div class="t m0 xb hb y2d ff1 fs9 fc0 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 x5 hc y2e ff1 fs1 fc0 sc0 ls0 ws0">Fast comm<span class="_ _6"></span>unication chip</div><div class="t m0 x1 h2 y7f ff1 fs0 fc0 sc0 ls0 ws0">5.<span class="_ _0"> </span>Bloc<span class="_ _4"></span>k diagram</div><div class="t m0 x1f h10 y80 ff2 fs7 fc1 sc0 ls0 ws0">(1)<span class="_ _24"> </span>LPC2368 only<span class="_ _3"></span>.</div><div class="t m0 x20 hd y81 ff1 fsa fc0 sc0 ls0 ws0">Fig 1.<span class="_ _25"> </span>LPC2364/66/68 bloc<span class="_ _4"></span>k diagram</div><div class="t m0 x10 h11 y82 ff5 fsb fc1 sc0 ls0 ws0">PWM1</div><div class="t m0 x21 h9 y83 ff6 fs7 fc1 sc0 ls0 ws0">ARM7TDMI-S</div><div class="t m0 x22 h11 y84 ff5 fsb fc1 sc0 ls0 ws0">PLL</div><div class="t m0 x23 h11 y85 ff5 fsb fc1 sc0 ls0 ws0">EINT3 to EINT0</div><div class="t m0 x24 h11 y86 ff5 fsb fc1 sc0 ls0 ws0">FLASH</div><div class="t m0 x25 h11 y87 ff5 fsb fc1 sc0 ls0 ws0">P3, P4</div><div class="t m0 x26 h11 y88 ff5 fsb fc1 sc0 ls0 ws0">P0, P1, P2,</div><div class="t m0 xc h11 y89 ff5 fsb fc1 sc0 ls0 ws0">LEGACY GPI/O</div><div class="t m0 x27 h11 y8a ff5 fsb fc1 sc0 ls0 ws0">52 PINS <span class="_ _6"></span>TO<span class="_ _6"></span>T<span class="_ _6"></span>AL</div><div class="t m0 x28 h11 y8b ff5 fsb fc1 sc0 ls0 ws0">P0, P1</div><div class="t m0 x29 h11 y8c ff5 fsb fc1 sc0 ls0 ws0">SCK, SCK0</div><div class="t m0 x29 h11 y8d ff5 fsb fc1 sc0 ls0 ws0">MOSI, MOSI0</div><div class="t m0 x29 h11 y8e ff5 fsb fc1 sc0 ls0 ws0">SSEL, SSEL1</div><div class="t m0 x29 h11 y8f ff5 fsb fc1 sc0 ls0 ws0">SCK1</div><div class="t m0 x29 h11 y90 ff5 fsb fc1 sc0 ls0 ws0">MOSI1</div><div class="t m0 x29 h11 y91 ff5 fsb fc1 sc0 ls0 ws0">MIS01</div><div class="t m0 x29 h11 y92 ff5 fsb fc1 sc0 ls0 ws0">SSEL1</div><div class="t m0 x29 h11 y93 ff5 fsb fc1 sc0 ls0 ws0">SCL0, SCL1, SCL2</div><div class="t m0 x29 h11 y94 ff5 fsb fc1 sc0 ls0 ws0">I2SRX_CLK</div><div class="t m0 x29 h11 y95 ff5 fsb fc1 sc0 ls0 ws0">I2STX_CLK</div><div class="t m0 x29 h11 y96 ff5 fsb fc1 sc0 ls0 ws0">I2SRX_WS</div><div class="t m0 x29 h11 y97 ff5 fsb fc1 sc0 ls0 ws0">I2STX_WS</div><div class="t m0 x2a h12 y98 ff5 fsb fc1 sc0 ls0 ws0">6 <span class="ff4">×</span> AD0</div><div class="t m0 x2b h11 y99 ff5 fsb fc1 sc0 ls0 ws0">RTCX1</div><div class="t m0 x2b h11 y9a ff5 fsb fc1 sc0 ls0 ws0">RTCX2</div><div class="t m0 x29 h11 y9b ff5 fsb fc1 sc0 ls0 ws0">MCICLK, MCIPWR</div><div class="t m0 x29 h11 y9c ff5 fsb fc1 sc0 ls0 ws0">RXD0, RXD2, RXD3</div><div class="t m0 x29 h11 y9d ff5 fsb fc1 sc0 ls0 ws0">TXD1</div><div class="t m0 x29 h11 y9e ff5 fsb fc1 sc0 ls0 ws0">RXD1</div><div class="t m0 x29 h11 y9f ff5 fsb fc1 sc0 ls0 ws0">RD1, RD2</div><div class="t m0 x29 h11 ya0 ff5 fsb fc1 sc0 ls0 ws1">TD1, TD2</div><div class="t m0 x2c h11 ya1 ff5 fsb fc1 sc0 ls0 ws0">CAN1, CAN2</div><div class="t m0 x29 h12 ya2 ff5 fsb fc1 sc0 ls0 ws0">USB_D+, USB_D<span class="ff4">−</span></div><div class="t m0 x2d h13 ya3 ff5 fsc fc1 sc0 ls0 ws0">XT<span class="_ _3"></span>AL1</div><div class="t m0 x2e h13 ya4 ff5 fsc fc1 sc0 ls0 ws0">TCK<span class="_ _26"> </span>TDO</div><div class="t m0 x2f h11 ya5 ff5 fsb fc1 sc0 ls0 ws0">EXTIN0</div><div class="t m0 x30 h11 ya6 ff5 fsb fc1 sc0 ls0 ws0">XT<span class="_ _3"></span>AL2</div><div class="t m0 x31 h11 ya7 ff5 fsb fc1 sc0 ls0 ws0">RESET<span class="_ _27"></span>TRST</div><div class="t m0 x32 h11 ya8 ff5 fsb fc1 sc0 ls0 ws0">TDI<span class="_ _28"></span>TMS</div><div class="t m0 x33 h11 ya9 ff5 fsb fc1 sc0 ls0 ws0">HIGH-SPEED</div><div class="t m0 x2 h11 yaa ff5 fsb fc1 sc0 ls0 ws0">GPI/O</div><div class="t m0 x34 h11 yab ff5 fsb fc1 sc0 ls0 ws0">70 PINS</div><div class="t m0 x35 h11 yac ff5 fsb fc1 sc0 ls5 ws0">TOT<span class="_ _6"></span>A<span class="_ _2"></span>L</div><div class="t m0 x36 h9 yad ff6 fs7 fc1 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 x37 h11 yae ff5 fsb fc1 sc0 ls0 ws0">8/32 kB</div><div class="t m0 x38 h11 yaf ff5 fsb fc1 sc0 ls0 ws0">SRAM</div><div class="t m0 xf h11 yb0 ff5 fsb fc1 sc0 ls0 ws0">128/256/</div><div class="t m0 x39 h11 yb1 ff5 fsb fc1 sc0 ls0 ws0">512 kB</div><div class="t m0 x39 h11 yb2 ff5 fsb fc1 sc0 ls0 ws0">FLASH</div><div class="t m0 x3a h11 yb3 ff5 fsb fc1 sc0 ls0 ws0">INTERNAL</div><div class="t m0 x1d h11 yb4 ff5 fsb fc1 sc0 ls0 ws0">CONTROLLERS</div><div class="t m0 x3b h11 yb5 ff5 fsb fc1 sc0 ls0 ws0">TEST/DEBUG</div><div class="t m0 x3c h11 yb6 ff5 fsb fc1 sc0 ls0 ws0">INTERF<span class="_ _6"></span>ACE</div><div class="t m1 x16 h11 yb7 ff5 fsb fc1 sc0 ls0 ws0">EMULA<span class="_ _3"></span>TION</div><div class="t m1 x3d h11 yb8 ff5 fsb fc1 sc0 ls0 ws0">TRACE MODULE</div><div class="t m0 x3e h11 yb9 ff5 fsb fc1 sc0 ls0 ws0">trace signals</div><div class="t m0 x3f h11 yba ff5 fsb fc1 sc0 ls0 ws0">AHB</div><div class="t m0 x9 h11 ybb ff5 fsb fc1 sc0 ls0 ws0">BRIDGE</div><div class="t m0 x40 h11 ybc ff5 fsb fc1 sc0 ls0 ws0">AHB</div><div class="t m0 x3e h11 ybd ff5 fsb fc1 sc0 ls0 ws0">BRIDGE</div><div class="t m0 x41 h11 ybe ff5 fsb fc1 sc0 ls0 ws0">ETHERNET</div><div class="t m0 x42 h11 ybf ff5 fsb fc1 sc0 ls0 ws2">MAC WITH</div><div class="t m0 x2 h11 yc0 ff5 fsb fc1 sc0 ls0 ws2">DMA</div><div class="t m0 x43 h11 yc1 ff5 fsb fc1 sc0 ls0 ws0">16 kB</div><div class="t m0 x44 h11 yc2 ff5 fsb fc1 sc0 ls0 ws0">SRAM</div><div class="t m0 x9 h11 yc3 ff5 fsb fc1 sc0 ls0 ws0">MASTER</div><div class="t m0 x45 h11 yc4 ff5 fsb fc1 sc0 ls0 ws0">PORT</div><div class="t m0 x46 h11 yc3 ff5 fsb fc1 sc0 ls0 ws1">AHB T<span class="_ _4"></span>O</div><div class="t m0 x47 h11 yc4 ff5 fsb fc1 sc0 ls0 ws0">APB BRIDGE</div><div class="t m0 x48 h11 yc3 ff5 fsb fc1 sc0 ls0 ws0">SLA<span class="_ _6"></span>VE</div><div class="t m0 x40 h11 yc4 ff5 fsb fc1 sc0 ls0 ws0">PORT</div><div class="t m0 x49 h11 yc5 ff5 fsb fc1 sc0 ls0 ws0">system</div><div class="t m0 x17 h11 yc6 ff5 fsb fc1 sc0 ls0 ws0">clock</div><div class="t m0 x2d h11 yc7 ff5 fsb fc1 sc0 ls0 ws0">SYSTEM</div><div class="t m0 x4a h11 yc8 ff5 fsb fc1 sc0 ls0 ws0">FUNCTIONS</div><div class="t m0 x4b h11 yc9 ff5 fsb fc1 sc0 ls0 ws0">INTERNAL RC</div><div class="t m0 x4c h11 yca ff5 fsb fc1 sc0 ls0 ws0">OSCILLA<span class="_ _3"></span>TOR</div><div class="t m0 x19 h11 ycb ff5 fsb fc1 sc0 ls0 ws0">V</div><div class="t m0 x4d h14 ycc ff5 fsd fc1 sc0 ls0 ws0">DDA</div><div class="t m0 x4e h11 ycd ff5 fsb fc1 sc0 ls0 ws0">V</div><div class="t m0 x4f h14 yce ff5 fsd fc1 sc0 ls0 ws0">DD(3V3)</div><div class="t m0 x29 h11 ycf ff5 fsb fc1 sc0 ls0 ws0">VREF</div><div class="t m0 x29 h11 yd0 ff5 fsb fc1 sc0 ls0 ws0">V</div><div class="t m0 x50 h14 yd1 ff5 fsd fc1 sc0 ls0 ws0">SSA</div><div class="t m0 x51 h11 yd2 ff5 fsb fc1 sc0 ls0 ws1">, V</div><div class="t m0 x52 h14 yd1 ff5 fsd fc1 sc0 ls0 ws3">SS</div><div class="t m0 x49 h11 yd3 ff5 fsb fc1 sc0 ls0 ws1">VECT<span class="_ _4"></span>ORED</div><div class="t m0 x49 h11 yd4 ff5 fsb fc1 sc0 ls0 ws1">INTERR<span class="_ _4"></span>UPT</div><div class="t m0 x53 h11 yd5 ff5 fsb fc1 sc0 ls0 ws1">CONTROLLER</div><div class="t m0 x54 h11 yd6 ff5 fsb fc1 sc0 ls0 ws0">8 kB</div><div class="t m0 x55 h11 yd7 ff5 fsb fc1 sc0 ls0 ws0">SRAM</div><div class="t m0 x56 h11 yd8 ff5 fsb fc1 sc0 ls0 ws2">USB WITH</div><div class="t m0 x57 h11 yd9 ff5 fsb fc1 sc0 ls0 ws0">4 kB RAM</div><div class="t m0 x56 h11 yda ff5 fsb fc1 sc0 ls0 ws0"> AND DMA</div><div class="t m0 x58 h11 ydb ff5 fsb fc1 sc0 ls0 ws0">GP DMA</div><div class="t m0 x59 h11 ydc ff5 fsb fc1 sc0 ls0 ws0">CONTROLLER</div><div class="t m0 x5a h11 ydd ff5 fsb fc1 sc0 ls0 ws0">I</div><div class="t m0 x5b h14 yde ff5 fsd fc1 sc0 ls0 ws0">2</div><div class="t m0 x2c h11 ydd ff5 fsb fc1 sc0 ls0 ws0">S INTERF<span class="_ _6"></span>ACE</div><div class="t m0 x5c h11 ydf ff5 fsb fc1 sc0 ls0 ws0">SPI, SSP0 INTERF<span class="_ _6"></span>ACE</div><div class="t m0 x29 h11 ye0 ff5 fsb fc1 sc0 ls0 ws0">I2SRX_SD<span class="_ _4"></span>A</div><div class="t m0 x29 h11 ye1 ff5 fsb fc1 sc0 ls0 ws0">I2STX_SD<span class="_ _4"></span>A</div><div class="t m0 x29 h11 ye2 ff5 fsb fc1 sc0 ls0 ws0">MISO<span class="_ _4"></span>, MISO0</div><div class="t m0 x31 h11 ye3 ff5 fsb fc1 sc0 ls0 ws0">SSP1 INTERF<span class="_ _6"></span>ACE</div><div class="t m0 x5a h11 ye4 ff5 fsb fc1 sc0 ls0 ws0">SD/MMC CARD</div><div class="t m0 x5b h11 ye5 ff5 fsb fc1 sc0 ls0 ws0">INTERF<span class="_ _6"></span>ACE</div><div class="t m0 x5d h14 ye6 ff5 fsd fc1 sc0 ls0 ws0">(1)</div><div class="t m0 x29 h11 ye7 ff5 fsb fc1 sc0 ls0 ws0">MCICMD<span class="_ _6"></span>,</div><div class="t m0 x29 h11 ye8 ff5 fsb fc1 sc0 ls0 ws0">MCID<span class="_ _4"></span>A<span class="_ _3"></span>T[3:0]</div><div class="t m0 x29 h11 ye9 ff5 fsb fc1 sc0 ls0 ws1">TXD0, TXD2, TXD3</div><div class="t m0 x5e h11 yea ff5 fsb fc1 sc0 ls0 ws0">U<span class="_ _4"></span>ART0, U<span class="_ _6"></span>ART2, U<span class="_ _6"></span>ART3</div><div class="t m0 x18 h11 yeb ff5 fsb fc1 sc0 ls5 ws0">UA<span class="_ _2"></span>RT<span class="_ _2"></span>1</div><div class="t m0 x29 h11 yec ff5 fsb fc1 sc0 ls0 ws0">DTR1, RTS1</div><div class="t m0 x29 h11 yed ff5 fsb fc1 sc0 ls0 ws0">DSR1, CTS1, DCD1,</div><div class="t m0 x29 h11 yee ff5 fsb fc1 sc0 ls0 ws0">RI1</div><div class="t m0 x5a h11 yef ff5 fsb fc1 sc0 ls0 ws0">I</div><div class="t m0 x5b h14 yf0 ff5 fsd fc1 sc0 ls0 ws0">2</div><div class="t m0 x5f h11 yf1 ff5 fsb fc1 sc0 ls0 ws0">C0, I</div><div class="t m0 x4a h14 yf0 ff5 fsd fc1 sc0 ls0 ws0">2</div><div class="t m0 x60 h11 yf1 ff5 fsb fc1 sc0 ls0 ws0">C1, I</div><div class="t m0 x61 h14 yf0 ff5 fsd fc1 sc0 ls0 ws0">2</div><div class="t m0 x19 h11 yf1 ff5 fsb fc1 sc0 ls0 ws0">C2</div><div class="t m0 x29 h11 yf2 ff5 fsb fc1 sc0 ls0 ws0">SD<span class="_ _4"></span>A0, SD<span class="_ _4"></span>A1, SD<span class="_ _4"></span>A2</div><div class="t m0 x62 h11 yf3 ff5 fsb fc1 sc0 ls0 ws0">EXTERNAL INTERR<span class="_ _4"></span>UPTS</div><div class="t m0 x1c h11 yf4 ff5 fsb fc1 sc0 ls0 ws0">CAPTURE/COMP<span class="_ _3"></span>ARE</div><div class="t m0 x63 h11 yf5 ff5 fsb fc1 sc0 ls0 ws0">TIMER0/TIMER1/</div><div class="t m0 x64 h11 yf6 ff5 fsb fc1 sc0 ls0 ws0">TIMER2/TIMER3</div><div class="t m0 x7 h11 yf7 ff5 fsb fc1 sc0 ls0 ws0">A/D CONVERTER</div><div class="t m0 x7 h11 yf8 ff5 fsb fc1 sc0 ls0 ws0">D/A CONVERTER</div><div class="t m0 x65 h11 yf9 ff5 fsb fc1 sc0 ls0 ws0">2 kB BA<span class="_ _3"></span>TTERY RAM</div><div class="t m0 x66 h11 yfa ff5 fsb fc1 sc0 ls6 ws0">RTC</div><div class="t m0 x42 h11 yfb ff5 fsb fc1 sc0 ls0 ws0">OSCILLA<span class="_ _3"></span>TOR</div><div class="t m0 x67 h11 yfc ff5 fsb fc1 sc0 ls0 ws0">REAL-</div><div class="t m0 x68 h11 yfd ff5 fsb fc1 sc0 ls0 ws0">TIME</div><div class="t m0 x69 h11 yfe ff5 fsb fc1 sc0 ls0 ws0">CLOCK</div><div class="t m0 x65 h11 yff ff5 fsb fc1 sc0 ls0 ws1">W<span class="_ _6"></span>A<span class="_ _6"></span>TCHDOG TIMER</div><div class="t m0 x65 h11 y100 ff5 fsb fc1 sc0 ls0 ws0">SYSTEM CONTROL</div><div class="t m0 x6a h12 y101 ff5 fsb fc1 sc0 ls0 ws0">2 <span class="ff4">× </span>CAP0/CAP1/</div><div class="t m0 x6b h11 y102 ff5 fsb fc1 sc0 ls0 ws0">CAP2/CAP3</div><div class="t m0 x6c h12 y103 ff5 fsb fc1 sc0 ls0 ws0">4 <span class="ff4">×</span> MA<span class="_ _3"></span>T2,</div><div class="t m0 x6d h12 y104 ff5 fsb fc1 sc0 ls0 ws0">2 <span class="ff4">× </span>MA<span class="_ _3"></span>T0/MA<span class="_ _6"></span>T1/</div><div class="t m0 x25 h11 y105 ff5 fsb fc1 sc0 ls0 ws0">MA<span class="_ _3"></span>T3</div><div class="t m0 x26 h12 y106 ff5 fsb fc1 sc0 ls0 ws0">6 <span class="ff4">×</span> PWM1</div><div class="t m0 x6e h12 y107 ff5 fsb fc1 sc0 ls0 ws0">2 <span class="ff4">×</span> PCAP1</div><div class="t m0 x6f h11 y108 ff5 fsb fc1 sc0 ls0 ws0">AOUT</div><div class="t m0 x25 h11 y109 ff5 fsb fc1 sc0 ls0 ws0">VBA<span class="_ _3"></span>T</div><div class="t m0 x70 h11 y10a ff5 fsb fc1 sc0 ls0 ws1">AHB T<span class="_ _4"></span>O</div><div class="t m0 x71 h11 y10b ff5 fsb fc1 sc0 ls0 ws0">APB BRIDGE</div><div class="t m0 x72 h11 y10c ff5 fsb fc1 sc0 ls0 ws0">SRAM</div><div class="t m0 x2b h11 y10d ff5 fsb fc1 sc0 ls0 ws0">RMII(8)</div><div class="t m0 x29 h11 y10e ff5 fsb fc1 sc0 ls0 ws0">V</div><div class="t m0 x50 h14 y10f ff5 fsd fc1 sc0 ls7 ws0">BUS</div><div class="t m0 x29 h11 y110 ff5 fsb fc1 sc0 ls0 ws0">USB_CONNECT</div><div class="t m0 x29 h11 y111 ff5 fsb fc1 sc0 ls0 ws0">USB_UP_LED</div><div class="t m2 x73 h15 y112 ff5 fse fc1 sc0 ls0 ws0">002aac566</div><div class="t m0 x28 h11 y113 ff5 fsb fc1 sc0 ls0 ws0">P0, P2</div><div class="t m0 x1f h11 y114 ff5 fsb fc2 sc0 ls0 ws0">power domain 2</div><div class="t m0 x37 h11 y115 ff5 fsb fc1 sc0 ls0 ws0">AHB2</div><div class="t m0 x60 h11 y116 ff5 fsb fc1 sc0 ls0 ws0">AHB1</div><div class="t m0 x74 h11 y117 ff5 fsb fc1 sc0 ls0 ws0">power domain 2</div><div class="t m0 x29 h11 y118 ff5 fsb fc1 sc0 ls0 ws0">V</div><div class="t m0 x50 h14 y119 ff5 fsd fc1 sc0 ls0 ws0">DD(DCDC)(3V3)</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/bg5.jpg"><div class="t m0 x1 h8 y2a ff2 fs6 fc1 sc0 ls0 ws0">LPC2364_66_68_2<span class="_ _9"> </span>© NXP B.V<span class="_ _6"></span>. 2007. All rights reserved.</div><div class="t m0 x1 h9 y2b ff1 fs7 fc0 sc0 ls0 ws0">Preliminary data sheet<span class="_ _a"> </span>Rev<span class="_ _3"></span>. 02 — 1 October 2007<span class="_ _b"> </span>5 of 47</div><div class="t m0 x1 ha y2c ff1 fs8 fc0 sc0 ls0 ws0">NXP Semiconductors</div><div class="t m0 xb hb y2d ff1 fs9 fc0 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 x5 hc y2e ff1 fs1 fc0 sc0 ls0 ws0">Fast comm<span class="_ _6"></span>unication chip</div><div class="t m0 x1 h2 y7f ff1 fs0 fc0 sc0 ls0 ws0">6.<span class="_ _0"> </span>Pinning inf<span class="_ _4"></span>ormation</div><div class="t m0 x12 ha y11a ff1 fs8 fc0 sc0 ls0 ws0">6.1<span class="_ _d"> </span>Pinning</div><div class="t m0 x12 ha y11b ff1 fs8 fc0 sc0 ls0 ws0">6.2<span class="_ _d"> </span>Pin description</div><div class="t m0 x20 hd y11c ff1 fsa fc0 sc0 ls0 ws0">Fig 2.<span class="_ _25"> </span>LPC2364/66/68 pinning</div><div class="t m0 x3c h9 y11d ff6 fs7 fc1 sc0 ls0 ws0">LPC2364FBD100</div><div class="t m0 x3c h9 y11e ff6 fs7 fc1 sc0 ls0 ws0">LPC2366FBD100</div><div class="t m0 x3c h9 y11f ff6 fs7 fc1 sc0 ls0 ws0">LPC2368FBD100</div><div class="t m0 x75 h11 y120 ff5 fsb fc1 sc0 ls0 ws0">75</div><div class="t m1 x76 h11 y121 ff5 fsb fc1 sc0 ls0 ws0">26</div><div class="t m1 x3 h11 y121 ff5 fsb fc1 sc0 ls0 ws0">50</div><div class="t m1 x76 h11 y122 ff5 fsb fc1 sc0 ls0 ws0">100</div><div class="t m1 x3 h11 y123 ff5 fsb fc1 sc0 ls0 ws0">76</div><div class="t m0 x49 h11 y124 ff5 fsb fc1 sc0 ls0 ws0">51</div><div class="t m0 x8 h11 y120 ff5 fsb fc1 sc0 ls0 ws0">1</div><div class="t m0 x77 h11 y124 ff5 fsb fc1 sc0 ls0 ws0">25</div><div class="t m2 x78 h15 y125 ff5 fse fc1 sc0 ls0 ws0">002aac576</div><div class="t m0 x1 hd y126 ff1 fsa fc0 sc0 ls0 ws0">T<span class="_ _6"></span>ab<span class="_ _4"></span>le 3.<span class="_ _e"> </span>Pin description</div><div class="t m0 x13 hd y127 ff1 fsa fc1 sc0 ls0 ws0">Symbol<span class="_ _29"> </span>Pin<span class="_ _2a"> </span>T<span class="_ _6"></span>ype<span class="_ _2b"> </span>Description</div><div class="t m0 x13 hd y128 ff2 fsa fc1 sc0 ls0 ws0">P0[0] to P0[31]<span class="_ _16"> </span>I/O<span class="_ _2c"> </span><span class="ff1">P<span class="_ _6"></span>or<span class="_ _2"></span>t 0:<span class="ff2"> P<span class="_ _6"></span>or<span class="_ _2"></span>t 0 is a 32-bit I/O por<span class="_ _2d"></span>t with individual direction controls f<span class="_ _4"></span>or each bit. The</span></span></div><div class="t m0 x79 hf y129 ff2 fsa fc1 sc0 ls0 ws0">operation of por<span class="_ _2"></span>t 0 pins depends upon the pin function selected via the Pin Connect</div><div class="t m0 x79 hf y12a ff2 fsa fc1 sc0 ls0 ws0">bloc<span class="_ _6"></span>k. Pins 12, 13, 14, and 31 of this por<span class="_ _2d"></span>t are not av<span class="_ _6"></span>ailable.</div><div class="t m0 x13 hf y12b ff2 fsa fc1 sc0 ls0 ws0">P0[0]/RD1/TXD3/</div><div class="t m0 x13 hf y12c ff2 fsa fc1 sc0 ls0 ws0">SD<span class="_ _6"></span>A1</div><div class="t m0 x7a hf y12b ff2 fsa fc1 sc0 ls0 ws0">46</div><div class="t m0 x41 h16 y12d ff2 fsf fc3 sc0 ls0 ws0">[1]</div><div class="t m0 x7b hd y12e ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">P0[0] —<span class="_"> </span></span>General purpose digital input/output pin.</div><div class="t m0 x7b hd y12f ff2 fsa fc1 sc0 ls0 ws0">I<span class="_ _1c"> </span><span class="ff1">RD1 —<span class="_"> </span></span>CAN1 receiver input.</div><div class="t m0 x7b hd y130 ff2 fsa fc1 sc0 ls0 ws0">O<span class="_ _2e"> </span><span class="ff1">TXD3 —<span class="_"> </span></span>T<span class="_ _3"></span>ransmitter output f<span class="_ _6"></span>or U<span class="_ _4"></span>ART3.</div><div class="t m0 x7b hd y131 ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">SD<span class="_ _6"></span>A1 —<span class="_"> </span><span class="ff2">I</span></span></div><div class="t m0 x45 h16 y132 ff2 fsf fc1 sc0 ls0 ws0">2</div><div class="t m0 x7c hf y133 ff2 fsa fc1 sc0 ls0 ws0">C1 data input/output (this is not an open-drain pin).</div><div class="t m0 x13 hf y134 ff2 fsa fc1 sc0 ls0 ws0">P0[1]/TD1/RXD3/</div><div class="t m0 x13 hf y135 ff2 fsa fc1 sc0 ls0 ws0">SCL1</div><div class="t m0 x7a hf y134 ff2 fsa fc1 sc0 ls0 ws0">47</div><div class="t m0 x41 h16 y136 ff2 fsf fc3 sc0 ls0 ws0">[1]</div><div class="t m0 x7b hd y137 ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">P0[1] —<span class="_"> </span></span>General purpose digital input/output pin.</div><div class="t m0 x7b hd y138 ff2 fsa fc1 sc0 ls0 ws0">O<span class="_ _2e"> </span><span class="ff1">TD1 —<span class="_"> </span></span>CAN1 transmitter output.</div><div class="t m0 x7b hd y139 ff2 fsa fc1 sc0 ls0 ws0">I<span class="_ _1c"> </span><span class="ff1">RXD3 —<span class="_"> </span></span>Receiver input f<span class="_ _6"></span>or UAR<span class="_ _6"></span>T3.</div><div class="t m0 x7b hd y13a ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">SCL1 —<span class="_"> </span></span>I</div><div class="t m0 x45 h16 y13b ff2 fsf fc1 sc0 ls0 ws0">2</div><div class="t m0 x7d hf y13c ff2 fsa fc1 sc0 ls0 ws0">C1 clock input/output (this is not an open-dr<span class="_ _4"></span>ain pin).</div><div class="t m0 x13 hf y13d ff2 fsa fc1 sc0 ls0 ws0">P0[2]/TXD0<span class="_ _10"> </span>98</div><div class="t m0 x41 h16 y13e ff2 fsf fc3 sc0 ls0 ws0">[1]</div><div class="t m0 x7b hd y13f ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">P0[2] —<span class="_"> </span></span>General purpose digital input/output pin.</div><div class="t m0 x7b hd y140 ff2 fsa fc1 sc0 ls0 ws0">O<span class="_ _2e"> </span><span class="ff1">TXD0 —<span class="_"> </span></span>T<span class="_ _3"></span>ransmitter output f<span class="_ _6"></span>or U<span class="_ _4"></span>ART0.</div><div class="t m0 x13 hf y141 ff2 fsa fc1 sc0 ls0 ws0">P0[3]/RXD0<span class="_ _2f"> </span>99</div><div class="t m0 x41 h16 y142 ff2 fsf fc3 sc0 ls0 ws0">[1]</div><div class="t m0 x7b hd y143 ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">P0[3] —<span class="_"> </span></span>General purpose digital input/output pin.</div><div class="t m0 x7b hd y144 ff2 fsa fc1 sc0 ls0 ws0">I<span class="_ _1c"> </span><span class="ff1">RXD0 —<span class="_"> </span></span>Receiver input f<span class="_ _6"></span>or UAR<span class="_ _6"></span>T0.</div><div class="t m0 x13 hf y145 ff2 fsa fc1 sc0 ls0 ws0">P0[4]/</div><div class="t m0 x13 hf y146 ff2 fsa fc1 sc0 ls0 ws0">I2SRX_CLK/</div><div class="t m0 x13 hf y147 ff2 fsa fc1 sc0 ls0 ws0">RD2/CAP2[0]</div><div class="t m0 x7a hf y145 ff2 fsa fc1 sc0 ls0 ws0">81</div><div class="t m0 x41 h16 y148 ff2 fsf fc3 sc0 ls0 ws0">[1]</div><div class="t m0 x7b hd y149 ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">P0[4] —<span class="_"> </span></span>General purpose digital input/output pin.</div><div class="t m0 x7b hd y14a ff2 fsa fc1 sc0 ls0 ws0">I/O<span class="_ _2c"> </span><span class="ff1">I2SRX_CLK —<span class="_"> </span></span>Receiv<span class="_ _6"></span>e Clock. It is driven by the master and receiv<span class="_ _6"></span>ed by the slav<span class="_ _6"></span>e.</div><div class="t m0 x79 hf y14b ff2 fsa fc1 sc0 ls0 ws0">Corresponds to the signal SCK in the</div><div class="t m3 x7e h17 y14c ff2 fs10 fc1 sc0 ls0 ws0">I</div><div class="t m4 x7f h18 y14d ff2 fs11 fc1 sc0 ls0 ws0">2</div><div class="t m3 x80 h17 y14c ff2 fs10 fc1 sc0 ls0 ws0">S-bus speciﬁcation</div><div class="t m0 x81 hf y14c ff2 fsa fc1 sc0 ls0 ws0">.</div><div class="t m0 x7b hd y14e ff2 fsa fc1 sc0 ls0 ws0">I<span class="_ _1c"> </span><span class="ff1">RD2 —<span class="_"> </span></span>CAN2 receiver input.</div><div class="t m0 x7b hd y14f ff2 fsa fc1 sc0 ls0 ws0">I<span class="_ _1c"> </span><span class="ff1">CAP2[0] —<span class="_"> </span></span>Capture input for Timer<span class="_"> </span>2, channel 0.</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m5"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m5"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m5"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m5"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m5"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>