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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/622b3b77ff7f9c46a606ea07/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">1.<span class="_ _0"> </span>General description</div><div class="t m0 x2 h3 y2 ff2 fs1 fc1 sc0 ls0 ws0">The<span class="_ _1"> </span>LPC2364/66/68<span class="_ _1"> </span>microcontrollers<span class="_ _1"> </span>are<span class="_ _1"> </span>based<span class="_ _1"> </span>on<span class="_ _1"> </span>a<span class="_ _1"> </span>16-bit/32-bit<span class="_ _1"> </span>ARM7TDMI-S<span class="_ _1"> </span>CPU<span class="_ _1"> </span>with</div><div class="t m0 x2 h3 y3 ff2 fs1 fc1 sc0 ls0 ws0">real-time emulation that combines the microcontroller with up to 512<span class="_"> </span>kB of embedded</div><div class="t m0 x2 h3 y4 ff2 fs1 fc1 sc0 ls0 ws0">high-speed &#64258;ash memor<span class="_ _2"></span>y<span class="_ _3"></span>. A 128-bit wide memor<span class="_ _2"></span>y interf<span class="_ _4"></span>ace and a unique accelerator</div><div class="t m0 x2 h3 y5 ff2 fs1 fc1 sc0 ls0 ws0">architecture enable 32-bit code e<span class="_ _4"></span>x<span class="_ _4"></span>ecution at the maxim<span class="_ _4"></span>um clock r<span class="_ _4"></span>ate. F<span class="_ _4"></span>or critical</div><div class="t m0 x2 h3 y6 ff2 fs1 fc1 sc0 ls0 ws0">perf<span class="_ _4"></span>ormance<span class="_"> </span>in<span class="_ _1"> </span>interrupt<span class="_ _1"> </span>ser<span class="_ _2"></span>vice<span class="_ _1"> </span>routines<span class="_"> </span>and<span class="_ _1"> </span>DSP<span class="_ _1"> </span>algorithms,<span class="_ _1"> </span>this<span class="_ _1"> </span>increases<span class="_ _1"> </span>performance</div><div class="t m0 x2 h3 y7 ff2 fs1 fc1 sc0 ls0 ws0">up to 30<span class="_"> </span>% ov<span class="_ _4"></span>er Thumb mode<span class="_ _4"></span>. F<span class="_ _4"></span>or critical code size applications, the alternative 16-bit</div><div class="t m0 x2 h3 y8 ff2 fs1 fc1 sc0 ls0 ws0">Thumb mode reduces code by more than 30<span class="_"> </span>% with minimal perf<span class="_ _4"></span>ormance penalty<span class="_ _3"></span>.</div><div class="t m0 x2 h3 y9 ff2 fs1 fc1 sc0 ls0 ws0">The LPC2364/66/68 are ideal f<span class="_ _4"></span>or multi-purpose ser<span class="_ _2"></span>ial communication applications. The<span class="_ _4"></span>y</div><div class="t m0 x2 h3 ya ff2 fs1 fc1 sc0 ls0 ws0">incor<span class="_ _2"></span>porate a 10/100 Ethernet Media Access Controller (MAC), USB full speed de<span class="_ _4"></span>vice</div><div class="t m0 x2 h3 yb ff2 fs1 fc1 sc0 ls0 ws0">with 4<span class="_"> </span>kB of endpoint RAM, f<span class="_ _4"></span>our U<span class="_ _4"></span>AR<span class="_ _4"></span>Ts<span class="_ _4"></span>, two CAN channels, an SPI interf<span class="_ _4"></span>ace<span class="_ _4"></span>, two</div><div class="t m0 x2 h3 yc ff2 fs1 fc1 sc0 ls0 ws0">Synchronous Serial P<span class="_ _4"></span>or<span class="_ _2"></span>ts (SSP), three I</div><div class="t m0 x3 h4 yd ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x4 h3 yc ff2 fs1 fc1 sc0 ls0 ws0">C interf<span class="_ _4"></span>aces, and an I</div><div class="t m0 x5 h4 yd ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x6 h3 yc ff2 fs1 fc1 sc0 ls0 ws0">S interf<span class="_ _4"></span>ace. This b<span class="_ _4"></span>lend of</div><div class="t m0 x2 h3 ye ff2 fs1 fc1 sc0 ls0 ws0">serial communications interfaces combined with an on-chip 4<span class="_"> </span>MHz internal oscillator<span class="_ _4"></span>,</div><div class="t m0 x2 h3 yf ff2 fs1 fc1 sc0 ls0 ws0">SRAM of up to 32 kB, 16<span class="_"> </span>kB SRAM f<span class="_ _4"></span>or Ethernet, 8<span class="_"> </span>kB SRAM for USB and gener<span class="_ _4"></span>al</div><div class="t m0 x2 h3 y10 ff2 fs1 fc1 sc0 ls0 ws0">pur<span class="_ _2"></span>pose use, together with 2<span class="_"> </span>kB battery powered SRAM mak<span class="_ _4"></span>e these de<span class="_ _4"></span>vices v<span class="_ _4"></span>er<span class="_ _2"></span>y well</div><div class="t m0 x2 h3 y11 ff2 fs1 fc1 sc0 ls0 ws0">suited f<span class="_ _4"></span>or communication gate<span class="_ _4"></span>wa<span class="_ _4"></span>ys and protocol con<span class="_ _4"></span>v<span class="_ _4"></span>er<span class="_ _2"></span>ters. V<span class="_ _3"></span>ar<span class="_ _2"></span>ious 32-bit timers, an</div><div class="t m0 x2 h3 y12 ff2 fs1 fc1 sc0 ls0 ws0">improv<span class="_ _4"></span>ed 10-bit ADC<span class="_ _4"></span>, 10-bit D<span class="_ _4"></span>A<span class="_ _4"></span>C<span class="_ _4"></span>, one PWM unit, a CAN control unit, and up to 70 f<span class="_ _4"></span>ast</div><div class="t m0 x2 h3 y13 ff2 fs1 fc1 sc0 ls0 ws0">GPIO lines with up to 12 edge or le<span class="_ _4"></span>vel sensitiv<span class="_ _4"></span>e e<span class="_ _4"></span>xternal interrupt pins make these</div><div class="t m0 x2 h3 y14 ff2 fs1 fc1 sc0 ls0 ws0">microcontrollers par<span class="_ _2"></span>ticular<span class="_ _2"></span>ly suitable f<span class="_ _4"></span>or industrial control and medical systems.</div><div class="t m0 x1 h2 y15 ff1 fs0 fc0 sc0 ls0 ws0">2.<span class="_ _0"> </span>Features</div><div class="t m0 x2 h3 y16 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">ARM7TDMI-S processor<span class="_ _4"></span>, running at up to 72<span class="_"> </span>MHz.</span></div><div class="t m0 x2 h3 y17 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Up to 512<span class="_"> </span>kB on-chip &#64258;ash program memory with In-System Programming (ISP) and</span></div><div class="t m0 x7 h3 y18 ff2 fs1 fc1 sc0 ls0 ws0">In-Application Programming (IAP) capabilities<span class="_ _4"></span>. Flash program memory is on the ARM</div><div class="t m0 x7 h3 y19 ff2 fs1 fc1 sc0 ls0 ws0">local bus f<span class="_ _4"></span>or high perf<span class="_ _4"></span>ormance CPU access.</div><div class="t m0 x2 h3 y1a ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">8/32<span class="_"> </span>kB of SRAM on the ARM local bus f<span class="_ _4"></span>or high perf<span class="_ _4"></span>ormance CPU access.</span></div><div class="t m0 x2 h3 y1b ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">16<span class="_"> </span>kB SRAM f<span class="_ _4"></span>or Ethernet interface. Can also be used as gener<span class="_ _4"></span>al pur<span class="_ _2"></span>pose SRAM.</span></div><div class="t m0 x2 h3 y1c ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">8<span class="_"> </span>kB SRAM f<span class="_ _4"></span>or general purpose DMA use also accessible by the USB<span class="_ _4"></span>.</span></div><div class="t m0 x2 h3 y1d ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Dual Adv<span class="_ _4"></span>anced High-perf<span class="_ _4"></span>or<span class="_ _2"></span>mance Bus (AHB) system that provides f<span class="_ _4"></span>or sim<span class="_ _4"></span>ultaneous</span></div><div class="t m0 x7 h3 y1e ff2 fs1 fc1 sc0 ls0 ws0">Ethernet DMA, USB DMA, and program ex<span class="_ _6"></span>ecution from on-chip &#64258;ash with no</div><div class="t m0 x7 h3 y1f ff2 fs1 fc1 sc0 ls0 ws0">contention between those functions. A b<span class="_ _6"></span>us br<span class="_ _2"></span>idge allows the Ethernet DMA to access</div><div class="t m0 x7 h3 y20 ff2 fs1 fc1 sc0 ls0 ws0">the other AHB subsystem.</div><div class="t m0 x2 h3 y21 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">Advanced V<span class="_ _3"></span>ectored Interrupt Controller (VIC), suppor<span class="_ _2"></span>ting up to 32 vectored interrupts.</span></div><div class="t m0 x2 h3 y22 ff3 fs1 fc0 sc0 ls0 ws0">n<span class="_ _5"> </span><span class="ff2 fc1">General<span class="_"> </span>Purpose<span class="_"> </span>AHB<span class="_"> </span>DMA<span class="_"> </span>controller<span class="_"> </span>(GPDMA)<span class="_"> </span>that<span class="_"> </span>can<span class="_"> </span>be<span class="_"> </span>used<span class="_"> </span>with<span class="_"> </span>the<span class="_"> </span>SSP<span class="_ _1"> </span>ser<span class="_ _2"></span>ial</span></div><div class="t m0 x7 h3 y23 ff2 fs1 fc1 sc0 ls0 ws0">interf<span class="_ _6"></span>aces, the I</div><div class="t m0 x8 h4 y24 ff2 fs2 fc1 sc0 ls0 ws0">2</div><div class="t m0 x9 h3 y23 ff2 fs1 fc1 sc0 ls0 ws0">S por<span class="_ _2"></span>t, and the Secure Digital/MultiMediaCard (SD/MMC) card por<span class="_ _2"></span>t,</div><div class="t m0 x7 h3 y25 ff2 fs1 fc1 sc0 ls0 ws0">as well as f<span class="_ _6"></span>or memor<span class="_ _2"></span>y-to-memor<span class="_ _2"></span>y transf<span class="_ _4"></span>ers.</div><div class="t m0 xa h5 y26 ff1 fs3 fc0 sc0 ls0 ws0">LPC2364/66/68</div><div class="t m0 xa h6 y27 ff1 fs4 fc0 sc0 ls0 ws0">Single-chip 16-bit/32-bit micr<span class="_ _6"></span>ocontroller<span class="_ _6"></span>s; up to 512 kB &#64258;ash</div><div class="t m0 xa h6 y28 ff1 fs4 fc0 sc0 ls0 ws0">with ISP/IAP<span class="_ _7"></span>, Ethernet, USB 2.0, CAN, and 10-bit ADC/D<span class="_ _6"></span>A<span class="_ _6"></span>C</div><div class="t m0 xa h7 y29 ff1 fs5 fc0 sc0 ls0 ws0">Rev<span class="_ _3"></span>. 02 &#8212; 1 October 2007<span class="_ _8"> </span>Preliminary data sheet</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>
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