VRS51L3074_Keil.rar

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this a c program,be careful
VRS51L3074_Keil.rar
  • VRS51L3074_Keil.h
    19.9KB
  • www.pudn.com.txt
    218B
内容介绍
/************************************************************************** * File: VRS51L3074_Keil.h * Version: 2.1 * Target: Keil 猩ision3 C51 compiler * Date: 1/19/2007 *************************************************************************** * * This file provides all of the SFR definitions described in the device * datsheet. * * DO NOT ACCESS REGISTER VALUES NOT ON THIS LIST * Make sure that the page selected contains the SFR being accessed * * Copyright (C) 2007 Ramtron International Corporation * * 猩ision3 Copyright (c) Keil Elektronik GmbH / Keil Software, Inc. * 1995 - 2005 **************************************************************************/ #ifndef __VRS51L3074_KEIL_H__ #define __VRS51L3074_KEIL_H__ // SFRs that can be accessed on either page sfr P0 = 0x80; // Port 0 sfr SP = 0x81; // Stack pointer sfr DPL0 = 0x82; // Data Pointer 0 lower byte sfr DPH0 = 0x83; // Data Pointer 0 upper byte sfr DPL1 = 0x84; // Data Pointer 1 lower byte sfr DPH1 = 0x85; // Data Pointer 1 upper byte sfr DPS = 0x86; // Data Pointer select sfr PCON = 0x87; // Power control sfr INTEN1 = 0x88; // Interrupt enable 1 sfr T0T1CFG = 0x89; // Timer 0 and Timer 1 configuration sfr TL0 = 0x8A; // Timer 0 lower byte sfr TH0 = 0x8B; // Timer 0 upper byte sfr TL1 = 0x8C; // Timer 1 lower byte sfr TH1 = 0x8D; // Timer 1 upper byte sfr TL2 = 0x8E; // Timer 2 lower byte sfr TH2 = 0x8F; // Timer 2 upper byte sfr P1 = 0x90; // Port 1 sfr WDTCFG = 0x91; // Watchdog timer configuration sfr RCAP0L = 0x92; // Reload / Capture for Timer 0: lower byte sfr RCAP0H = 0x93; // Reload / Capture for Timer 0: upper byte sfr RCAP1L = 0x94; // Reload / Capture for Timer 1: lower byte sfr RCAP1H = 0x95; // Reload / Capture for Timer 1: upper byte sfr RCAP2L = 0x96; // Reload / Capture for Timer 2: lower byte sfr RCAP2H = 0x97; // Reload / Capture for Timer 2: upper byte sfr P5 = 0x98; // Port 5 sfr T0T1CLKCFG = 0x99; // Timer 0 and Timer 1 input clock configurations sfr T0CON = 0x9A; // Timer 0 configuration register sfr T1CON = 0x9B; // Timer 1 configuration register sfr T2CON = 0x9C; // Timer 2 configuration register sfr T2CLKCFG = 0x9D; // Timer 2 input clock configuration sfr P2 = 0xA0; // Port 2 sfr INTEN2 = 0xA8; // Interrupt enable 2 sfr P3 = 0xB0; // Port 3 sfr IPINFLAG1 = 0xB8; // Interrupt pin flags 1 sfr PORTCHG = 0xB9; // Interrupt port change sfr P4 = 0xC0; // Port 4 sfr P6 = 0xC8; // Port 6 sfr PSW = 0xD0; // Program Status Word sfr IPININV1 = 0xD6; // Interrupt pin inversion 1 sfr IPININV2 = 0xD7; // Interrupt pin inversion 2 sfr IPINFLAG2 = 0xD8; // Interrupt pin flags 2 sfr XMEMCTRL = 0xD9; // Off-chip external memory control sfr ACC = 0xE0; // Accumulator sfr DEVIOMAP = 0xE1; // Device input/output mapping sfr INTPRI1 = 0xE2; // Interrupt priority configuration 1 sfr INTPRI2 = 0xE3; // Interrupt priority configuration 2 sfr INTSRC1 = 0xE4; // Interrupt source configuration 1 sfr INTSRC2 = 0xE5; // Interrupt source configuration 2 sfr IPINSENS1 = 0xE6; // Interrupt pin sensitivity configuration 1 sfr IPINSENS2 = 0xE7; // Interrupt pin sensitivity configuration 2 sfr GENINTEN = 0xE8; // General interrupt control sfr FPICONFIG = 0xE9; // Flash programming interface configuration sfr FPIADDRL = 0xEA; // Flash programming address lower byte sfr FPIADDRH = 0xEB; // Flash programming address upper byte sfr FPIDATAL = 0xEC; // Flash programming data lower byte sfr FPIDATAH = 0xED; // Flash programming data upper byte sfr FPICLKSPD = 0xEE; // Flash programming clock speed sfr B = 0xF0; // B sfr MPAGE = 0xF1; // External memory page select sfr DEVCLKCFG1 = 0xF2; // Clock configuration 1 sfr DEVCLKCFG2 = 0xF3; // Clock configuration 2 sfr PERIPHEN1 = 0xF4; // Perhipheral enable 1 sfr PERIPHEN2 = 0xF5; // Perhipheral enable 2 sfr DEVMEMCFG = 0xF6; // Memory control sfr PORTINEN = 0xF7; // Port input logic enable
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