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<html><head><title>NASM Manual</title></head> <body><h1 align=center>The Netwide Assembler: NASM</h1> <a href="nasmdoca.html" rel='nofollow' onclick='return false;'>Previous Chapter</a> | <a href="nasmdoc0.html" rel='nofollow' onclick='return false;'>Contents</a> | <a href="nasmdoci.html" rel='nofollow' onclick='return false;'>Index</a> <h2><a name="appendix-B" rel='nofollow' onclick='return false;'>Appendix B: x86 Instruction Reference</a></h2> This appendix provides a complete list of the machine instructions which NASM will assemble, and a short description of the function of each one. It is not intended to be exhaustive documentation on the fine details of the instructions' function, such as which exceptions they can trigger: for such documentation, you should go to Intel's Web site, <a href="http://developer.intel.com/design/Pentium4/manuals/" rel='nofollow' onclick='return false;'><code>http://developer.intel.com/design/Pentium4/manuals/</code></a>. Instead, this appendix is intended primarily to provide documentation on the way the instructions may be used within NASM. For example, looking up <code>LOOP</code> will tell you that NASM allows <code>CX</code> or <code>ECX</code> to be specified as an optional second argument to the <code>LOOP</code> instruction, to enforce which of the two possible counter registers should be used if the default is not the one desired. The instructions are not quite listed in alphabetical order, since groups of instructions with similar functions are lumped together in the same entry. Most of them don't move very far from their alphabetic position because of this. <h3><a name="section-B.1" rel='nofollow' onclick='return false;'>B.1 Key to Operand Specifications</a></h3> The instruction descriptions in this appendix specify their operands using the following notation: <ul> <li>Registers: <code>reg8</code> denotes an 8-bit general purpose register, <code>reg16</code> denotes a 16-bit general purpose register, and <code>reg32</code> a 32-bit one. <code>fpureg</code> denotes one of the eight FPU stack registers, <code>mmxreg</code> denotes one of the eight 64-bit MMX registers, and <code>segreg</code> denotes a segment register. In addition, some registers (such as <code>AL</code>, <code>DX</code> or <code>ECX</code>) may be specified explicitly. <li>Immediate operands: <code>imm</code> denotes a generic immediate operand. <code>imm8</code>, <code>imm16</code> and <code>imm32</code> are used when the operand is intended to be a specific size. For some of these instructions, NASM needs an explicit specifier: for example, <code>ADD ESP,16</code> could be interpreted as either <code>ADD r/m32,imm32</code> or <code>ADD r/m32,imm8</code>. NASM chooses the former by default, and so you must specify <code>ADD ESP,BYTE 16</code> for the latter. <li>Memory references: <code>mem</code> denotes a generic memory reference; <code>mem8</code>, <code>mem16</code>, <code>mem32</code>, <code>mem64</code> and <code>mem80</code> are used when the operand needs to be a specific size. Again, a specifier is needed in some cases: <code>DEC [address]</code> is ambiguous and will be rejected by NASM. You must specify <code>DEC BYTE [address]</code>, <code>DEC WORD [address]</code> or <code>DEC DWORD [address]</code> instead. <li>Restricted memory references: one form of the <code>MOV</code> instruction allows a memory address to be specified without allowing the normal range of register combinations and effective address processing. This is denoted by <code>memoffs8</code>, <code>memoffs16</code> and <code>memoffs32</code>. <li>Register or memory choices: many instructions can accept either a register or a memory reference as an operand. <code>r/m8</code> is a shorthand for <code>reg8/mem8</code>; similarly <code>r/m16</code> and <code>r/m32</code>. <code>r/m64</code> is MMX-related, and is a shorthand for <code>mmxreg/mem64</code>. </ul> <h3><a name="section-B.2" rel='nofollow' onclick='return false;'>B.2 Key to Opcode Descriptions</a></h3> This appendix also provides the opcodes which NASM will generate for each form of each instruction. The opcodes are listed in the following way: <ul> <li>A hex number, such as <code>3F</code>, indicates a fixed byte containing that number. <li>A hex number followed by <code>+r</code>, such as <code>C8+r</code>, indicates that one of the operands to the instruction is a register, and the `register value' of that register should be added to the hex number to produce the generated byte. For example, EDX has register value 2, so the code <code>C8+r</code>, when the register operand is EDX, generates the hex byte <code>CA</code>. Register values for specific registers are given in <a href="#section-B.2.1" rel='nofollow' onclick='return false;'>section B.2.1</a>. <li>A hex number followed by <code>+cc</code>, such as <code>40+cc</code>, indicates that the instruction name has a condition code suffix, and the numeric representation of the condition code should be added to the hex number to produce the generated byte. For example, the code <code>40+cc</code>, when the instruction contains the <code>NE</code> condition, generates the hex byte <code>45</code>. Condition codes and their numeric representations are given in <a href="#section-B.2.2" rel='nofollow' onclick='return false;'>section B.2.2</a>. <li>A slash followed by a digit, such as <code>/2</code>, indicates that one of the operands to the instruction is a memory address or register (denoted <code>mem</code> or <code>r/m</code>, with an optional size). This is to be encoded as an effective address, with a ModR/M byte, an optional SIB byte, and an optional displacement, and the spare (register) field of the ModR/M byte should be the digit given (which will be from 0 to 7, so it fits in three bits). The encoding of effective addresses is given in <a href="#section-B.2.5" rel='nofollow' onclick='return false;'>section B.2.5</a>. <li>The code <code>/r</code> combines the above two: it indicates that one of the operands is a memory address or <code>r/m</code>, and another is a register, and that an effective address should be generated with the spare (register) field in the ModR/M byte being equal to the `register value' of the register operand. The encoding of effective addresses is given in <a href="#section-B.2.5" rel='nofollow' onclick='return false;'>section B.2.5</a>; register values are given in <a href="#section-B.2.1" rel='nofollow' onclick='return false;'>section B.2.1</a>. <li>The codes <code>ib</code>, <code>iw</code> and <code>id</code> indicate that one of the operands to the instruction is an immediate value, and that this is to be encoded as a byte, little-endian word or little-endian doubleword respectively. <li>The codes <code>rb</code>, <code>rw</code> and <code>rd</code> indicate that one of the operands to the instruction is an immediate value, and that the difference between this value and the address of the end of the instruction is to be encoded as a byte, word or doubleword respectively. Where the form <code>rw/rd</code> appears, it indicates that either <code>rw</code> or <code>rd</code> should be used according to whether assembly is being performed in <code>BITS 16</code> or <code>BITS 32</code> state respectively. <li>The codes <code>ow</code> and <code>od</code> indicate that one of the operands to the instru