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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62546aba47503a0a93a89346/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">《电子工程师创新设计必备宝典系列之FPGA开发全攻略》</div><div class="t m0 x1 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">FPGA开发全攻略</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">—</div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls1 ws0">工程师创新设计宝典</div><div class="t m0 x4 h5 y4 ff4 fs3 fc0 sc0 ls0 ws0">上册</div><div class="t m0 x5 h6 y5 ff1 fs4 fc0 sc0 ls0 ws0">基础篇</div><div class="t m0 x6 h7 y6 ff5 fs0 fc0 sc0 ls0 ws0">2009年2月 1.0版</div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62546aba47503a0a93a89346/bg2.jpg"><div class="t m0 x7 h8 y7 ff6 fs5 fc0 sc0 ls0 ws0">2.</div><div class="t m0 x8 h9 y8 ff2 fs6 fc0 sc0 ls0 ws0">FPGA开发全攻略</div><div class="t m2 x9 h9 y8 ff2 fs6 fc0 sc0 ls0 ws0">—</div><div class="t m0 xa ha y9 ff3 fs6 fc0 sc0 ls2 ws0">工程师创新设计宝典</div><div class="t m0 xb hb ya ff4 fs6 fc0 sc0 ls0 ws0">上册<span class="ff1"> 基础篇</span></div><div class="t m0 xc hc yb ff1 fs7 fc0 sc0 ls0 ws0">前言</div><div class="t m0 xd h7 yc ff5 fs0 fc0 sc0 ls3 ws0">2008年，我参加了几次可编程器件供应商举办的技术研讨会，让我留下深刻印象的<span class="_ _0"></span>是</div><div class="t m0 x8 h7 yd ff5 fs0 fc0 sc0 ls4 ws0">参加这些研讨会的工程师人数之多，简直可以用爆满来形容，很多工程师聚精会神地全天听</div><div class="t m0 x8 h7 ye ff5 fs0 fc0 sc0 ls4 ws0">讲，很少出现吃完午饭就闪人的现象，而且工程师们对研讨会上展出的基于可编程器件的通</div><div class="t m0 x8 h7 yf ff5 fs0 fc0 sc0 ls4 ws0">信、消费电子、医疗电子、工业等解决方案也有浓厚的兴趣，这和其他器件研讨会形成了鲜</div><div class="t m0 x8 h7 y10 ff5 fs0 fc0 sc0 ls0 ws0">明的对比。</div><div class="t m0 xd h7 y11 ff5 fs0 fc0 sc0 ls5 ws0">Garnter和iSuppli公布的数据显示：2008年，全球半导体整体销售出现25年以来首次</div><div class="t m0 x8 h7 y12 ff5 fs0 fc0 sc0 ls6 ws0">萎缩现象，但是，可编程器件却还在保持了增长，预计2008年可编程逻辑器件(PLD)市场销</div><div class="t m0 x8 h7 y13 ff5 fs0 fc0 sc0 ls7 ws0">售额增长7.6%，可编程器件的领头羊美国供应商赛灵思公司2008年营业收入预计升6.5%！</div><div class="t m0 x8 h7 y14 ff5 fs0 fc0 sc0 ls4 ws0">在全球经济危机的背景下，这是非常骄人的业绩！也足见可编程器件在应用领域的热度没有</div><div class="t m0 x8 h7 y15 ff5 fs0 fc0 sc0 ls0 ws0">受到经济危机的影响！这可能也解释了为什么那么多工程师对可编程器件感兴趣吧。</div><div class="t m0 xd h7 y16 ff5 fs0 fc0 sc0 ls8 ws0">在与工程师的交流中，我发现，很多工程师非常需要普及以FPGA为代表的可编程器</div><div class="t m0 x8 h7 y17 ff5 fs0 fc0 sc0 ls9 ws0">件的应用开发知识，也有很多工程师苦于进阶无门，缺乏专业、权威性的指导，在Google</div><div class="t m0 x8 h7 y18 ff5 fs0 fc0 sc0 lsa ws0">上搜索后，我发现很少有帮助工程师设计的FPGA电子书，即使有也只是介绍一些概念性的</div><div class="t m0 x8 h7 y19 ff5 fs0 fc0 sc0 lsa ws0">基础知识，缺乏实用性和系统性，于是，我萌生了出版一本指导工程师FPGA应用开发电子</div><div class="t m0 x8 h7 y1a ff5 fs0 fc0 sc0 ls4 ws0">书的想法，而且这个电子书要突出实用性，让大家都可以免费下载，并提供许多技巧和资源</div><div class="t m0 x8 h7 y1b ff5 fs0 fc0 sc0 ls4 ws0">信息，很高兴美国赛灵思公司对这个想法给予了大力支持，赛灵思公司亚太区市场经理张俊</div><div class="t m0 x8 h7 y1c ff5 fs0 fc0 sc0 lsa ws0">伟小姐和高级产品经理梁晓明先生对电子书提出了宝贵的意见，并提供了大量FPGA设计资</div><div class="t m0 x8 h7 y1d ff5 fs0 fc0 sc0 lsa ws0">源，也介绍了一些FPGA设计高手参与了电子书的编撰，很短的时间内，一个电子书项目团</div><div class="t m0 x8 h7 y1e ff5 fs0 fc0 sc0 ls4 ws0">队组建起来，北京邮电大学的研究生田耘先生和赛灵思公司上海办事处的苏同麒先生等人都</div><div class="t m0 x8 h7 y1f ff5 fs0 fc0 sc0 lsb ws0">参与了电子书的编写，他们是有丰富设计经验的<span class="_ _0"></span>高手，在大家的共同努力下，这本凝结着</div><div class="t m0 x8 h7 y20 ff5 fs0 fc0 sc0 lsc ws0">智慧的FPGA电子书终于和大家见面了！我希望这本电子书可以成为对FPGA有兴趣或正在</div><div class="t m0 x8 h7 y21 ff5 fs0 fc0 sc0 lsa ws0">使用FPGA进行开发的工程师的手头设计宝典之一，也希望这个电子书可以对工程师们学习</div><div class="t m0 x8 h7 y22 ff5 fs0 fc0 sc0 ls0 ws0">FPGA开发和进阶有实用的帮助！如果可能，未来我们还将出版后续版本！</div><div class="t m0 xe hd y23 ff4 fs0 fc0 sc0 ls0 ws0">张国斌</div><div class="t m0 xe hd y24 ff4 fs0 fc0 sc0 ls0 ws0">电子书主编</div><div class="t m0 xe hd y25 ff4 fs0 fc0 sc0 ls0 ws0">2009年2月25日</div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62546aba47503a0a93a89346/bg3.jpg"><div class="t m0 x8 h9 y8 ff2 fs6 fc0 sc0 ls0 ws0">FPGA开发全攻略</div><div class="t m2 x9 h9 y8 ff2 fs6 fc0 sc0 ls0 ws0">—</div><div class="t m0 xa ha y9 ff3 fs6 fc0 sc0 ls2 ws0">工程师创新设计宝典</div><div class="t m0 xb hb ya ff4 fs6 fc0 sc0 ls0 ws0">上册<span class="ff1"> 基础篇</span></div><div class="t m0 xf he y26 ff7 fs1 fc0 sc0 ls0 ws0">目 录</div><div class="t m0 x8 hf y27 ff8 fs3 fc0 sc0 ls0 ws0">前言<span class="_ _1"> </span><span class="_ _2"> </span>2</div><div class="t m0 x8 hf y28 ff8 fs3 fc0 sc0 ls0 ws0">第一章、为什么工程师要掌握FPGA开发知识？</div><div class="t m0 x10 hf y29 ff8 fs3 fc0 sc0 ls0 ws0"><span class="_ _3"></span>5</div><div class="t m0 x8 hf y2a ff8 fs3 fc0 sc0 ls0 ws0">第二章、FPGA基本知识与发展趋势</div><div class="t m0 x11 hf y2b ff8 fs3 fc0 sc0 ls0 ws0"><span class="_ _4"> </span>7</div><div class="t m0 x12 h10 y2c ff9 fs0 fc0 sc0 ls0 ws0">2.1 FPGA结构和工作原理<span class="_ _5"> </span> <span class="_ _6"> </span>7</div><div class="t m0 x13 h11 y2d ff9 fs6 fc0 sc0 ls0 ws0">2.1.1 梦想成就伟业<span class="_ _7"> </span> <span class="_ _8"> </span>7</div><div class="t m0 x13 h11 y2e ff9 fs6 fc0 sc0 ls0 ws0">2.1.2 FPGA结构</div><div class="t m0 x11 h11 y2f ff9 fs6 fc0 sc0 ls0 ws0"> <span class="_ _8"> </span>8</div><div class="t m0 x13 h11 y30 ff9 fs6 fc0 sc0 ls0 ws0">2.1.3 软核、硬核以及固核的概念</div><div class="t m0 x11 h11 y31 ff9 fs6 fc0 sc0 lsd ws0"> 1<span class="_ _9"></span><span class="ls0">5</span></div><div class="t m0 x13 h11 y32 ff9 fs6 fc0 sc0 ls0 ws0">2.1.4 从可编程器件发展看FPGA未来趋势</div><div class="t m0 x11 h11 y33 ff9 fs6 fc0 sc0 lsd ws0"> 1<span class="_ _9"></span><span class="ls0">5</span></div><div class="t m0 x8 hf y34 ff8 fs3 fc0 sc0 ls0 ws0">第三章、FPGA主要供应商与产品<span class="_ _a"> </span><span class="lse">1<span class="_ _b"></span><span class="ls0">7</span></span></div><div class="t m0 x13 h11 y35 ff9 fs6 fc0 sc0 ls0 ws0">3.1.1 赛灵思主要产品介绍<span class="_ _c"> </span><span class="lsd"> 1<span class="_ _9"></span><span class="ls0">7</span></span></div><div class="t m0 x8 hf y36 ff8 fs3 fc0 sc0 ls0 ws0">第四章、FPGA开发基本流程<span class="_ _d"> </span><span class="lsf">2<span class="_ _e"></span><span class="ls0">9</span></span></div><div class="t m0 x12 h10 y37 ff9 fs0 fc0 sc0 ls0 ws0">4.1 典型FPGA开发流程与注意事项<span class="_ _f"> </span><span class="ls10"> 2<span class="_"> </span></span>9</div><div class="t m0 x12 h10 y38 ff9 fs0 fc0 sc0 ls0 ws0">4.2 基于FPGA的SOC设计方法</div><div class="t m0 x11 h10 y39 ff9 fs0 fc0 sc0 ls10 ws0"> 3<span class="_"> </span><span class="ls0">2</span></div><div class="t m0 x13 h11 y3a ff9 fs6 fc0 sc0 ls0 ws0">基于FPGA的典型SOC开发流程为 <span class="_ _10"> </span><span class="ls11"> 3<span class="_ _11"></span><span class="ls0">2</span></span></div><div class="t m0 x8 hf y3b ff8 fs3 fc0 sc0 ls0 ws0">第五章、FPGA实战开发技巧<span class="_ _12"> </span><span class="ls12">3<span class="_ _3"></span><span class="ls0">3</span></span></div><div class="t m0 x12 h10 y3c ff9 fs0 fc0 sc0 ls0 ws0">5.1 FPGA器件选型常识<span class="_ _13"> </span><span class="ls10"> 3<span class="_"> </span></span>3</div><div class="t m0 x13 h11 y3d ff9 fs6 fc0 sc0 ls0 ws0">5.1.1器件的供货渠道和开发工具的支持 <span class="_ _14"> </span><span class="ls13"> 3<span class="_ _15"> </span></span>3</div><div class="t m0 x13 h11 y3e ff9 fs6 fc0 sc0 ls0 ws0">5.1.2 器件的硬件资源 </div><div class="t m0 x14 h11 y3f ff9 fs6 fc0 sc0 ls13 ws0"> 3<span class="_ _15"> </span><span class="ls0">3</span></div><div class="t m0 x13 h11 y40 ff9 fs6 fc0 sc0 ls0 ws0">5.1.3 电气接口标准 </div><div class="t m0 x11 h11 y41 ff9 fs6 fc0 sc0 lsd ws0"> 3<span class="_ _9"></span><span class="ls0">4</span></div><div class="t m0 x13 h11 y42 ff9 fs6 fc0 sc0 ls0 ws0">5.1.4 器件的速度等级 </div><div class="t m0 x11 h11 y43 ff9 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"></span>35</div><div class="t m0 x13 h11 y44 ff9 fs6 fc0 sc0 ls0 ws0">5.1.5 器件的温度等级 </div><div class="t m0 x11 h11 y45 ff9 fs6 fc0 sc0 lsd ws0"> 3<span class="_ _9"></span><span class="ls0">5</span></div><div class="t m0 x13 h11 y46 ff9 fs6 fc0 sc0 ls0 ws0">5.1.6 器件的封装 </div><div class="t m0 x14 h11 y47 ff9 fs6 fc0 sc0 ls13 ws0"> 3<span class="_ _15"> </span><span class="ls0">5</span></div><div class="t m0 x13 h11 y48 ff9 fs6 fc0 sc0 ls0 ws0">5.1.7 器件的价格 </div><div class="t m0 x14 h11 y49 ff9 fs6 fc0 sc0 ls13 ws0"> 3<span class="_ _15"> </span><span class="ls0">5</span></div><div class="t m0 x12 h10 y4a ff9 fs0 fc0 sc0 ls0 ws0">5.2 如何进行FPGA设计早期系统规划 <span class="_ _16"> </span><span class="ls10"> 3<span class="_"> </span></span>6</div><div class="t m0 x12 h10 y4b ff9 fs0 fc0 sc0 ls0 ws0">5.3．综合和仿真技巧</div><div class="t m0 x11 h10 y4c ff9 fs0 fc0 sc0 ls10 ws0"> 3<span class="_"> </span><span class="ls0">7</span></div><div class="t m0 x13 h11 y4d ff9 fs6 fc0 sc0 ls0 ws0">5.3.1 综合工具XST的使用<span class="_ _17"> </span><span class="lsd"> 3<span class="_ _9"></span><span class="ls0">7</span></span></div><div class="t m0 x13 h11 y4e ff9 fs6 fc0 sc0 ls0 ws0">5.3.2 基于ISE的仿真</div><div class="t m0 x11 h11 y4f ff9 fs6 fc0 sc0 lsd ws0"> 4<span class="_ _9"></span><span class="ls0">2</span></div><div class="t m0 x13 h11 y50 ff9 fs6 fc0 sc0 ls0 ws0">5.3.3 和FPGA接口相关的设置以及时序分析</div><div class="t m0 x11 h11 y51 ff9 fs6 fc0 sc0 lsd ws0"> 4<span class="_ _9"></span><span class="ls0">5</span></div><div class="t m0 x13 h11 y52 ff9 fs6 fc0 sc0 ls0 ws0">5.3.4 综合高手揭秘XST的11个技巧</div><div class="t m0 x15 h11 y53 ff9 fs6 fc0 sc0 ls14 ws0"> 5<span class="ls0">1</span></div><div class="t m0 x12 h10 y54 ff9 fs0 fc0 sc0 ls0 ws0">5.4 大规模设计带来的综合和布线问题<span class="_ _18"> </span><span class="ls10"> 5<span class="_"> </span></span>2</div><div class="t m0 x12 h10 y55 ff9 fs0 fc0 sc0 ls0 ws0">5.5 FPGA相关电路设计知识</div><div class="t m0 x11 h10 y56 ff9 fs0 fc0 sc0 ls10 ws0"> 5<span class="_"> </span><span class="ls0">4</span></div><a class="l" rel='nofollow' onclick='return false;'><div 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62546aba47503a0a93a89346/bg4.jpg"><div class="t m0 x8 h9 y57 ff2 fs6 fc0 sc0 ls0 ws0">FPGA开发全攻略</div><div class="t m2 x9 h9 y57 ff2 fs6 fc0 sc0 ls0 ws0">—</div><div class="t m0 xa ha y58 ff3 fs6 fc0 sc0 ls2 ws0">工程师创新设计宝典</div><div class="t m0 xb hb y59 ff4 fs6 fc0 sc0 ls0 ws0">上册<span class="ff1"> 基础篇</span></div><div class="t m0 x13 h11 y5a ff9 fs6 fc0 sc0 ls0 ws0">5.5.1 配置电路<span class="_ _19"> </span><span class="lsd"> 5<span class="_ _9"></span><span class="ls0">4</span></span></div><div class="t m0 x13 h11 y5b ff9 fs6 fc0 sc0 ls0 ws0">5.5.2 主串模式——最常用的FPGA配置模式</div><div class="t m0 x11 h11 y5c ff9 fs6 fc0 sc0 lsd ws0"> 5<span class="_ _9"></span><span class="ls0">6</span></div><div class="t m0 x13 h11 y5d ff9 fs6 fc0 sc0 ls0 ws0">5.5.3 SPI串行Flash配置模式</div><div class="t m0 x11 h11 y5e ff9 fs6 fc0 sc0 lsd ws0"> 5<span class="_ _9"></span><span class="ls0">8</span></div><div class="t m0 x13 h11 y5f ff9 fs6 fc0 sc0 ls0 ws0">5.5.4 从串配置模式</div><div class="t m0 x16 h11 y60 ff9 fs6 fc0 sc0 ls15 ws0"> 6<span class="_ _1a"></span><span class="ls0">2</span></div><div class="t m0 x13 h11 y61 ff9 fs6 fc0 sc0 ls0 ws0">5.5.5 JTAG配置模式</div><div class="t m0 x11 h11 y62 ff9 fs6 fc0 sc0 lsd ws0"> 6<span class="_ _9"></span><span class="ls0">3</span></div><div class="t m0 x13 h11 y63 ff9 fs6 fc0 sc0 ls0 ws0">5.5.6 System ACE配置方案</div><div class="t m0 x11 h11 y64 ff9 fs6 fc0 sc0 lsd ws0"> 6<span class="_ _9"></span><span class="ls0">4</span></div><div class="t m0 x12 h10 y65 ff9 fs0 fc0 sc0 ls0 ws0">5.6 大规模设计的调试经验<span class="_ _1b"> </span><span class="ls10"> 6<span class="_"> </span></span>8</div><div class="t m0 x13 h11 y66 ff9 fs6 fc0 sc0 ls0 ws0">5.6.1 ChipScope Pro组件应用实例<span class="_ _1c"> </span><span class="lsd"> 6<span class="_ _9"></span><span class="ls0">8</span></span></div><div class="t m0 x12 h10 y67 ff9 fs0 fc0 sc0 ls0 ws0">5.7 FPGA设计的IP和算法应用<span class="_ _1d"> </span><span class="ls10"> 7<span class="_"> </span></span>4</div><div class="t m0 x13 h11 y68 ff9 fs6 fc0 sc0 ls0 ws0">5.7.1 IP核综述<span class="_ _1e"> </span><span class="lsd"> 7<span class="_ _9"></span><span class="ls0">4</span></span></div><div class="t m0 x13 h11 y69 ff9 fs6 fc0 sc0 ls0 ws0">5.7.2 FFT IP核应用示例</div><div class="t m0 x11 h11 y6a ff9 fs6 fc0 sc0 lsd ws0"> 7<span class="_ _9"></span><span class="ls0">5</span></div><div class="t m0 x12 h10 y6b ff9 fs0 fc0 sc0 ls0 ws0">5.8 赛灵思 FPGA的专用HDL开发技巧<span class="_ _1f"> </span><span class="ls10"> 7<span class="_"> </span></span>9</div><div class="t m0 x13 h11 y6c ff9 fs6 fc0 sc0 ls0 ws0">5.8.1 赛灵思 FPGA的体系结构特点<span class="_ _20"> </span><span class="lsd"> 7<span class="_ _9"></span><span class="ls0">9</span></span></div><div class="t m0 x13 h11 y6d ff9 fs6 fc0 sc0 ls0 ws0">5.8.2 赛灵思 FPGA 芯片专用代码风格</div><div class="t m0 x11 h11 y6e ff9 fs6 fc0 sc0 lsd ws0"> 7<span class="_ _9"></span><span class="ls0">9</span></div><div class="t m0 x8 hf y6f ff8 fs3 fc0 sc0 ls0 ws0">ISE与EDK开发技巧之时序篇<span class="_ _21"> </span><span class="ls16">8<span class="_ _15"></span></span>3</div><div class="t m0 x12 h10 y70 ff9 fs0 fc0 sc0 ls0 ws0">5.10 新一代开发工具ISE Design Suit10.1介绍<span class="_ _22"> </span><span class="ls10"> 8<span class="_"> </span></span>5</div><div class="t m0 x13 h11 y71 ff9 fs6 fc0 sc0 ls0 ws0">5.10.1 ISE Design Suit10.1综述 <span class="_ _23"> </span><span class="lsd"> 8<span class="_ _9"></span><span class="ls0">5</span></span></div><div class="t m0 x13 h11 y72 ff9 fs6 fc0 sc0 ls0 ws0">5.10.2 ISE Design Suit 10.1的创新特性</div><div class="t m0 x11 h11 y73 ff9 fs6 fc0 sc0 lsd ws0"> 8<span class="_ _9"></span><span class="ls0">5</span></div><div class="t m0 x12 h10 y74 ff9 fs0 fc0 sc0 ls0 ws0">5.11 ISE与第三方软件的配合使用技巧<span class="_ _24"> </span><span class="ls10"> 9<span class="_"> </span></span>2</div><div class="t m0 x13 h11 y75 ff9 fs6 fc0 sc0 ls0 ws0">5.11.1 Synplify Pro软件的使用 <span class="_ _25"> </span><span class="ls13"> 9<span class="_ _15"> </span></span>2</div><div class="t m0 x13 h11 y76 ff9 fs6 fc0 sc0 ls0 ws0">5.11.2 ModelSim软件的使用 </div><div class="t m0 x17 h11 y77 ff9 fs6 fc0 sc0 ls17 ws0"> 9<span class="_ _26"></span><span class="ls0">9</span></div><div class="t m0 x13 h11 y78 ff9 fs6 fc0 sc0 ls0 ws0">5.11.3 Synplify Pro、ModelSim和ISE的联合开发流程 </div><div class="t m0 x18 h11 y79 ff9 fs6 fc0 sc0 ls0 ws0"> <span class="_ _15"> </span>104</div><div class="t m0 x13 h11 y7a ff9 fs6 fc0 sc0 ls0 ws0">5.11.4 ISE与MATLAB的联合使用</div><div class="t m0 x19 h11 y7b ff9 fs6 fc0 sc0 ls0 ws0"> <span class="_ _4"> </span>105</div><div class="t m0 x12 h10 y7c ff9 fs0 fc0 sc0 ls0 ws0">5.12 征服FPGA低功耗设计的三个挑战 <span class="_ _27"> </span> <span class="_ _9"></span>108</div><div class="t m0 x12 h10 y7d ff9 fs0 fc0 sc0 ls0 ws0">5.13 高手之路——FPGA设计开发中的进阶路线</div><div class="t m0 x1a h10 y7e ff9 fs0 fc0 sc0 ls0 ws0"> <span class="_"> </span>111</div><div class="t m0 x8 hf y7f ff8 fs3 fc0 sc0 ls0 ws0">附录一、FPGA开发资源总汇<span class="_ _28"> </span><span class="_ _29"></span>112</div><div class="t m0 x8 hf y80 ff8 fs3 fc0 sc0 ls0 ws0">附录二、编委信息与后记</div><div class="t m0 x1b hf y81 ff8 fs3 fc0 sc0 ls0 ws0"><span class="_ _e"></span>113</div><div class="t m0 x8 hf y82 ff8 fs3 fc0 sc0 ls0 ws0">附录三、版权声明</div><div class="t m0 x1b hf y83 ff8 fs3 fc0 sc0 ls0 ws0"><span class="_ _2a"></span>114</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m3"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62546aba47503a0a93a89346/bg5.jpg"><div class="t m0 x7 h8 y84 ff6 fs5 fc0 sc0 ls0 ws0">5.</div><div class="t m0 x8 h9 y57 ff2 fs6 fc0 sc0 ls0 ws0">FPGA开发全攻略</div><div class="t m2 x9 h9 y57 ff2 fs6 fc0 sc0 ls0 ws0">—</div><div class="t m0 xa ha y58 ff3 fs6 fc0 sc0 ls2 ws0">工程师创新设计宝典</div><div class="t m0 xb hb y59 ff4 fs6 fc0 sc0 ls0 ws0">上册<span class="ff1"> 基础篇</span></div><div class="t m0 x1c h12 y85 ff1 fs8 fc0 sc0 ls0 ws0">第一章、为什么工程师要掌握FPGA开发知识？ </div><div class="t m0 x8 h13 y86 ff4 fs6 fc0 sc0 ls0 ws0">作者：张国斌、田耘</div><div class="t m0 x1d h14 y87 ffa fs6 fc0 sc0 ls18 ws0">20<span class="_ _3"></span>08<span class="_ _2b"> </span>年年初，某著名嵌入式系统<span class="_ _2b"> </span>I<span class="_ _3"></span>T<span class="_ _2b"> </span>公司为了帮助其产品售后工程师和在线技术支持工程师更好的理解其</div><div class="t m0 x8 h14 y88 ffa fs6 fc0 sc0 ls19 ws0">产品<span class="_ _3"></span>，举行了<span class="_ _2b"> </span>AS<span class="_ _3"></span>IC<span class="_ _3"></span>/F<span class="_ _3"></span>PG<span class="_ _3"></span>A<span class="_ _2b"> </span>基础专场培训<span class="_ _0"></span>．由于后者因为保密制度而只能接触到板级电路图和<span class="_ _2c"> </span>L<span class="_ _0"></span>A<span class="_ _3"></span>YO<span class="_ _3"></span>UT<span class="_ _3"></span>，同时</div><div class="t m0 x8 h14 y89 ffa fs6 fc0 sc0 ls1a ws0">因<span class="_"> </span>ASI<span class="_ _0"></span>C/FPGA<span class="_ _2b"> </span>都是典型的<span class="_"> </span>SoC<span class="_ _2c"> </span>应用，通常只是将<span class="_"> </span>ASIC/FPGA<span class="_ _2b"> </span>当作黑盒来理解，其猜测性读图造成公司与外部</div><div class="t m0 x8 h14 y8a ffa fs6 fc0 sc0 ls1b ws0">及公司内部大量的无效沟通．<span class="_ _9"></span>培训结束后<span class="_ _2c"> </span>,<span class="_ _2b"> </span>参与者纷纷表示<span class="_ _2c"> </span>ASIC/FPGA<span class="_"> </span>的白盒式剖析极大提高了对产品的理解，</div><div class="t m0 x8 h14 y8b ffa fs6 fc0 sc0 ls1c ws0">有效解决了合作伙伴和客户端理解偏异性问题，参加培训的工程师小<span class="_ _2b"> </span>L<span class="_"> </span>表示<span class="_ _2c"> </span>：<span class="_ _2d"></span>“FPG<span class="_ _0"></span>A<span class="_ _2b"> </span>同时拥有强大的处理功能</div><div class="t m0 x8 h14 y8c ffa fs6 fc0 sc0 ls1d ws0">和完全的设计自由度，以致于它的行业对手<span class="_ _2b"> </span>ASIC<span class="_"> </span>的设计者在做<span class="_ _2c"> </span>wafer <span class="_ _2e"></span>fabrica<span class="_ _0"></span>tion<span class="_ _2b"> </span>之前<span class="_"> </span>,<span class="_ _2c"> </span>也大量使用<span class="_"> </span>FPGA<span class="_ _2b"> </span>来做</div><div class="t m0 x8 h14 y8d ffa fs6 fc0 sc0 ls1b ws0">整个系统的板级仿真，学习<span class="_"> </span>FPGA<span class="_ _2b"> </span>开发知识不但提升了我们的服务质量从个人角度讲也提升了自己的价值。<span class="_ _2f"></span>”</div><div class="t m0 x1d h14 y8e ffa fs6 fc0 sc0 ls1e ws0">实际上，小<span class="_ _2b"> </span>L<span class="_ _2b"> </span>只是中国数十万<span class="_"> </span>F<span class="_ _0"></span>PGA<span class="_ _2c"> </span>开发工程师中一个缩影，目前，随着<span class="_ _2b"> </span>FPGA<span class="_ _2c"> </span>从可编程逻辑芯片升级为</div><div class="t m0 x8 h14 y8f ffa fs6 fc0 sc0 ls1f ws0">可编程系统级芯片，其在电路中的角色已经从最初的逻辑胶合延伸到数字信号处理<span class="_ _3"></span>、接口、高密度运算等更广</div><div class="t m0 x8 h14 y90 ffa fs6 fc0 sc0 ls20 ws0">阔的范围，应用领域也从通信延伸到消费电子<span class="_ _3"></span>、汽车电子、工业控制、医疗电子等更多领域<span class="_ _0"></span>，现在，大批其他</div><div class="t m0 x8 h14 y91 ffa fs6 fc0 sc0 ls21 ws0">领域的工程师也像小<span class="_ _2b"> </span>L<span class="_"> </span>一样加入到<span class="_ _2c"> </span>FPGA<span class="_ _2b"> </span>学习应用大军中。未来，随着<span class="_ _2b"> </span>FPGA<span class="_ _2c"> </span>把更多的硬核如<span class="_"> </span>Po<span class="_ _0"></span>werP<span class="_ _3"></span>C<span class="ffb ls0">™<span class="_ _2b"> </span></span>处理</div><div class="t m0 x8 h14 y92 ffa fs6 fc0 sc0 ls22 ws0">器等集成进来，以及采用新的工艺将存储单元集成<span class="_ _3"></span>，F<span class="_ _3"></span>PGA<span class="_ _2c"> </span>越来越成为一种融合处理、存储<span class="_ _3"></span>、接口于一体的超</div><div class="t m0 x8 h14 y93 ffa fs6 fc0 sc0 ls23 ws0">级芯片，<span class="_ _2f"></span>“F<span class="_ _0"></span>PGA<span class="_ _2b"> </span>会成为一种板级芯片，未来的电子产品可以通过配置<span class="_ _2b"> </span>FPGA<span class="_ _2b"> </span>来实现功能的升级，实际上，某些</div><div class="t m0 x8 h14 y94 ffa fs6 fc0 sc0 ls21 ws0">通信设备厂商已经在尝试这样做了。<span class="_ _2f"></span>”赛灵思公司全球资深副总裁汤立人这样指出<span class="_ _0"></span>。可以想象，未来，F<span class="_ _3"></span>PGA<span class="_ _2b"> </span>开</div><div class="t m0 x8 h14 y95 ffa fs6 fc0 sc0 ls1e ws0">发能力对工程师而言将成为类似<span class="_ _2b"> </span>C<span class="_"> </span>语言的基础能力之一<span class="_ _3"></span>，面对这样的发展趋势，你还能简单地将<span class="_"> </span>F<span class="_ _0"></span>PGA<span class="_ _2c"> </span>当成一</div><div class="t m0 x8 h14 y96 ffa fs6 fc0 sc0 ls1b ws0">种逻辑器件吗？还能对<span class="_"> </span>FPGA<span class="_ _2b"> </span>的发展无动于衷吗？</div><div class="t m0 x8 h15 y97 ff7 fs9 fc0 sc0 ls0 ws0">电子产品设计趋势的变化</div><div class="t m0 x1d h14 y98 ffa fs6 fc0 sc0 ls24 ws0">自电子产品诞生之日起，电子产品开发流程<span class="_ _0"></span>和方法就随着电子元器件的不断演进而变化<span class="_ _0"></span>，从最早的电子管</div><div class="t m0 x8 h14 y99 ffa fs6 fc0 sc0 ls1f ws0">器件到晶体管再到集成电路，工程师在设计产品时<span class="_ _3"></span>，所采用的工具和方法都有所不同，但是总的来说贯穿电子</div><div class="t m0 x8 h14 y9a ffa fs6 fc0 sc0 ls1b ws0">设计的统一思路是<span class="_ _2e"></span>：<span class="_ _30"></span>使用印刷电路板上的分立、现成元件、连接器或<span class="_"> </span>IC<span class="_ _2b"> </span>创建物理平台实现所需要的功能。例如，</div><div class="t m0 x8 h14 y9b ffa fs6 fc0 sc0 ls20 ws0">在<span class="_ _2b"> </span>60<span class="_ _2c"> </span>年代，如果要设计一个收音机，工程师必须通过在<span class="_ _2b"> </span>PC<span class="_ _3"></span>B<span class="_ _31"> </span>板上通过晶体管、电阻<span class="_ _3"></span>、电容、电感、电线<span class="_ _0"></span>、滤</div><div class="t m0 x8 h14 y9c ffa fs6 fc0 sc0 ls1b ws0">波器、二极管等电路搭建出一个物理平台，实现对<span class="_ _2b"> </span>RF<span class="_"> </span>信号的调谐、<span class="_ _3"></span>滤波、放大等，最后实现收音机的功能。集</div><div class="t m0 x8 h14 y9d ffa fs6 fc0 sc0 ls1d ws0">成电路出现以后，一些分立器件被集成到一颗芯片上，但是总的设计思路没有变化，还是要在一个<span class="_ _2b"> </span>PCB<span class="_ _2b"> </span>板上通</div><div class="t m0 x8 h14 y9e ffa fs6 fc0 sc0 ls1b ws0">过无源器件和<span class="_"> </span>IC<span class="_ _2b"> </span>搭建出一个物理平台，<span class="_ _b"></span>实现信号的接收、<span class="_ _b"></span>处理和输出。但是，<span class="_ _b"></span>随着<span class="_"> </span>FPGA<span class="_ _2b"> </span>等可编程器件的诞生，</div><div class="t m0 x8 h14 y9f ffa fs6 fc0 sc0 ls1f ws0">设计思路正发生着微妙的变化——随着更多功能从分立器件移到可编程领域<span class="_ _3"></span>，各种不同的设计流程交汇到了一</div><div class="t m0 x8 h14 ya0 ffa fs6 fc0 sc0 ls1f ws0">起。现在<span class="_ _3"></span>，有效的电子设计是将板卡设计、可编程逻辑设计和软件开发融合在一起，未来，随着<span class="_ _2c"> </span>FPG<span class="_ _3"></span>A<span class="_"> </span>融合处</div><div class="t m0 x8 h14 ya1 ffa fs6 fc0 sc0 ls1f ws0">理、存储于一体<span class="_ _3"></span>，板卡设计将融合进可编程逻辑设计中，电子产品设计将演变为可编程逻辑设计和嵌入式软件</div><div class="t m0 x8 h14 ya2 ffa fs6 fc0 sc0 ls1f ws0">设计，那时<span class="_ _3"></span>，电子设计将更体现一种“软”设计，一种通过开发语言和工具实现的设计，而<span class="_ _2c"> </span>FPG<span class="_ _3"></span>A<span class="_"> </span>将成为这种</div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>
