基于单片机与FPGA的实用信号源的设计_mcu_单片机_其他

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/62ab87daca7ee606dcca86e4/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62ab87daca7ee606dcca86e4/bg1.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x1 h3 y2 ff1 fs0 fc0 sc0 ls0 ws0">附录（系统的原理图和部分源程序）</div><div class="t m0 x2 h4 y3 ff2 fs1 fc0 sc0 ls0 ws0">1 <span class="ff1">系统的原理图</span></div><div class="t m0 x3 h5 y4 ff2 fs2 fc0 sc0 ls0 ws0">1.1<span class="ff1">单片机模块的原理图如附图</span>1.1<span class="ff1">所示</span></div><div class="t m0 x4 h6 y5 ff1 fs3 fc0 sc0 ls0 ws0">附图<span class="ff2">1.1 </span>单片机模块原理图</div><div class="t m0 x5 h5 y6 ff2 fs2 fc0 sc0 ls0 ws0"> 1.2 FPGA<span class="ff1">模块的原理图</span></div><div class="t m0 x5 h7 y7 ff3 fs3 fc0 sc0 ls0 ws0"> </div></div><div class="t m0 x6 h8 y8 ff3 fs4 fc0 sc0 ls0 ws0">1</div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62ab87daca7ee606dcca86e4/bg2.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x5 h6 y9 ff1 fs3 fc0 sc0 ls0 ws0">附图<span class="ff2">1.2 FPGA</span>模块原理图</div><div class="t m0 x7 h4 ya ff2 fs1 fc0 sc0 ls0 ws0">2 FPGA<span class="ff1">中的功能寄存器模块和</span>DDS<span class="ff1">模块</span></div><div class="t m0 x7 h5 yb ff2 fs2 fc0 sc0 ls0 ws0">2.1 <span class="ff1">功能寄存器模块</span></div><div class="t m0 x2 h9 yc ff3 fs3 fc0 sc0 ls0 ws0"> <span class="ff1 fs5">功能寄存器模块由<span class="ff2">8</span>位锁存器、<span class="ff2">8</span>位并入串出的移位寄存器、三位译码器、五个</span></div><div class="t m0 x2 h9 yd ff1 fs5 fc0 sc0 ls0 ws0">功能锁存器、一个与非门组成。由于<span class="ff2">8</span>位锁存器、三位译码器、五个功能锁存器</div><div class="t m0 x2 h9 ye ff1 fs5 fc0 sc0 ls0 ws0">和与非门可以直接调用<span class="ff2">MAX+PL<span class="_ _0"></span>USS II<span class="ff1">的</span>LPM<span class="ff1">库，所以实现比较简单，在此就不</span></span></div><div class="t m0 x2 h9 yf ff1 fs5 fc0 sc0 ls0 ws0">多介绍了。下面主要给出<span class="ff2">8</span>位并入串出移位寄存器。</div><div class="t m0 x5 h9 y10 ff2 fs5 fc0 sc0 ls0 ws0">8<span class="ff1">位并入串出移位寄存器的源程序（</span>SHIFT8<span class="_ _1"></span>_1.VHD<span class="ff1">）</span></div><div class="t m0 x5 h7 y7 ff3 fs3 fc0 sc0 ls0 ws0">LIBRAR<span class="_ _0"></span>Y<span class="_ _1"></span> IEEE;</div><div class="t m0 x5 h7 y11 ff3 fs3 fc0 sc0 ls0 ws0">USE IEEE.STD_LOGIC_1<span class="_ _1"></span>164.ALL;</div><div class="t m0 x5 h7 y12 ff3 fs3 fc0 sc0 ls0 ws0">USE IEEE.STD_LOGIC_UNSIGNED.ALL;</div><div class="t m0 x5 h7 y13 ff3 fs3 fc0 sc0 ls0 ws0">ENTITY<span class="_ _1"></span> SHIFT8_1 IS</div><div class="t m0 x5 h7 y14 ff3 fs3 fc0 sc0 ls0 ws0"> POR<span class="_ _0"></span>T(ALE:IN STD_LOGIC;</div><div class="t m0 x5 h7 y15 ff3 fs3 fc0 sc0 ls0 ws0"> SHIFT<span class="_ _0"></span>:IN STD_LOGIC_VECTOR(7 DOWNT<span class="_ _1"></span>O 0);</div><div class="t m0 x5 h7 y16 ff3 fs3 fc0 sc0 ls0 ws0"> Y<span class="_ _2"></span>:OUT S<span class="_ _1"></span>TD_LOGIC);</div><div class="t m0 x5 h7 y17 ff3 fs3 fc0 sc0 ls0 ws0"> END;</div><div class="t m0 x5 h7 y18 ff3 fs3 fc0 sc0 ls0 ws0"> ARCHITECTURE <span class="_ _0"></span>AR<span class="_ _0"></span>T OF SHIFT8_1 IS</div><div class="t m0 x5 h7 y19 ff3 fs3 fc0 sc0 ls0 ws0"> SIGNAL<span class="_ _1"></span> K:STD_LOGIC_VECT<span class="_ _1"></span>OR(7 DOWNT<span class="_ _1"></span>O 0);</div><div class="t m0 x5 h7 y1a ff3 fs3 fc0 sc0 ls0 ws0"> SIGNAL<span class="_ _1"></span> Q:STD_LOGIC_VECT<span class="_ _1"></span>OR(2 DOWNT<span class="_ _1"></span>O 0);</div><div class="t m0 x5 h7 y1b ff3 fs3 fc0 sc0 ls0 ws0"> BEGIN</div><div class="t m0 x5 h7 y1c ff3 fs3 fc0 sc0 ls0 ws0"> P1:PROCESS(ALE)</div><div class="t m0 x5 h7 y1d ff3 fs3 fc0 sc0 ls0 ws0"> BEGIN</div></div><div class="t m0 x6 h8 y8 ff3 fs4 fc0 sc0 ls0 ws0">2</div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62ab87daca7ee606dcca86e4/bg3.jpg"><div class="c x0 y1 w2 h2"><div class="t m0 x5 h7 y1e ff3 fs3 fc0 sc0 ls0 ws0"> IF <span class="_ _0"></span>ALE'EVENT <span class="_ _0"></span>AND <span class="_ _0"></span>ALE='1' THEN</div><div class="t m0 x5 h7 y1f ff3 fs3 fc0 sc0 ls0 ws0"> Q<=Q+1;</div><div class="t m0 x5 h7 y20 ff3 fs3 fc0 sc0 ls0 ws0"> END IF;</div><div class="t m0 x5 h7 y21 ff3 fs3 fc0 sc0 ls0 ws0"> END PROCESS;</div><div class="t m0 x5 h7 y22 ff3 fs3 fc0 sc0 ls0 ws0"> P2:PROCESS(ALE)</div><div class="t m0 x5 h7 y23 ff3 fs3 fc0 sc0 ls0 ws0"> BEGIN</div><div class="t m0 x5 h7 y24 ff3 fs3 fc0 sc0 ls0 ws0"> IF <span class="_ _0"></span>ALE'EVENT <span class="_ _0"></span>AND <span class="_ _0"></span>ALE='1' THEN</div><div class="t m0 x5 h7 y25 ff3 fs3 fc0 sc0 ls0 ws0"> IF Q>"000" THEN</div><div class="t m0 x5 h7 y26 ff3 fs3 fc0 sc0 ls0 ws0"> K(7 DOWNTO <span class="_ _1"></span>1)<=K(6 DOWNTO 0);</div><div class="t m0 x5 h7 y27 ff3 fs3 fc0 sc0 ls0 ws0"> ELSIF Q="000" THEN</div><div class="t m0 x5 h7 y28 ff3 fs3 fc0 sc0 ls0 ws0"> K<=SHIFT<span class="_ _0"></span>;</div><div class="t m0 x5 h7 y29 ff3 fs3 fc0 sc0 ls0 ws0"> END IF;</div><div class="t m0 x5 h7 y2a ff3 fs3 fc0 sc0 ls0 ws0"> END IF;</div><div class="t m0 x5 h7 y2b ff3 fs3 fc0 sc0 ls0 ws0"> Y<=K(7);</div><div class="t m0 x5 h7 y2c ff3 fs3 fc0 sc0 ls0 ws0"> END PROCESS;</div><div class="t m0 x5 h7 y2d ff3 fs3 fc0 sc0 ls0 ws0"> END; </div><div class="t m0 x2 h5 y2e ff2 fs2 fc0 sc0 ls0 ws0">2.2 DDS<span class="ff1">模块</span></div><div class="t m0 x2 h6 y2f ff3 fs3 fc0 sc0 ls0 ws0"> DDS<span class="ff1">模块由</span>24<span class="ff1">位加法器、</span>12<span class="ff1">位相位累加器、</span>12<span class="ff1">位相位锁存器、</span>12<span class="ff1">位频率控制字加法器、</span></div><div class="t m0 x2 h6 y30 ff3 fs3 fc0 sc0 ls0 ws0">ROM<span class="ff1">查找表、波形选择器和三个八位锁存器组成。由于有些模块可以直接用</span>MAX+PLUSS II</div><div class="t m0 x2 h6 y31 ff1 fs3 fc0 sc0 ls0 ws0">中的<span class="ff3">MegaW<span class="_ _1"></span>izard Plug_I<span class="_ _1"></span>n Manager<span class="ff1">设计，源程序就可以不必自己设计了。下面给出部分的源程</span></span></div><div class="t m0 x2 h6 y32 ff1 fs3 fc0 sc0 ls0 ws0">序。</div><div class="t m0 x2 h9 y33 ff2 fs5 fc0 sc0 ls0 ws0">2.2.1 24<span class="ff1">位加法器的源程序（</span>COUNTER_24.VHD<span class="ff1">）</span></div><div class="t m0 x2 h7 y34 ff3 fs3 fc0 sc0 ls0 ws0">LIBRAR<span class="_ _0"></span>Y<span class="_ _1"></span> IEEE;</div><div class="t m0 x2 h7 y35 ff3 fs3 fc0 sc0 ls0 ws0">USE IEEE.STD_LOGIC_1<span class="_ _1"></span>164.ALL;</div><div class="t m0 x2 h7 y36 ff3 fs3 fc0 sc0 ls0 ws0">USE IEEE.STD_LOGIC_UNSIGNED.ALL;</div><div class="t m0 x2 h7 y37 ff3 fs3 fc0 sc0 ls0 ws0">USE IEEE.STD_LOGIC_ARITH.ALL;</div><div class="t m0 x2 h7 y38 ff3 fs3 fc0 sc0 ls0 ws0">ENTITY<span class="_ _1"></span> COUNTER_24 IS</div><div class="t m0 x2 h7 y39 ff3 fs3 fc0 sc0 ls0 ws0"> POR<span class="_ _0"></span>T(CLOCK:IN STD_LOGIC;</div><div class="t m0 x2 h7 y3a ff3 fs3 fc0 sc0 ls0 ws0"> CLR:IN STD_LOGIC;</div><div class="t m0 x2 h7 y7 ff3 fs3 fc0 sc0 ls0 ws0"> ENA:IN STD_LOGIC; </div><div class="t m0 x2 h7 y11 ff3 fs3 fc0 sc0 ls0 ws0"> FENPIN_WORD:IN STD_LOGIC_VECTOR(2<span class="_ _1"></span>3 DOWNTO 0);</div><div class="t m0 x2 h7 y12 ff3 fs3 fc0 sc0 ls0 ws0"> NEWCLK:OUT STD_LOGIC);</div><div class="t m0 x2 h7 y13 ff3 fs3 fc0 sc0 ls0 ws0">END;</div><div class="t m0 x2 h7 y14 ff3 fs3 fc0 sc0 ls0 ws0">ARCHITECTURE <span class="_ _0"></span>AR<span class="_ _0"></span>T OF COUNTER_24 IS</div><div class="t m0 x2 h7 y15 ff3 fs3 fc0 sc0 ls0 ws0"> SIGNAL<span class="_ _0"></span> <span class="_ _3"></span>Q:STD_LOGIC_VECTOR(2<span class="_ _1"></span>3 DOWNTO 0);</div><div class="t m0 x2 h7 y16 ff3 fs3 fc0 sc0 ls0 ws0"> SIGNAL<span class="_ _0"></span> <span class="_ _3"></span>CK:STD_LOGIC;</div><div class="t m0 x2 h7 y17 ff3 fs3 fc0 sc0 ls0 ws0"> SIGNAL<span class="_ _0"></span> <span class="_ _3"></span>S:STD_LOGIC_VECT<span class="_ _1"></span>OR(23 DOWNTO 0);</div><div class="t m0 x2 h7 y18 ff3 fs3 fc0 sc0 ls0 ws0"> BEGIN</div><div class="t m0 x2 h7 y19 ff3 fs3 fc0 sc0 ls0 ws0"> S<=FENPIN_WORD-1;</div><div class="t m0 x2 h7 y1a ff3 fs3 fc0 sc0 ls0 ws0"> PROCESS(CLOCK,CLR) IS</div><div class="t m0 x2 h7 y1b ff3 fs3 fc0 sc0 ls0 ws0"> BEGIN</div><div class="t m0 x2 h7 y1c ff3 fs3 fc0 sc0 ls0 ws0"> IF CLR='1' THEN</div><div class="t m0 x2 h7 y1d ff3 fs3 fc0 sc0 ls0 ws0"> Q<=(OTHERS=>'0');</div></div><div class="t m0 x6 h8 y8 ff3 fs4 fc0 sc0 ls0 ws0">3</div></div><div class="pi" data-data='{"ctm":[1.611850,0.000000,0.000000,1.611850,0.000000,0.000000]}'></div></div>