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<div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259f2b292dc900e62cf1d7c/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Features</div><div class="t m0 x1 h3 y2 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls2 ws1">High-performance, Low-power A<span class="_ _1"></span>VR</span></div><div class="t m0 x2 h4 y3 ff2 fs3 fc0 sc0 ls3 ws0">® </div><div class="t m0 x3 h5 y2 ff1 fs2 fc0 sc0 ls4 ws2">8-bit Microcontr<span class="_ _1"></span>oller</div><div class="t m0 x1 h3 y4 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls5 ws3">Adv<span class="_ _1"></span>anc<span class="_ _2"></span>ed RISC Arc<span class="_ _3"></span>hitecture</span></div><div class="t m0 x4 h5 y5 ff1 fs2 fc0 sc0 ls6 ws4">–<span class="_ _4"> </span>131 P<span class="_ _1"></span>owerful In<span class="_ _1"></span>structions – Most Single-c<span class="_ _1"></span>lock Cyc<span class="_ _1"></span>le Execution</div><div class="t m0 x4 h5 y6 ff1 fs2 fc0 sc0 ls7 ws5">–<span class="_ _4"> </span>32 x 8 General Purpose W<span class="_ _1"></span>orking Registers</div><div class="t m0 x4 h5 y7 ff1 fs2 fc0 sc0 ls8 ws6">–<span class="_ _4"> </span>Fully Stati<span class="_ _1"></span>c<span class="_ _2"></span> Operation</div><div class="t m0 x4 h5 y8 ff1 fs2 fc0 sc0 ls9 ws7">–<span class="_ _4"> </span>Up to 16 MIPS Thro<span class="_ _3"></span>ughput at 16 MHz</div><div class="t m0 x4 h5 y9 ff1 fs2 fc0 sc0 lsa ws8">–<span class="_ _4"> </span>On-chip 2-c<span class="_ _1"></span>ycle Multiplier</div><div class="t m0 x1 h3 ya ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 lsb ws9">High Endurance <span class="_ _2"></span>Non-volatile Memory segments</span></div><div class="t m0 x4 h5 yb ff1 fs2 fc0 sc0 lsc wsa">–<span class="_ _4"> </span>16K Bytes of In-System Self-p<span class="lsd wsb">rogrammable Flash program memory</span></div><div class="t m0 x4 h5 yc ff1 fs2 fc0 sc0 lsd wsc">–<span class="_ _4"> </span>512 Bytes EEPROM</div><div class="t m0 x4 h5 yd ff1 fs2 fc0 sc0 lse wsd">–<span class="_ _4"> </span>1K Byte Internal SRAM</div><div class="t m0 x4 h5 ye ff1 fs2 fc0 sc0 lsf wse">–<span class="_ _4"> </span>Write/Erase Cycles: 10,000 Flash/100,0<span class="_ _2"></span>00 EEPROM</div><div class="t m0 x4 h5 yf ff1 fs2 fc0 sc0 ls10 wsf">–<span class="_ _4"> </span>Data retention: 20 years at 85°C/100 years at 25°C</div><div class="t m0 x5 h6 y10 ff2 fs4 fc1 sc0 ls11 ws0">(1)</div><div class="t m0 x4 h5 y11 ff1 fs2 fc0 sc0 ls12 ws10">–<span class="_ _4"> </span>Optional Boot Code Section w<span class="_ _1"></span>i<span class="_ _2"></span>th Independent Loc<span class="_ _1"></span>k Bits</div><div class="t m0 x6 h5 y12 ff1 fs2 fc0 sc0 ls13 ws11">•<span class="_ _4"> </span>In-System Programming b<span class="_ _1"></span>y On-chip Boot Program</div><div class="t m0 x6 h5 y13 ff1 fs2 fc0 sc0 lsc wsa">•<span class="_ _4"> </span>T<span class="_ _1"></span>rue Read-While-W<span class="ls14 ws12">rite Operatio<span class="_ _2"></span>n</span></div><div class="t m0 x4 h5 y14 ff1 fs2 fc0 sc0 lsd wsb">–<span class="_ _4"> </span>Programming Loc<span class="_ _3"></span>k for Software Security</div><div class="t m0 x1 h3 y15 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls15 ws13">JT<span class="_ _5"></span>A<span class="_ _1"></span>G (IEEE std. 1149.1 <span class="ls16 ws14">Compliant) Interface</span></span></div><div class="t m0 x4 h5 y16 ff1 fs2 fc0 sc0 ls7 ws15">–<span class="_ _4"> </span>Boundary-scan Capa<span class="_ _2"></span>bilities A<span class="ls17 ws16">ccording to the JT<span class="_ _5"></span>A<span class="_ _1"></span>G Standard</span></div><div class="t m0 x4 h5 y17 ff1 fs2 fc0 sc0 ls18 ws17">–<span class="_ _4"> </span>Extensive On-chip Debug Support</div><div class="t m0 x4 h5 y18 ff1 fs2 fc0 sc0 ls19 wsc">–<span class="_ _4"> </span>Programming of Flas<span class="ls7 ws5">h, EEPROM, Fuses, and <span class="ls16 ws18">Loc<span class="_ _1"></span>k Bits through the JT<span class="_ _5"></span>A<span class="_ _5"></span>G Interface</span></span></div><div class="t m0 x1 h3 y19 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls1a ws19">P<span class="_ _1"></span>eripheral Featu<span class="_ _1"></span>res</span></div><div class="t m0 x4 h5 y1a ff1 fs2 fc0 sc0 ls18 ws17">–<span class="_ _4"> </span>T<span class="_ _1"></span>wo 8-bit Timer/Counte<span class="ls1b ws1a">r<span class="_ _1"></span>s<span class="_ _2"></span> with Separate Prescalers and Compare Modes</span></div><div class="t m0 x4 h5 y1b ff1 fs2 fc0 sc0 lsa ws8">–<span class="_ _4"> </span>One 16-bit Timer/Coun<span class="_ _1"></span>ter <span class="ls1c ws1b">with Separate Pres<span class="_ _2"></span>caler<span class="_ _1"></span>, Compare Mode, and Capture </span></div><div class="t m0 x7 h5 y1c ff1 fs2 fc0 sc0 ls1d ws0">Mode</div><div class="t m0 x4 h5 y1d ff1 fs2 fc0 sc0 ls1e ws1c">–<span class="_ _4"> </span>Real Time Counter wi<span class="_ _2"></span>th<span class="ls13 ws1d"> Separate Oscillator</span></div><div class="t m0 x4 h5 y1e ff1 fs2 fc0 sc0 ls1f ws1e">–F<span class="_ _6"></span>o<span class="_ _6"></span>u<span class="_ _6"></span>r<span class="_ _6"></span> P<span class="_ _6"></span>W<span class="_ _6"></span>M<span class="_ _6"></span> <span class="_ _2"></span>C<span class="_ _6"></span>h<span class="_ _6"></span>a<span class="_ _6"></span>n<span class="_ _6"></span>n<span class="_ _6"></span>e<span class="_ _6"></span>l<span class="_ _6"></span>s</div><div class="t m0 x4 h5 y1f ff1 fs2 fc0 sc0 ls7 ws5">–<span class="_ _4"> </span>8-channel, 10-bit ADC</div><div class="t m0 x6 h5 y20 ff1 fs2 fc0 sc0 ls20 ws1f">•<span class="_ _4"> </span>8 Single-ended Channels</div><div class="t m0 x6 h5 y21 ff1 fs2 fc0 sc0 ls8 ws1f">•<span class="_ _4"> </span>7 Differential Chann<span class="_ _1"></span>e<span class="_ _2"></span>ls in TQFP P<span class="_ _1"></span>acka<span class="_ _1"></span>g<span class="_ _2"></span>e Only</div><div class="t m0 x6 h5 y22 ff1 fs2 fc0 sc0 ls20 ws20">•<span class="_ _4"> </span>2 Differential Channels with Pr<span class="_ _1"></span>og<span class="ls21 ws21">rammable Gain at 1x, 10x, or 200x</span></div><div class="t m0 x4 h5 y23 ff1 fs2 fc0 sc0 ls5 ws3">–<span class="_ _4"> </span>Byte-oriented T<span class="_ _1"></span>wo-wire Serial Interface</div><div class="t m0 x4 h5 y24 ff1 fs2 fc0 sc0 ls22 ws22">–<span class="_ _4"> </span>Programmable Serial USAR<span class="_ _1"></span>T</div><div class="t m0 x4 h5 y25 ff1 fs2 fc0 sc0 ls5 ws3">–<span class="_ _4"> </span>Master/Slave SPI Serial Interface</div><div class="t m0 x4 h5 y26 ff1 fs2 fc0 sc0 ls23 ws23">–<span class="_ _4"> </span>Programmab<span class="_ _1"></span>le Wat<span class="_ _3"></span>chdog Timer <span class="_ _3"></span>with Separate On-chip <span class="_ _3"></span>Oscillator</div><div class="t m0 x4 h5 y27 ff1 fs2 fc0 sc0 ls24 ws23">–<span class="_ _4"> </span>On-chip Analog <span class="_ _1"></span>Comparator</div><div class="t m0 x1 h3 y28 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ws24">Special Micr<span class="_ _1"></span>ocontroller Features</span></div><div class="t m0 x4 h5 y29 ff1 fs2 fc0 sc0 ls18 ws25">–<span class="_ _4"> </span>P<span class="_ _1"></span>ower-on Reset and Programmable Br<span class="_ _1"></span>own-out Detection</div><div class="t m0 x4 h5 y2a ff1 fs2 fc0 sc0 ls25 ws26">–<span class="_ _4"> </span>Internal Calibrated RC Oscillator</div><div class="t m0 x4 h5 y2b ff1 fs2 fc0 sc0 ls26 ws27">–<span class="_ _4"> </span>External and Internal Interrupt Sources</div><div class="t m0 x4 h5 y2c ff1 fs2 fc0 sc0 lsd ws28">–<span class="_ _4"> </span>Six Sleep Modes: <span class="_ _2"></span>Idle, ADC Noise Reduc<span class="ls27 ws29">tio<span class="_ _2"></span>n, P<span class="_ _3"></span>ower-sa<span class="_ _1"></span>ve<span class="_ _2"></span>, P<span class="_ _1"></span>ower-down, Standby </span></div><div class="t m0 x7 h5 y2d ff1 fs2 fc0 sc0 ls18 ws17">and Extended Standby</div><div class="t m0 x1 h3 y2e ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls28 ws2a">I/O and P<span class="_ _1"></span>acka<span class="_ _1"></span>ges</span></div><div class="t m0 x4 h5 y2f ff1 fs2 fc0 sc0 ls1c ws1b">–<span class="_ _4"> </span>32 Programmable I/O Lines</div><div class="t m0 x4 h5 y30 ff1 fs2 fc0 sc0 ls29 ws2b">–<span class="_ _4"> </span>40-pin PDIP<span class="_ _5"></span>, 44-lead TQFP<span class="_ _7"></span>, and 44-pad QFN/MLF</div><div class="t m0 x1 h3 y31 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls2a ws2c">Operating V<span class="_ _1"></span>oltages</span></div><div class="t m0 x4 h5 y32 ff1 fs2 fc0 sc0 lse wsd">–<span class="_ _4"> </span>2.7 - 5.5V for <span class="_ _3"></span>A<span class="_ _5"></span>Tmega16A</div><div class="t m0 x1 h3 y33 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 lsc wsa">Speed Grades</span></div><div class="t m0 x4 h5 y34 ff1 fs2 fc0 sc0 ls1 ws2d">–<span class="_ _4"> </span>0 - 16 MHz for A<span class="_ _5"></span>Tmega16A</div><div class="t m0 x1 h7 y35 ff2 fs1 fc0 sc0 ls1 ws0">•<span class="_ _0"> </span><span class="ff1 fs2 ls1d ws2e">P<span class="_ _1"></span>ower Consumption @ 1 MHz, <span class="_ _1"></span>3V<span class="_ _5"></span>, and 25<span class="ff3 ls1 ws0">°</span><span class="lsc ws2f">C f<span class="_ _1"></span>o<span class="_ _2"></span>r A<span class="_ _5"></span>Tmega16A</span></span></div><div class="t m0 x4 h5 y36 ff1 fs2 fc0 sc0 lse wsd">–<span class="_ _4"> </span>Active: 0.6 mA</div><div class="t m0 x4 h5 y37 ff1 fs2 fc0 sc0 ls22 ws22">–<span class="_ _4"> </span>Idle Mode: 0.2 mA</div><div class="t m0 x4 h5 y38 ff1 fs2 fc0 sc0 ls2b ws30">–<span class="_ _4"> </span>Powe<span class="_ _2"></span>r-d<span class="_ _2"></span>own<span class="_ _2"></span> Mo<span class="_ _2"></span>d<span class="_ _2"></span>e:<span class="_ _2"></span> <<span class="_ _2"></span> 1µ<span class="_ _2"></span>A</div><div class="t m0 x8 h8 y39 ff1 fs5 fc0 sc0 ls2c ws31">8-bit </div><div class="t m0 x8 h8 y3a ff1 fs5 fc0 sc0 ls2c ws0">Micr<span class="_ _1"></span>ocontroller </div><div class="t m0 x8 h8 y3b ff1 fs5 fc0 sc0 ls2c ws32">with 16K Bytes </div><div class="t m0 x8 h8 y3c ff1 fs5 fc0 sc0 ls1 ws0">In-System</div><div class="t m0 x8 h8 y3d ff1 fs5 fc0 sc0 ls29 ws0">Pr<span class="_ _1"></span>ogrammable </div><div class="t m0 x8 h8 y3e ff1 fs5 fc0 sc0 ls29 ws0">Flash</div><div class="t m0 x8 h8 y3f ff1 fs5 fc0 sc0 ls1 ws0">A<span class="_ _8"></span>Tmega16A</div><div class="t m0 x9 h9 y40 ff2 fs6 fc0 sc0 ls2d ws0">8154B–AVR–07/09</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259f2b292dc900e62cf1d7c/bg2.jpg"><div class="t m0 xa h3 y41 ff1 fs1 fc0 sc0 ls1 ws0">2</div><div class="t m0 xb h9 y42 ff2 fs6 fc0 sc0 ls2e ws0">8154B–AVR–07/09</div><div class="t m0 xc h8 y43 ff1 fs5 fc0 sc0 ls18 ws0">ATmega16A</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls2f ws33">1.<span class="_ _9"> </span>Pin Configurations</div><div class="t m0 xd h3 y44 ff1 fs1 fc0 sc0 ls30 ws34">Figure 1-1.<span class="_ _a"> </span><span class="ff2 ls31 ws35">Pinout ATmega16<span class="_ _3"></span>A</span></div><div class="c xe y45 w2 ha"><div class="t m2 xf hb y46 ff4 fs7 fc2 sc0 ls1 ws0">(XCK/T0) PB0</div><div class="t m2 x10 hb y47 ff4 fs7 fc2 sc0 ls1 ws0">(T1) PB1</div><div class="t m2 x11 hb y48 ff4 fs7 fc2 sc0 ls1 ws0">(INT2/AIN0) PB2</div><div class="t m2 x12 hb y49 ff4 fs7 fc2 sc0 ls1 ws0">(OC0/AIN1) PB3</div><div class="t m2 x13 hb y4a ff4 fs7 fc2 sc0 ls1 ws0">(SS) PB4</div><div class="t m2 x14 hb y4b ff4 fs7 fc2 sc0 ls1 ws0">(MOSI) PB5</div><div class="t m2 x14 hb y4c ff4 fs7 fc2 sc0 ls1 ws0">(MISO) PB6</div><div class="t m2 x15 hb y4d ff4 fs7 fc2 sc0 ls1 ws0">(SCK) PB7</div><div class="t m2 x16 hb y4e ff4 fs7 fc2 sc0 ls1 ws0">RESET</div><div class="t m2 x17 hb y4f ff4 fs7 fc2 sc0 ls1 ws0">VCC</div><div class="t m2 x18 hb y50 ff4 fs7 fc2 sc0 ls1 ws0">GND</div><div class="t m2 x19 hb y51 ff4 fs7 fc2 sc0 ls1 ws0">XT<span class="_ _1"></span>AL2</div><div class="t m2 x19 hb y52 ff4 fs7 fc2 sc0 ls1 ws0">XT<span class="_ _1"></span>AL1</div><div class="t m2 x1a hb y53 ff4 fs7 fc2 sc0 ls1 ws0">(RXD) PD0</div><div class="t m2 x15 hb y54 ff4 fs7 fc2 sc0 ls1 ws0">(TXD) PD1</div><div class="t m2 x1a hb y55 ff4 fs7 fc2 sc0 ls1 ws0">(INT0) PD2</div><div class="t m2 x1a hb y56 ff4 fs7 fc2 sc0 ls1 ws0">(INT1) PD3</div><div class="t m2 x1b hb y57 ff4 fs7 fc2 sc0 ls1 ws0">(OC1B) PD4</div><div class="t m2 x1b hb y58 ff4 fs7 fc2 sc0 ls1 ws0">(OC1A) PD5</div><div class="t m2 x1c hb y59 ff4 fs7 fc2 sc0 ls1 ws0">(ICP1) PD6</div><div class="t m2 x1d hb y5a ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A0 (ADC0)</div><div class="t m2 x1d hb y5b ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A1 (ADC1)</div><div class="t m2 x1d hb y5c ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A2 (ADC2)</div><div class="t m2 x1d hb y5d ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A3 (ADC3)</div><div class="t m2 x1d hb y5e ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A4 (ADC4)</div><div class="t m2 x1d hb y5f ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A5 (ADC5)</div><div class="t m2 x1d hb y60 ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A6 (ADC6)</div><div class="t m2 x1d hb y61 ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A7 (ADC7)</div><div class="t m2 x1d hb y62 ff4 fs7 fc2 sc0 ls1 ws0">AREF</div><div class="t m2 x1d hb y63 ff4 fs7 fc2 sc0 ls1 ws0">GND</div><div class="t m2 x1d hb y64 ff4 fs7 fc2 sc0 ls1 ws0">A<span class="_ _1"></span>VCC</div><div class="t m2 x1d hb y65 ff4 fs7 fc2 sc0 ls1 ws0">PC7 (TOSC2)</div><div class="t m2 x1d hb y66 ff4 fs7 fc2 sc0 ls1 ws0">PC6 (TOSC1)</div><div class="t m2 x1d hb y67 ff4 fs7 fc2 sc0 ls1 ws0">PC5 (TDI)</div><div class="t m2 x1d hb y68 ff4 fs7 fc2 sc0 ls1 ws0">PC4 (TDO)</div><div class="t m2 x1d hb y69 ff4 fs7 fc2 sc0 ls1 ws0">PC3 (TMS)</div><div class="t m2 x1d hb y6a ff4 fs7 fc2 sc0 ls1 ws0">PC2 (TCK)</div><div class="t m2 x1d hb y6b ff4 fs7 fc2 sc0 ls1 ws0">PC1 (SDA)</div><div class="t m2 x1d hb y6c ff4 fs7 fc2 sc0 ls1 ws0">PC0 (SCL)</div><div class="t m2 x1d hb y6d ff4 fs7 fc2 sc0 ls1 ws0">PD7 (OC2)</div><div class="t m2 x1e hb y6e ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A4 (ADC4)</div><div class="t m2 x1e hb y6f ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A5 (ADC5)</div><div class="t m2 x1e hb y70 ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A6 (ADC6)</div><div class="t m2 x1e hb y71 ff4 fs7 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A7 (ADC7)</div><div class="t m2 x1e hb y72 ff4 fs7 fc2 sc0 ls1 ws0">AREF</div><div class="t m2 x1e hb y73 ff4 fs7 fc2 sc0 ls1 ws0">GND</div><div class="t m2 x1e hb y74 ff4 fs7 fc2 sc0 ls1 ws0">A<span class="_ _1"></span>VCC</div><div class="t m2 x1e hb y75 ff4 fs7 fc2 sc0 ls1 ws0">PC7 (TOSC2)</div><div class="t m2 x1e hb y76 ff4 fs7 fc2 sc0 ls1 ws0">PC6 (TOSC1)</div><div class="t m2 x1e hb y77 ff4 fs7 fc2 sc0 ls1 ws0">PC5 (TDI)</div><div class="t m2 x1e hb y78 ff4 fs7 fc2 sc0 ls1 ws0">PC4 (TDO)</div><div class="t m2 x1f hb y79 ff4 fs7 fc2 sc0 ls1 ws0">(MOSI) PB5</div><div class="t m2 x1f hb y7a ff4 fs7 fc2 sc0 ls1 ws0">(MISO) PB6</div><div class="t m2 x20 hb y7b ff4 fs7 fc2 sc0 ls1 ws0">(SCK) PB7</div><div class="t m2 x21 hb y7c ff4 fs7 fc2 sc0 ls1 ws0">RESET</div><div class="t m2 x22 hb y7d ff4 fs7 fc2 sc0 ls1 ws0">VCC</div><div class="t m2 x23 hb y7e ff4 fs7 fc2 sc0 ls1 ws0">GND</div><div class="t m2 x24 hb y7f ff4 fs7 fc2 sc0 ls1 ws0">XT<span class="_ _1"></span>AL2</div><div class="t m2 x24 hb y80 ff4 fs7 fc2 sc0 ls1 ws0">XT<span class="_ _1"></span>AL1</div><div class="t m2 x25 hb y81 ff4 fs7 fc2 sc0 ls1 ws0">(RXD) PD0</div><div class="t m2 x20 hb y82 ff4 fs7 fc2 sc0 ls1 ws0">(TXD) PD1</div><div class="t m2 x25 hb y83 ff4 fs7 fc2 sc0 ls1 ws0">(INT0) PD2</div><div class="t m3 x26 hc y84 ff4 fs8 fc2 sc0 ls1 ws0">(INT1) PD3</div><div class="t m3 x27 hc y85 ff4 fs8 fc2 sc0 ls1 ws0">(OC1B) PD4</div><div class="t m3 x28 hc y85 ff4 fs8 fc2 sc0 ls1 ws0">(OC1A) PD5</div><div class="t m3 x29 hc y86 ff4 fs8 fc2 sc0 ls1 ws0">(ICP1) PD6</div><div class="t m3 x2a hc y87 ff4 fs8 fc2 sc0 ls1 ws0">(OC2) PD7</div><div class="t m3 x2b hc y88 ff4 fs8 fc2 sc0 ls1 ws0">VCC</div><div class="t m3 x2c hc y89 ff4 fs8 fc2 sc0 ls1 ws0">GND</div><div class="t m3 x2d hc y8a ff4 fs8 fc2 sc0 ls1 ws0">(SCL) PC0</div><div class="t m3 x2e hc y8b ff4 fs8 fc2 sc0 ls1 ws0">(SDA) PC1</div><div class="t m3 x2f hc y8c ff4 fs8 fc2 sc0 ls1 ws0">(TCK) PC2</div><div class="t m3 x30 hc y8d ff4 fs8 fc2 sc0 ls1 ws0">(TMS) PC3</div><div class="t m3 x31 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">PB4 (SS)</div><div class="t m3 x32 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">PB3 (AIN1/OC0)</div><div class="t m3 x33 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">PB2 (AIN0/INT2)</div><div class="t m3 x34 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">PB1 (T1)</div><div class="t m3 x35 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">PB0 (XCK/T0)</div><div class="t m3 x36 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">GND</div><div class="t m3 x37 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">VCC</div><div class="t m3 x38 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A0 (ADC0)</div><div class="t m3 x39 hc y8e ff4 fs8 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A1 (ADC1)</div><div class="t m3 x3a hc y8e ff4 fs8 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A2 (ADC2)</div><div class="t m3 x3b hc y8e ff4 fs8 fc2 sc0 ls1 ws0">P<span class="_ _1"></span>A3 (ADC3)</div><div class="t m2 x35 hd y8f ff1 fs9 fc2 sc0 ls1 ws0">PDIP</div><div class="t m2 x3c hd y90 ff1 fs9 fc2 sc0 ls1 ws0">TQFP/QFN/MLF</div><div class="t m2 x3d he y91 ff5 fs9 fc2 sc0 ls1 ws0">NOTE:</div><div class="t m2 x3d he y92 ff5 fs9 fc2 sc0 ls1 ws0">Bottom pad should </div><div class="t m2 x3d he y93 ff5 fs9 fc2 sc0 ls1 ws0">be soldered to ground.</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259f2b292dc900e62cf1d7c/bg3.jpg"><div class="t m0 x3e h3 y41 ff1 fs1 fc0 sc0 ls1 ws0">3</div><div class="t m0 x1 h9 y42 ff2 fs6 fc0 sc0 ls32 ws0">8154B–AVR–07/09</div><div class="t m0 x3f h8 y94 ff1 fs5 fc0 sc0 ls18 ws0">ATmega16A</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls33 ws0">2.<span class="_ _9"> </span>Overview</div><div class="t m0 xd h3 y95 ff2 fs1 fc0 sc0 ls34 ws36">The ATmega16A <span class="_ _1"></span>is a low-power CMOS 8-bit microco<span class="_ _3"></span>ntroller based o<span class="_ _1"></span>n the AVR enhanced RISC</div><div class="t m0 xd h3 y96 ff2 fs1 fc0 sc0 ls35 ws37">architecture. By executing powerful instructions in a single clock cycle, the ATmega16A</div><div class="t m0 xd h3 y97 ff2 fs1 fc0 sc0 ls36 ws38">achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize</div><div class="t m0 xd h3 y98 ff2 fs1 fc0 sc0 ls37 ws39">power consumption versus proc<span class="_ _3"></span>essing speed.</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259f2b292dc900e62cf1d7c/bg4.jpg"><div class="t m0 xa h3 y41 ff1 fs1 fc0 sc0 ls1 ws0">4</div><div class="t m0 xb h9 y42 ff2 fs6 fc0 sc0 ls2e ws0">8154B–AVR–07/09</div><div class="t m0 xc h8 y43 ff1 fs5 fc0 sc0 ls18 ws0">ATmega16A</div><div class="t m0 x1 hf y99 ff1 fsa fc0 sc0 ls38 ws3a">2.1<span class="_ _b"> </span>Bloc<span class="_ _1"></span>k Diagram</div><div class="t m0 xd h3 y9a ff1 fs1 fc0 sc0 ls30 ws34">Figure 2-1.<span class="_ _a"> </span><span class="ff2 ls39 ws3b">Block Diagr<span class="_ _1"></span>am</span></div><div class="c x2e y9b w3 h10"><div class="t m4 x40 h11 y9c ff2 fsb fc2 sc0 ls1 ws0">INTERNAL</div><div class="t m4 x41 h11 y9d ff2 fsb fc2 sc0 ls1 ws0">OSCILLA<span class="_ _5"></span>TOR</div><div class="t m4 x42 h11 y9e ff2 fsb fc2 sc0 ls1 ws0">OSCILLA<span class="_ _5"></span>TOR</div><div class="t m4 x43 h11 y9f ff2 fsb fc2 sc0 ls1 ws0">W<span class="_ _3"></span>A<span class="_ _5"></span>TCHDOG</div><div class="t m4 x44 h11 ya0 ff2 fsb fc2 sc0 ls1 ws0">TIMER</div><div class="t m4 x45 h11 ya1 ff2 fsb fc2 sc0 ls1 ws0">MCU CTRL.</div><div class="t m4 x46 h11 ya2 ff2 fsb fc2 sc0 ls1 ws3c">& TIMING</div><div class="t m4 x42 h11 ya3 ff2 fsb fc2 sc0 ls1 ws0">OSCILLA<span class="_ _5"></span>TOR</div><div class="t m4 x47 h11 ya4 ff2 fsb fc2 sc0 ls1 ws0">TIMERS/</div><div class="t m4 x45 h11 ya5 ff2 fsb fc2 sc0 ls1 ws0">COUNTERS</div><div class="t m4 x48 h11 ya6 ff2 fsb fc2 sc0 ls1 ws0">INTERRUPT</div><div class="t m4 x49 h11 ya7 ff2 fsb fc2 sc0 ls1 ws0">UNIT</div><div class="t m4 x34 h11 ya8 ff2 fsb fc2 sc0 ls1 ws0">ST<span class="_ _5"></span>ACK</div><div class="t m4 x4a h11 ya9 ff2 fsb fc2 sc0 ls1 ws0">POINTER</div><div class="t m4 x46 h11 yaa ff2 fsb fc2 sc0 ls1 ws0">EEPROM</div><div class="t m4 x4b h11 yab ff2 fsb fc2 sc0 ls1 ws0">SRAM</div><div class="t m4 x4c h11 yac ff2 fsb fc2 sc0 ls1 ws0">ST<span class="_ _5"></span>A<span class="_ _1"></span>TUS</div><div class="t m4 x4d h11 yad ff2 fsb fc2 sc0 ls1 ws0">REGISTER</div><div class="t m4 x4e h11 yae ff2 fsb fc2 sc0 ls1 ws0">USART</div><div class="t m4 x4f h11 ya8 ff2 fsb fc2 sc0 ls1 ws0">PROGRAM</div><div class="t m4 x1b h11 ya9 ff2 fsb fc2 sc0 ls1 ws0">COUNTER</div><div class="t m4 x4f h11 y9c ff2 fsb fc2 sc0 ls1 ws0">PROGRAM</div><div class="t m4 x1a h11 y9d ff2 fsb fc2 sc0 ls1 ws0">FLASH</div><div class="t m4 xf h11 y9f ff2 fsb fc2 sc0 ls1 ws0">INSTRUCTION</div><div class="t m4 x4f h11 ya0 ff2 fsb fc2 sc0 ls1 ws0">REGISTER</div><div class="t m4 xf h11 ya1 ff2 fsb fc2 sc0 ls1 ws0">INSTRUCTION</div><div class="t m4 x4f h11 ya2 ff2 fsb fc2 sc0 ls1 ws0">DECODER</div><div class="t m5 x7 h12 yaf ff2 fsc fc2 sc0 ls3a ws0">PROGRAMMING</div><div class="t m5 x6 h12 yb0 ff2 fsc fc2 sc0 ls3a ws0">LOGIC</div><div class="t m4 x50 h11 yae ff2 fsb fc2 sc0 ls1 ws0">SPI</div><div class="t m4 x51 h11 yb1 ff2 fsb fc2 sc0 ls1 ws0">ADC</div><div class="t m4 x52 h11 yb2 ff2 fsb fc2 sc0 ls1 ws0">INTERF<span class="_ _1"></span>ACE</div><div class="t m4 x34 h11 yb3 ff2 fsb fc2 sc0 ls1 ws0">COMP<span class="_ _5"></span>.</div><div class="t m4 x52 h11 yb4 ff2 fsb fc2 sc0 ls1 ws0">INTERF<span class="_ _1"></span>ACE</div><div class="t m4 x6 h11 yb5 ff2 fsb fc2 sc0 ls1 ws0">PORT<span class="_ _5"></span>A DRIVERS/BUFFERS</div><div class="t m4 x1a h11 yb6 ff2 fsb fc2 sc0 ls1 ws0">PORT<span class="_ _5"></span>A DIGIT<span class="_ _5"></span>AL INTERFA<span class="_ _1"></span>CE</div><div class="t m4 x4d h11 yb7 ff2 fsb fc2 sc0 ls1 ws0">GENERAL</div><div class="t m4 x4d h11 yb8 ff2 fsb fc2 sc0 ls1 ws0">PURPOSE</div><div class="t m4 x28 h11 yb9 ff2 fsb fc2 sc0 ls1 ws0">REGISTERS</div><div class="t m4 x53 h11 yba ff2 fsb fc2 sc0 ls1 ws0">X</div><div class="t m4 x53 h11 ybb ff2 fsb fc2 sc0 ls1 ws0">Y</div><div class="t m4 x53 h11 ybc ff2 fsb fc2 sc0 ls1 ws0">Z</div><div class="t m6 x29 h13 ybd ff2 fsd fc2 sc0 ls1 ws0">ALU</div><div class="t m7 x54 h14 ybe ff2 fse fc2 sc0 ls1 ws0">+</div><div class="t m7 x55 h14 ybf ff2 fse fc2 sc0 ls1 ws0">-</div><div class="t m4 x56 h11 yb5 ff2 fsb fc2 sc0 ls1 ws0">PORTC DRIVERS/BUFFERS</div><div class="t m4 x44 h11 yb6 ff2 fsb fc2 sc0 ls1 ws0">PORTC DIGIT<span class="_ _5"></span>AL INTERF<span class="_ _1"></span>ACE</div><div class="t m4 x1a h11 yc0 ff2 fsb fc2 sc0 ls1 ws0">PORTB DIGIT<span class="_ _5"></span>AL INTERF<span class="_ _1"></span>ACE</div><div class="t m4 x6 h11 yc1 ff2 fsb fc2 sc0 ls1 ws0">PORTB DRIVERS/BUFFERS</div><div class="t m4 x44 h11 yc0 ff2 fsb fc2 sc0 ls1 ws0">PORTD DIGIT<span class="_ _5"></span>AL INTERF<span class="_ _1"></span>ACE</div><div class="t m4 x56 h11 yc1 ff2 fsb fc2 sc0 ls1 ws0">PORTD DRIVERS/BUFFERS</div><div class="t m4 x57 h11 yc2 ff2 fsb fc2 sc0 ls1 ws0">XT<span class="_ _5"></span>AL1</div><div class="t m4 x57 h11 yc3 ff2 fsb fc2 sc0 ls1 ws0">XT<span class="_ _5"></span>AL2</div><div class="t m4 x57 h11 yc4 ff2 fsb fc2 sc0 ls1 ws0">RESET</div><div class="t m7 x58 h14 yc5 ff2 fse fc2 sc0 ls1 ws0">CONTROL</div><div class="t m7 x1a h14 yc6 ff2 fse fc2 sc0 ls1 ws0">LINES</div><div class="t m4 x0 h11 yc7 ff2 fsb fc2 sc0 ls1 ws0">VCC</div><div class="t m4 x59 h11 yc8 ff2 fsb fc2 sc0 ls1 ws0">GND</div><div class="t m6 x1a h13 yc9 ff2 fsd fc2 sc0 ls1 ws0">MUX &</div><div class="t m6 x54 h13 yca ff2 fsd fc2 sc0 ls1 ws0">ADC</div><div class="t m4 x5a h11 ycb ff2 fsb fc2 sc0 ls1 ws0">AREF</div><div class="t m4 x5b h11 ycc ff2 fsb fc2 sc0 ls1 ws0">P<span class="_ _5"></span>A0 - P<span class="_ _1"></span>A7<span class="_ _c"> </span>PC0 - PC7</div><div class="t m4 x5c h11 ycd ff2 fsb fc2 sc0 ls1 ws0">PD0 - PD7<span class="_ _d"></span>PB0 - PB7</div><div class="t m8 xf h15 yce ff2 fsf fc2 sc0 ls1 ws0">A<span class="_ _1"></span>VR CPU</div><div class="t m4 x5d h11 ycf ff2 fsb fc2 sc0 ls1 ws0">TWI</div><div class="t m4 x5a h11 yd0 ff2 fsb fc2 sc0 ls1 ws0">A<span class="_ _1"></span>VCC</div><div class="t m4 x5e h11 yd1 ff2 fsb fc2 sc0 ls1 ws0">INTERNAL</div><div class="t m4 x42 h11 yd2 ff2 fsb fc2 sc0 ls1 ws0">CALIBRA<span class="_ _5"></span>TED</div><div class="t m4 x42 h11 yd3 ff2 fsb fc2 sc0 ls1 ws0">OSCILLA<span class="_ _5"></span>TOR</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/6259f2b292dc900e62cf1d7c/bg5.jpg"><div class="t m0 x3e h3 y41 ff1 fs1 fc0 sc0 ls1 ws0">5</div><div class="t m0 x1 h9 y42 ff2 fs6 fc0 sc0 ls32 ws0">8154B–AVR–07/09</div><div class="t m0 x3f h8 y94 ff1 fs5 fc0 sc0 ls18 ws0">ATmega16A</div><div class="t m0 xd h3 yd4 ff2 fs1 fc0 sc0 ls3b ws3d">The AVR core combines a rich instruction<span class="_ _1"></span> <span class="_ _2"></span>set with 32 general purpose wo<span class="_ _1"></span>rking <span class="_ _2"></span>registers. All the</div><div class="t m0 xd h3 yd5 ff2 fs1 fc0 sc0 ls3b ws3d">32 registers are di<span class="_ _1"></span>rectly <span class="_ _2"></span>connected to th<span class="_ _1"></span>e Arithmetic Logic Unit (ALU), allowing two inde<span class="_ _1"></span>pendent</div><div class="t m0 xd h3 yd6 ff2 fs1 fc0 sc0 ls3c ws3e">registers to be accessed in one single instruction executed<span class="ls3d ws3f"> in one clock cycle. The resulting</span></div><div class="t m0 xd h3 yd7 ff2 fs1 fc0 sc0 ls3e ws40">architecture is more code efficient while achiev<span class="_ _2"></span><span class="ls3f ws41">ing throughputs up to ten times faster than con-</span></div><div class="t m0 xd h3 yd8 ff2 fs1 fc0 sc0 ls40 ws42">ventional CISC microcontrollers.</div><div class="t m0 xd h3 yd9 ff2 fs1 fc0 sc0 ls41 ws43">The ATmega16A provides the following features: <span class="ls3f ws44">16K bytes of In-System Programmable Flash</span></div><div class="t m0 xd h3 yda ff2 fs1 fc0 sc0 ls42 ws45">Program memory with Re<span class="_ _2"></span><span class="ls43 ws46">ad-While-Write capabilities, 512 <span class="ls44 ws47">bytes EE<span class="_ _2"></span>PROM, 1K byte SRAM, 32</span></span></div><div class="t m0 xd h3 ydb ff2 fs1 fc0 sc0 ls3b ws48">general purpose I/<span class="_ _3"></span>O lines, 32 general pur<span class="_ _3"></span>pose working register<span class="_ _1"></span>s, a <span class="_ _2"></span>JTAG interface for Bou<span class="_ _1"></span>ndary-</div><div class="t m0 xd h3 ydc ff2 fs1 fc0 sc0 ls45 ws49">scan, On-chip Debugging su<span class="_ _3"></span>pport and programmin<span class="_ _3"></span>g<span class="ls46 ws4a">, three flexible Timer/Cou<span class="_ _3"></span>nters with com-</span></div><div class="t m0 xd h3 ydd ff2 fs1 fc0 sc0 ls47 ws4b">pare mode<span class="_ _2"></span>s, Interna<span class="_ _2"></span>l and Extern<span class="_ _2"></span>al Interrup<span class="_ _2"></span>ts<span class="ls48 ws4c">, a serial programma<span class="_ _1"></span>ble USART, a byte oriented</span></div><div class="t m0 xd h3 yde ff2 fs1 fc0 sc0 ls45 ws4c">Two-wire Serial Interf<span class="_ _3"></span>ace, an 8-channel, 10-<span class="_ _3"></span>bi<span class="ls49 ws4d">t ADC with optio<span class="_ _3"></span>nal differential input stage with</span></div><div class="t m0 xd h3 ydf ff2 fs1 fc0 sc0 ls31 ws4e">programmable g<span class="_ _1"></span>ain (TQFP package only), a programma<span class="_ _3"></span>ble Watchdog Timer<span class="_ _3"></span> with Internal Oscil-</div><div class="t m0 xd h3 ye0 ff2 fs1 fc0 sc0 ls30 ws4f">lator, an SPI serial port, and six software<span class="_ _1"></span> <span class="_ _2"></span>selectable power saving modes. The Idle mod<span class="_ _1"></span>e stops</div><div class="t m0 xd h3 ye1 ff2 fs1 fc0 sc0 ls4a ws50">the CPU while allowing the USART,<span class="ls1 ws51"> Two-wire in<span class="_ _2"></span>terface, A/D Conver<span class="_ _2"></span>ter, SRAM, Timer/Co<span class="_ _2"></span>unters,</span></div><div class="t m0 xd h3 ye2 ff2 fs1 fc0 sc0 ls4b ws52">SPI port, and inte<span class="_ _3"></span>rrupt system to continue<span class="_ _1"></span> functioning. The Power-down mod<span class="_ _3"></span>e saves the register</div><div class="t m0 xd h3 ye3 ff2 fs1 fc0 sc0 ls40 ws42">contents but freezes the Oscillator,<span class="ls4c ws53"> disabling all other ch</span>ip functions until the <span class="ls4d ws54">next External Inter-</span></div><div class="t m0 xd h3 ye4 ff2 fs1 fc0 sc0 ls4e ws40">rupt or Hardware <span class="_ _2"></span>Reset. In Power-save mode<span class="_ _2"></span>, the Asynchronous Timer con<span class="_ _2"></span>tinues to run,</div><div class="t m0 xd h3 ye5 ff2 fs1 fc0 sc0 ls4f ws55">allowing the user<span class="_ _1"></span> to maintain a timer base while the<span class="_ _1"></span> rest of the device is sleeping. The ADC</div><div class="t m0 xd h3 ye6 ff2 fs1 fc0 sc0 ls50 ws56">Noise Reduction mode stops the CPU and all I<span class="_ _3"></span>/O modules except Asynchronous Timer and</div><div class="t m0 xd h3 ye7 ff2 fs1 fc0 sc0 ls51 ws57">ADC, to minimize switching noise<span class="_ _2"></span> during ADC conversions. In <span class="_ _2"></span>Standby mode, the <span class="_ _2"></span>crystal/reso-</div><div class="t m0 xd h3 ye8 ff2 fs1 fc0 sc0 ls52 ws58">nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up</div><div class="t m0 xd h3 ye9 ff2 fs1 fc0 sc0 ls49 ws4d">combined with low-power consumption. In Extended Standby mode,<span class="ls53 ws59"> both the main Oscillator</span></div><div class="t m0 xd h3 yea ff2 fs1 fc0 sc0 ls31 ws35">and the Asyn<span class="_ _1"></span>chronous Timer continue to r<span class="_ _1"></span>un. </div><div class="t m0 xd h3 yeb ff2 fs1 fc0 sc0 ls54 ws5a">The device is manufactured u<span class="_ _1"></span>s<span class="_ _2"></span>ing Atmel’s high <span class="ls3b ws5b">density no<span class="_ _1"></span>nvolatile memory technology. The On-</span></div><div class="t m0 xd h3 yec ff2 fs1 fc0 sc0 ls55 ws5c">chip ISP Flash allows the prog<span class="ls56 ws5d">ram memory to be repr<span class="ls40 ws5e">ogrammed in-system th<span class="ls57 ws5f">rough an SPI serial</span></span></span></div><div class="t m0 xd h3 yed ff2 fs1 fc0 sc0 ls58 ws37">interface, by a conventional nonvolatile memory programm<span class="_ _2"></span>er, or by an On-chip Boot program</div><div class="t m0 xd h3 yee ff2 fs1 fc0 sc0 ls59 ws60">running on the AVR core. The boot progra<span class="_ _2"></span>m can use any interface to download the <span class="_ _2"></span>application</div><div class="t m0 xd h3 yef ff2 fs1 fc0 sc0 ls31 ws61">program in the App<span class="_ _3"></span>lication Flash memory. Sof<span class="_ _1"></span>tware in the Boot Flash section wil<span class="_ _1"></span>l <span class="_ _2"></span>continue to run</div><div class="t m0 xd h3 yf0 ff2 fs1 fc0 sc0 ls5a ws62">while the Application Flash section is updated, <span class="ls5b ws63">providing true Rea<span class="_ _2"></span>d-While-Write operation. By</span></div><div class="t m0 xd h3 yf1 ff2 fs1 fc0 sc0 ls5c ws64">combining an 8-bit RISC CPU with In-System Self-P<span class="_ _2"></span>rogrammable Flash on a mon<span class="_ _2"></span>olithic chip,</div><div class="t m0 xd h3 yf2 ff2 fs1 fc0 sc0 ls5d ws64">the Atmel ATmeg<span class="_ _2"></span>a16A is a pow<span class="_ _2"></span>erful microcon<span class="_ _2"></span>troller that provid<span class="_ _2"></span>es a highly-flex<span class="_ _2"></span>ible and cos<span class="_ _2"></span>t-</div><div class="t m0 xd h3 yf3 ff2 fs1 fc0 sc0 ls5e ws65">effective solution t<span class="_ _1"></span>o<span class="_ _2"></span> many embedded cont<span class="_ _1"></span>rol applications.</div><div class="t m0 xd h3 yf4 ff2 fs1 fc0 sc0 ls5f ws4c">The ATmega16A AVR is suppor<span class="_ _1"></span>ted with a full suite of program and system develo<span class="_ _1"></span>pment tools</div><div class="t m0 xd h3 yf5 ff2 fs1 fc0 sc0 ls60 ws56">including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,</div><div class="t m0 xd h3 yf6 ff2 fs1 fc0 sc0 ls61 ws66">and evaluation kits.</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
