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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/628c3821ce083560b88131d5/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c3821ce083560b88131d5/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">S3C2440A</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls1 ws0">32-BIT RISC</div><div class="t m0 x3 h3 y3 ff1 fs1 fc0 sc0 ls2 ws0">MICROPROCESSOR</div><div class="t m0 x4 h4 y4 ff1 fs2 fc0 sc0 ls3 ws0">USER'S MANUAL</div><div class="t m0 x5 h5 y5 ff1 fs3 fc0 sc0 ls4 ws0">(Preliminary)</div><div class="t m0 x6 h5 y6 ff1 fs3 fc0 sc0 ls5 ws0">Revision 0.13</div><div class="t m0 x7 h6 y7 ff2 fs4 fc0 sc0 ls6 ws0">(June 3, 2004)</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c3821ce083560b88131d5/bg2.jpg"><div class="t m0 x8 h7 y8 ff3 fs5 fc0 sc0 ls7 ws0">2004.06.03</div><div class="t m0 x9 h7 y9 ff3 fs5 fc0 sc0 ls7 ws0">Preliminary product information describes products that are in development,</div><div class="t m0 xa h7 ya ff3 fs5 fc0 sc0 ls7 ws0">for which full characterization data and associated errata are not yet available</div><div class="t m0 xb h7 yb ff3 fs5 fc0 sc0 ls7 ws0">Specifications and information herein are subject to change without notice.</div><div class="t m0 xc h8 yc ff4 fs5 fc0 sc0 ls8 ws0">S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW</div><div class="t m0 xd h8 yd ff4 fs5 fc0 sc0 ls9 ws0">1-1</div><div class="t m0 xc h9 ye ff4 fs6 fc0 sc0 ls7 ws0">1 PRODUCT OVERVIEW</div><div class="t m0 xc ha yf ff4 fs8 fc0 sc0 lsb ws0">INTRODUCTION</div><div class="t m0 xc hb y10 ff3 fs4 fc0 sc0 lsc ws0">This manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is</div><div class="t m0 xc hb y11 ff3 fs4 fc0 sc0 lsd ws0">designed to provide hand-held devices and general applications with low-power, and high-performance micro-</div><div class="t m0 xc hb y12 ff3 fs4 fc0 sc0 lsd ws0">controller solution in small die size. To reduce total system cost, the S3C2440A includes the following components.</div><div class="t m0 xc hb y13 ff3 fs4 fc0 sc0 lsc ws0">The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-</div><div class="t m0 xc hb y14 ff3 fs4 fc0 sc0 lse ws0">power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It</div><div class="t m0 xc hb y15 ff3 fs4 fc0 sc0 lsf ws0">adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).</div><div class="t m0 xc hb y16 ff3 fs4 fc0 sc0 lsf ws0">The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by</div><div class="t m0 xc hb y17 ff3 fs4 fc0 sc0 lsd ws0">Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture</div><div class="t m0 xc hb y18 ff3 fs4 fc0 sc0 lsc ws0">with separate 16KB instruction and 16KB data caches, each with an 8-word line length.</div><div class="t m0 xc hb y19 ff3 fs4 fc0 sc0 ls10 ws0">By providing a complete set of common system peripherals, the S3C2440A minimizes overall system costs and</div><div class="t m0 xc hb y1a ff3 fs4 fc0 sc0 ls10 ws0">eliminates the need to configure additional components. The integrated on-chip functions that are described in this</div><div class="t m0 xc hb y1b ff3 fs4 fc0 sc0 ls11 ws0">document include:</div><div class="t m0 xc hc y1c ff5 fs9 fc0 sc0 ls7 ws0">• Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-</div><div class="t m0 xe hb y1d ff3 fs4 fc0 sc0 ls13 ws0">Cache/MMU</div><div class="t m0 xc hc y1e ff5 fs9 fc0 sc0 ls7 ws0">• External memory controller (SDRAM Control and Chip Select logic)</div><div class="t m0 xc hc y1f ff5 fs9 fc0 sc0 ls7 ws0">• LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA</div><div class="t m0 xc hc y20 ff5 fs9 fc0 sc0 ls7 ws0">• 4-ch DMA controllers with external request pins</div><div class="t m0 xc hc y21 ff5 fs9 fc0 sc0 ls7 ws0">• 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)</div><div class="t m0 xc hc y22 ff5 fs9 fc0 sc0 ls7 ws0">• 2-ch SPls</div><div class="t m0 xc hc y23 ff5 fs9 fc0 sc0 ls7 ws0">• IIC bus interface (multi-master support)</div><div class="t m0 xc hc y24 ff5 fs9 fc0 sc0 ls7 ws0">• IIS Audio CODEC interface</div><div class="t m0 xc hc y25 ff5 fs9 fc0 sc0 ls7 ws0">• AC’97 CODEC interface</div><div class="t m0 xc hc y26 ff5 fs9 fc0 sc0 ls7 ws0">• SD Host interface version 1.0 & MMC Protocol version 2.11 compatible</div><div class="t m0 xc hc y27 ff5 fs9 fc0 sc0 ls7 ws0">• 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)</div><div class="t m0 xc hc y28 ff5 fs9 fc0 sc0 ls7 ws0">• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer</div><div class="t m0 xc hc y29 ff5 fs9 fc0 sc0 ls7 ws0">• 8-ch 10-bit ADC and Touch screen interface</div><div class="t m0 xc hc y2a ff5 fs9 fc0 sc0 ls7 ws0">• RTC with calendar function</div><div class="t m0 xc hc y2b ff5 fs9 fc0 sc0 ls7 ws0">• Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)</div><div class="t m0 xc hc y2c ff5 fs9 fc0 sc0 ls7 ws0">• 130 General Purpose I/O ports / 24-ch external interrupt source</div><div class="t m0 xc hc y2d ff5 fs9 fc0 sc0 ls7 ws0">• Power control: Normal, Slow, Idle and Sleep mode</div><div class="t m0 xc hc y2e ff5 fs9 fc0 sc0 ls7 ws0">• On-chip clock generator with PLL</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c3821ce083560b88131d5/bg3.jpg"><div class="t m0 x8 h7 y8 ff3 fs5 fc0 sc0 ls7 ws0">2004.06.03</div><div class="t m0 x9 h7 y9 ff3 fs5 fc0 sc0 ls7 ws0">Preliminary product information describes products that are in development,</div><div class="t m0 xa h7 ya ff3 fs5 fc0 sc0 ls7 ws0">for which full characterization data and associated errata are not yet available</div><div class="t m0 xb h7 yb ff3 fs5 fc0 sc0 ls7 ws0">Specifications and information herein are subject to change without notice.</div><div class="t m0 xf h8 yc ff4 fs5 fc0 sc0 ls1a ws0">PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR</div><div class="t m0 xf hd y2f ff4 fs4 fc0 sc0 ls6 ws0">1-2</div><div class="t m0 xf ha y30 ff4 fs8 fc0 sc0 ls1b ws0">FEATURES</div><div class="t m0 xf hd y31 ff4 fs4 fc0 sc0 ls16 ws0">Architecture</div><div class="t m0 xf hc y32 ff5 fs9 fc0 sc0 ls7 ws0">• Integrated system for hand-held devices and</div><div class="t m0 x10 hb y33 ff3 fs4 fc0 sc0 ls11 ws0">general embedded applications.</div><div class="t m0 xf hc y34 ff5 fs9 fc0 sc0 ls7 ws0">• 16/32-Bit RISC architecture and powerful</div><div class="t m0 x10 hb y35 ff3 fs4 fc0 sc0 lsc ws0">instruction set with ARM920T CPU core.</div><div class="t m0 xf hc y36 ff5 fs9 fc0 sc0 ls7 ws0">• Enhanced ARM architecture MMU to support</div><div class="t m0 x10 hb y37 ff3 fs4 fc0 sc0 ls1d ws0">WinCE, EPOC 32 and Linux.</div><div class="t m0 xf hc y38 ff5 fs9 fc0 sc0 ls7 ws0">• Instruction cache, data cache, write buffer and</div><div class="t m0 x10 hb y39 ff3 fs4 fc0 sc0 ls12 ws0">Physical address TAG RAM to reduce the effect</div><div class="t m0 x10 hb y3a ff3 fs4 fc0 sc0 ls12 ws0">of main memory bandwidth and latency on</div><div class="t m0 x10 hb y3b ff3 fs4 fc0 sc0 ls6 ws0">performance.</div><div class="t m0 xf hc y3c ff5 fs9 fc0 sc0 ls7 ws0">• ARM920T CPU core supports the ARM debug</div><div class="t m0 x10 hb y3d ff3 fs4 fc0 sc0 ls12 ws0">architecture.</div><div class="t m0 xf hc y3e ff5 fs9 fc0 sc0 ls7 ws0">• Internal Advanced Microcontroller Bus</div><div class="t m0 x10 hb y3f ff3 fs4 fc0 sc0 ls1f ws0">Architecture (AMBA) (AMBA2.0, AHB/APB).</div><div class="t m0 xf hd y40 ff4 fs4 fc0 sc0 ls19 ws0">System Manager</div><div class="t m0 xf hc y41 ff5 fs9 fc0 sc0 ls7 ws0">• Little/Big Endian support.</div><div class="t m0 xf hc y42 ff5 fs9 fc0 sc0 ls7 ws0">• Address space: 128M bytes for each bank (total</div><div class="t m0 x10 hb y43 ff3 fs4 fc0 sc0 ls6 ws0">1G bytes).</div><div class="t m0 xf hc y44 ff5 fs9 fc0 sc0 ls7 ws0">• Supports programmable 8/16/32-bit data bus</div><div class="t m0 x10 hb y45 ff3 fs4 fc0 sc0 ls6 ws0">width for each bank.</div><div class="t m0 xf hc y46 ff5 fs9 fc0 sc0 ls7 ws0">• Fixed bank start address from bank 0 to bank 6.</div><div class="t m0 xf hc y47 ff5 fs9 fc0 sc0 ls7 ws0">• Programmable bank start address and bank size</div><div class="t m0 x10 hb y48 ff3 fs4 fc0 sc0 ls6 ws0">for bank 7.</div><div class="t m0 xf hc y49 ff5 fs9 fc0 sc0 ls7 ws0">• Eight memory banks:</div><div class="t m0 x10 hb y4a ff3 fs4 fc0 sc0 lsd ws0">– Six memory banks for ROM, SRAM, and others.</div><div class="t m0 x10 hb y4b ff3 fs4 fc0 sc0 ls12 ws0">– Two memory banks for ROM/SRAM/</div><div class="t m0 x11 hb y4c ff3 fs4 fc0 sc0 ls10 ws0">Synchronous DRAM.</div><div class="t m0 xf hc y4d ff5 fs9 fc0 sc0 ls7 ws0">• Complete Programmable access cycles for all</div><div class="t m0 x10 hb y4e ff3 fs4 fc0 sc0 ls6 ws0">memory banks.</div><div class="t m0 xf hc y4f ff5 fs9 fc0 sc0 ls7 ws0">• Supports external wait signals to expand the bus</div><div class="t m0 x10 hb y50 ff3 fs4 fc0 sc0 ls20 ws0">cycle.</div><div class="t m0 xf hc y51 ff5 fs9 fc0 sc0 ls7 ws0">• Supports self-refresh mode in SDRAM for power-</div><div class="t m0 x10 hb y52 ff3 fs4 fc0 sc0 ls6 ws0">down.</div><div class="t m0 xf hc y53 ff5 fs9 fc0 sc0 ls7 ws0">• Supports various types of ROM for booting</div><div class="t m0 x10 hb y54 ff3 fs4 fc0 sc0 ls21 ws0">(NOR/NAND Flash, EEPROM, and others).</div><div class="t m0 x12 hd y55 ff4 fs4 fc0 sc0 ls22 ws0">NAND Flash Boot Loader</div><div class="t m0 x12 hc y32 ff5 fs9 fc0 sc0 ls7 ws0">• Supports booting from NAND flash memory.</div><div class="t m0 x12 hc y56 ff5 fs9 fc0 sc0 ls7 ws0">• 4KB internal buffer for booting.</div><div class="t m0 x12 hc y57 ff5 fs9 fc0 sc0 ls7 ws0">• Supports storage memory for NAND flash</div><div class="t m0 x13 hb y58 ff3 fs4 fc0 sc0 lsc ws0">memory after booting.</div><div class="t m0 x12 hc y59 ff5 fs9 fc0 sc0 ls7 ws0">• Supports Advanced NAND flash</div><div class="t m0 x12 hd y5a ff4 fs4 fc0 sc0 ls23 ws0">Cache Memory</div><div class="t m0 x12 hc y5b ff5 fs9 fc0 sc0 ls7 ws0">• 64-way set-associative cache with I-Cache</div><div class="t m0 x13 hb y5c ff3 fs4 fc0 sc0 lsc ws0">(16KB) and D-Cache (16KB).</div><div class="t m0 x12 hc y5d ff5 fs9 fc0 sc0 ls7 ws0">• 8words length per line with one valid bit and two</div><div class="t m0 x13 hb y5e ff3 fs4 fc0 sc0 ls26 ws0">dirty bits per line.</div><div class="t m0 x12 hc y5f ff5 fs9 fc0 sc0 ls7 ws0">• Pseudo random or round robin replacement</div><div class="t m0 x13 hb y60 ff3 fs4 fc0 sc0 lse ws0">algorithm.</div><div class="t m0 x12 hc y61 ff5 fs9 fc0 sc0 ls7 ws0">• Write-through or write-back cache operation to</div><div class="t m0 x13 hb y62 ff3 fs4 fc0 sc0 ls10 ws0">update the main memory.</div><div class="t m0 x12 hc y63 ff5 fs9 fc0 sc0 ls7 ws0">• The write buffer can hold 16 words of data and</div><div class="t m0 x13 hb y64 ff3 fs4 fc0 sc0 ls6 ws0">four addresses.</div><div class="t m0 x12 hd y65 ff4 fs4 fc0 sc0 ls27 ws0">Clock & Power Manager</div><div class="t m0 x12 hc y66 ff5 fs9 fc0 sc0 ls7 ws0">• On-chipMPLLandUPLL:</div><div class="t m0 x13 hb y67 ff3 fs4 fc0 sc0 ls12 ws0">UPLL generates the clock to operate USB</div><div class="t m0 x13 hb y68 ff3 fs4 fc0 sc0 ls19 ws0">Host/Device.</div><div class="t m0 x13 hb y69 ff3 fs4 fc0 sc0 ls1e ws0">MPLL generates the clock to operate MCU at</div><div class="t m0 x13 hb y6a ff3 fs4 fc0 sc0 ls6 ws0">maximum 533Mhz @ 1.35V.</div><div class="t m0 x12 hc y6b ff5 fs9 fc0 sc0 ls7 ws0">• Clock can be fed selectively to each function</div><div class="t m0 x13 hb y6c ff3 fs4 fc0 sc0 ls29 ws0">block by software.</div><div class="t m0 x12 hd y6d ff5 fs9 fc0 sc0 ls7 ws0">• Power mode: Normal, Slow, Idle, and Sleep</div><div class="t m0 x13 hb y6e ff3 fs4 fc0 sc0 ls6 ws0">mode</div><div class="t m0 x13 hd y6f ff4 fs4 fc0 sc0 ls2b ws0">Normal mode: Normal operating mode</div><div class="t m0 x13 hd y70 ff4 fs4 fc0 sc0 ls2a ws0">Slow mode: Low frequency clock without PLL</div><div class="t m0 x13 hd y71 ff4 fs4 fc0 sc0 ls2c ws0">Idle mode: The clock for only CPU is stopped.</div><div class="t m0 x13 hd y72 ff4 fs4 fc0 sc0 ls2d ws0">Sleep mode: The Core power including all</div><div class="t m0 x13 hb y73 ff3 fs4 fc0 sc0 ls18 ws0">peripherals is shut down.</div><div class="t m0 x12 hc y74 ff5 fs9 fc0 sc0 ls7 ws0">• Woken up by EINT[15:0] or RTC alarm interrupt</div><div class="t m0 x13 hb y75 ff3 fs4 fc0 sc0 ls6 ws0">from Sleep mode</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c3821ce083560b88131d5/bg4.jpg"><div class="t m0 x8 h7 y8 ff3 fs5 fc0 sc0 ls7 ws0">2004.06.03</div><div class="t m0 x9 h7 y9 ff3 fs5 fc0 sc0 ls7 ws0">Preliminary product information describes products that are in development,</div><div class="t m0 xa h7 ya ff3 fs5 fc0 sc0 ls7 ws0">for which full characterization data and associated errata are not yet available</div><div class="t m0 xb h7 yb ff3 fs5 fc0 sc0 ls7 ws0">Specifications and information herein are subject to change without notice.</div><div class="t m0 xc h8 yc ff4 fs5 fc0 sc0 ls8 ws0">S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW</div><div class="t m0 xd h8 yd ff4 fs5 fc0 sc0 ls9 ws0">1-3</div><div class="t m0 xc ha y30 ff4 fs8 fc0 sc0 ls2f ws0">FEATURES (Continued)</div><div class="t m0 xc hd y76 ff4 fs4 fc0 sc0 ls30 ws0">Interrupt Controller</div><div class="t m0 xc hc y32 ff5 fs9 fc0 sc0 ls7 ws0">• 60 Interrupt sources</div><div class="t m0 xe hb y33 ff3 fs4 fc0 sc0 lsc ws0">(One Watch dog timer, 5 timers, 9 UARTs, 24</div><div class="t m0 xe hb y77 ff3 fs4 fc0 sc0 ls13 ws0">external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC,</div><div class="t m0 xe hb y78 ff3 fs4 fc0 sc0 ls13 ws0">2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1</div><div class="t m0 xe hb y79 ff3 fs4 fc0 sc0 ls31 ws0">NAND and 2 Camera), 1 AC97</div><div class="t m0 xc hc y7a ff5 fs9 fc0 sc0 ls7 ws0">• Level/Edge mode on external interrupt source</div><div class="t m0 xc hc y7b ff5 fs9 fc0 sc0 ls7 ws0">• Programmable polarity of edge and level</div><div class="t m0 xc hc y7c ff5 fs9 fc0 sc0 ls7 ws0">• Supports Fast Interrupt request (FIQ) for very</div><div class="t m0 xe hb y7d ff3 fs4 fc0 sc0 lsc ws0">urgent interrupt request</div><div class="t m0 xc hd y7e ff4 fs4 fc0 sc0 ls32 ws0">Timer with Pulse Width Modulation (PWM)</div><div class="t m0 xc hc y7f ff5 fs9 fc0 sc0 ls7 ws0">• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal</div><div class="t m0 xe hb y80 ff3 fs4 fc0 sc0 ls19 ws0">timer with DMA-based or interrupt-based</div><div class="t m0 xe hb y81 ff3 fs4 fc0 sc0 lsc ws0">operation</div><div class="t m0 xc hc y82 ff5 fs9 fc0 sc0 ls7 ws0">• Programmable duty cycle, frequency, and polarity</div><div class="t m0 xc hc y83 ff5 fs9 fc0 sc0 ls7 ws0">• Dead-zone generation</div><div class="t m0 xc hc y84 ff5 fs9 fc0 sc0 ls7 ws0">• Supports external clock sources</div><div class="t m0 xc hd y85 ff4 fs4 fc0 sc0 ls33 ws0">RTC (Real Time Clock)</div><div class="t m0 xc hc y86 ff5 fs9 fc0 sc0 ls7 ws0">• Full clock feature: msec, second, minute, hour,</div><div class="t m0 xe hb y87 ff3 fs4 fc0 sc0 ls1c ws0">date, day, month, and year</div><div class="t m0 xc hc y88 ff5 fs9 fc0 sc0 ls7 ws0">• 32.768 KHz operation</div><div class="t m0 xc hc y89 ff5 fs9 fc0 sc0 ls7 ws0">• Alarm interrupt</div><div class="t m0 xc hc y8a ff5 fs9 fc0 sc0 ls7 ws0">• Time tick interrupt</div><div class="t m0 xc hd y8b ff4 fs4 fc0 sc0 ls34 ws0">General Purpose Input/Output Ports</div><div class="t m0 xc hc y8c ff5 fs9 fc0 sc0 ls7 ws0">• 24 external interrupt ports</div><div class="t m0 xc hc y8d ff5 fs9 fc0 sc0 ls7 ws0">• Multiplexed input/output ports</div><div class="t m0 xc hd y8e ff4 fs4 fc0 sc0 ls35 ws0">DMA Controller</div><div class="t m0 xc hc y8f ff5 fs9 fc0 sc0 ls7 ws0">• 4-ch DMA controller</div><div class="t m0 xc hc y90 ff5 fs9 fc0 sc0 ls7 ws0">• Supports memory to memory, IO to memory,</div><div class="t m0 xe hb y91 ff3 fs4 fc0 sc0 ls36 ws0">memory to IO, and IO to IO transfers</div><div class="t m0 xc hc y92 ff5 fs9 fc0 sc0 ls7 ws0">• Burst transfer mode to enhance the transfer rate</div><div class="t m0 xc hd y93 ff4 fs4 fc0 sc0 ls37 ws0">LCD Controller STN LCD Displays Feature</div><div class="t m0 xc hc y94 ff5 fs9 fc0 sc0 ls7 ws0">• Supports 3 types of STN LCD panels: 4-bit dual</div><div class="t m0 xe hb y95 ff3 fs4 fc0 sc0 ls38 ws0">scan, 4-bit single scan, 8-bit single scan display</div><div class="t m0 xe hb y96 ff3 fs4 fc0 sc0 ls27 ws0">type</div><div class="t m0 xc hc y97 ff5 fs9 fc0 sc0 ls7 ws0">• Supports monochrome mode, 4 gray levels, 16</div><div class="t m0 x14 hb y98 ff3 fs4 fc0 sc0 ls1f ws0">gray levels, 256 colors and 4096 colors for STN</div><div class="t m0 x14 hb y99 ff3 fs4 fc0 sc0 ls39 ws0">LCD</div><div class="t m0 x15 hc y9a ff5 fs9 fc0 sc0 ls7 ws0">• Supports multiple screen size</div><div class="t m0 x16 hb y9b ff3 fs4 fc0 sc0 ls12 ws0">– Typical actual screen size: 640x480, 320x240,</div><div class="t m0 x17 hb y9c ff3 fs4 fc0 sc0 ls6 ws0">160x160, and others.</div><div class="t m0 x16 hb y9d ff3 fs4 fc0 sc0 ls3b ws0">– Maximum frame buffer size is 4 Mbytes.</div><div class="t m0 x16 hb y9e ff3 fs4 fc0 sc0 ls38 ws0">– Maximum virtual screen size in 256 color mode:</div><div class="t m0 x17 hb y9f ff3 fs4 fc0 sc0 ls6 ws0">4096x1024, 2048x2048, 1024x4096 and others</div><div class="t m0 x15 hd ya0 ff4 fs4 fc0 sc0 ls3c ws0">TFT(Thin Film Transistor) Color Displays Feature</div><div class="t m0 x15 hc ya1 ff5 fs9 fc0 sc0 ls7 ws0">• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette</div><div class="t m0 x14 hb ya2 ff3 fs4 fc0 sc0 ls3a ws0">color displays for color TFT</div><div class="t m0 x15 hc ya3 ff5 fs9 fc0 sc0 ls7 ws0">• Supports 16, 24 bpp non-palette true-color</div><div class="t m0 x14 hb ya4 ff3 fs4 fc0 sc0 ls21 ws0">displays for color TFT</div><div class="t m0 x15 hc ya5 ff5 fs9 fc0 sc0 ls7 ws0">• Supports maximum 16M color TFT at 24 bpp</div><div class="t m0 x14 hb ya6 ff3 fs4 fc0 sc0 ls3d ws0">mode</div><div class="t m0 x15 hc ya7 ff5 fs9 fc0 sc0 ls7 ws0">• LPC3600 Timing controller embedded for</div><div class="t m0 x14 hb ya8 ff3 fs4 fc0 sc0 lsc ws0">LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait /</div><div class="t m0 x14 hb ya9 ff3 fs4 fc0 sc0 ls1f ws0">256K-color/ Reflective a-Si TFT LCD)</div><div class="t m0 x15 hc yaa ff5 fs9 fc0 sc0 ls7 ws0">• LCC3600 Timing controller embedded for</div><div class="t m0 x14 hb yab ff3 fs4 fc0 sc0 ls19 ws0">LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait /</div><div class="t m0 x14 hb yac ff3 fs4 fc0 sc0 ls10 ws0">256K-color/ Transflective a-Si TFT LCD)</div><div class="t m0 x15 hc yad ff5 fs9 fc0 sc0 ls7 ws0">• Supports multiple screen size</div><div class="t m0 x16 hb yae ff3 fs4 fc0 sc0 ls12 ws0">– Typical actual screen size: 640x480, 320x240,</div><div class="t m0 x17 hb yaf ff3 fs4 fc0 sc0 ls6 ws0">160x160, and others.</div><div class="t m0 x16 hb yb0 ff3 fs4 fc0 sc0 ls3b ws0">– Maximum frame buffer size is 4Mbytes.</div><div class="t m0 x16 hb yb1 ff3 fs4 fc0 sc0 ls3e ws0">– Maximum virtual screen size in 64K color mode :</div><div class="t m0 x17 hb yb2 ff3 fs4 fc0 sc0 ls17 ws0">2048x1024, and others</div><div class="t m0 x15 hd yb3 ff4 fs4 fc0 sc0 ls2b ws0">UART</div><div class="t m0 x15 hc yb4 ff5 fs9 fc0 sc0 ls7 ws0">• 3-channel UART with DMA-based or interrupt-</div><div class="t m0 x14 hb yb5 ff3 fs4 fc0 sc0 ls18 ws0">based operation</div><div class="t m0 x15 hc yb6 ff5 fs9 fc0 sc0 ls7 ws0">• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data</div><div class="t m0 x14 hb yb7 ff3 fs4 fc0 sc0 ls13 ws0">transmit/receive (Tx/Rx)</div><div class="t m0 x15 hc yb8 ff5 fs9 fc0 sc0 ls7 ws0">• Supports external clocks for the UART operation</div><div class="t m0 x14 hb yb9 ff3 fs4 fc0 sc0 ls3f ws0">(UEXTCLK)</div><div class="t m0 x15 hc yba ff5 fs9 fc0 sc0 ls7 ws0">• Programmable baud rate</div><div class="t m0 x15 hc ybb ff5 fs9 fc0 sc0 ls7 ws0">• Supports IrDA 1.0</div><div class="t m0 x15 hc ybc ff5 fs9 fc0 sc0 ls7 ws0">• Loopback mode for testing</div><div class="t m0 x15 hc ybd ff5 fs9 fc0 sc0 ls7 ws0">• Each channel has internal 64-byte Tx FIFO and</div><div class="t m0 x14 hb ybe ff3 fs4 fc0 sc0 ls13 ws0">64-byte Rx FIFO.</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/628c3821ce083560b88131d5/bg5.jpg"><div class="t m0 x8 h7 y8 ff3 fs5 fc0 sc0 ls7 ws0">2004.06.03</div><div class="t m0 x9 h7 y9 ff3 fs5 fc0 sc0 ls7 ws0">Preliminary product information describes products that are in development,</div><div class="t m0 xa h7 ya ff3 fs5 fc0 sc0 ls7 ws0">for which full characterization data and associated errata are not yet available</div><div class="t m0 xb h7 yb ff3 fs5 fc0 sc0 ls7 ws0">Specifications and information herein are subject to change without notice.</div><div class="t m0 xf h8 yc ff4 fs5 fc0 sc0 ls1a ws0">PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR</div><div class="t m0 xf hd y2f ff4 fs4 fc0 sc0 ls6 ws0">1-4</div><div class="t m0 xf ha y30 ff4 fs8 fc0 sc0 ls1b ws0">FEATURES (Continued)</div><div class="t m0 xf hd y76 ff4 fs4 fc0 sc0 ls12 ws0">A/D Converter & Touch Screen Interface</div><div class="t m0 xf hc ybf ff5 fs9 fc0 sc0 ls7 ws0">• 8-ch multiplexed ADC</div><div class="t m0 xf hc yc0 ff5 fs9 fc0 sc0 ls7 ws0">• Max. 500KSPS and 10-bit Resolution</div><div class="t m0 xf hc yc1 ff5 fs9 fc0 sc0 ls7 ws0">• Internal FET for direct Touch screen interface</div><div class="t m0 xf hd yc2 ff4 fs4 fc0 sc0 ls41 ws0">Watchdog Timer</div><div class="t m0 xf hc yc3 ff5 fs9 fc0 sc0 ls7 ws0">• 16-bit Watchdog Timer</div><div class="t m0 xf hc yc4 ff5 fs9 fc0 sc0 ls7 ws0">• Interrupt request or system reset at time-out</div><div class="t m0 xf hd yc5 ff4 fs4 fc0 sc0 ls36 ws0">IIC-Bus Interface</div><div class="t m0 xf hc yc6 ff5 fs9 fc0 sc0 ls7 ws0">• 1-ch Multi-Master IIC-Bus</div><div class="t m0 xf hc yc7 ff5 fs9 fc0 sc0 ls7 ws0">• Serial, 8-bit oriented and bi-directional data</div><div class="t m0 x10 hb yc8 ff3 fs4 fc0 sc0 ls11 ws0">transfers can be made at up to 100 Kbit/s in</div><div class="t m0 x10 hb yc9 ff3 fs4 fc0 sc0 ls12 ws0">Standard mode or up to 400 Kbit/s in Fast mode.</div><div class="t m0 xf hd yca ff4 fs4 fc0 sc0 ls42 ws0">IIS-Bus Interface</div><div class="t m0 xf hc ycb ff5 fs9 fc0 sc0 ls7 ws0">• 1-ch IIS-bus for audio interface with DMA-based</div><div class="t m0 x10 hb ycc ff3 fs4 fc0 sc0 lsc ws0">operation</div><div class="t m0 xf hc ycd ff5 fs9 fc0 sc0 ls7 ws0">• Serial, 8-/16-bit per channel data transfers</div><div class="t m0 xf hc yce ff5 fs9 fc0 sc0 ls7 ws0">• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx</div><div class="t m0 xf hc ycf ff5 fs9 fc0 sc0 ls7 ws0">• Supports IIS format and MSB-justified data format</div><div class="t m0 xf hd yd0 ff4 fs4 fc0 sc0 ls1e ws0">AC97 Audio-CODEC Interface</div><div class="t m0 xf hc yd1 ff5 fs9 fc0 sc0 ls7 ws0">• Support 16-bit samples</div><div class="t m0 xf hc yd2 ff5 fs9 fc0 sc0 ls7 ws0">• 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs</div><div class="t m0 x10 hb yd3 ff3 fs4 fc0 sc0 ls6 ws0">1-ch MIC input</div><div class="t m0 xf hd yd4 ff4 fs4 fc0 sc0 ls43 ws0">USB Host</div><div class="t m0 xf hc yd5 ff5 fs9 fc0 sc0 ls7 ws0">• 2-port USB Host</div><div class="t m0 xf hc yd6 ff5 fs9 fc0 sc0 ls7 ws0">• Complies with OHCI Rev. 1.0</div><div class="t m0 xf hc yd7 ff5 fs9 fc0 sc0 ls7 ws0">• Compatible with USB Specification version 1.1</div><div class="t m0 xf hd yd8 ff4 fs4 fc0 sc0 ls1c ws0">USB Device</div><div class="t m0 xf hc yd9 ff5 fs9 fc0 sc0 ls7 ws0">• 1-port USB Device</div><div class="t m0 xf hc yda ff5 fs9 fc0 sc0 ls7 ws0">• 5 Endpoints for USB Device</div><div class="t m0 xf hc ydb ff5 fs9 fc0 sc0 ls7 ws0">• Compatible with USB Specification version 1.1</div><div class="t m0 xf hd ydc ff4 fs4 fc0 sc0 ls18 ws0">SD Host Interface</div><div class="t m0 xf hc ydd ff5 fs9 fc0 sc0 ls7 ws0">• Normal, Interrupt and DMA data transfer</div><div class="t m0 x10 hb yde ff3 fs4 fc0 sc0 ls6 ws0">mode(byte, halfword, word transfer)</div><div class="t m0 x12 hc ydf ff5 fs9 fc0 sc0 ls7 ws0">• DMA burst4 access support(only word transfer)</div><div class="t m0 x12 hc ybf ff5 fs9 fc0 sc0 ls7 ws0">• Compatible with SD Memory Card Protocol</div><div class="t m0 x13 hb ye0 ff3 fs4 fc0 sc0 ls44 ws0">version 1.0</div><div class="t m0 x12 hc ye1 ff5 fs9 fc0 sc0 ls7 ws0">• Compatible with SDIO Card Protocol version 1.0</div><div class="t m0 x12 hc ye2 ff5 fs9 fc0 sc0 ls7 ws0">• 64 Bytes FIFO for Tx/Rx</div><div class="t m0 x12 hc ye3 ff5 fs9 fc0 sc0 ls7 ws0">• Compatible with Multimedia Card Protocol version</div><div class="t m0 x13 hb ye4 ff3 fs4 fc0 sc0 ls26 ws0">2.11</div><div class="t m0 x12 hd ye5 ff4 fs4 fc0 sc0 ls3b ws0">SPI Interface</div><div class="t m0 x12 hc ye6 ff5 fs9 fc0 sc0 ls7 ws0">• Compatible with 2-ch Serial Peripheral Interface</div><div class="t m0 x13 hb ye7 ff3 fs4 fc0 sc0 ls19 ws0">Protocol version 2.11</div><div class="t m0 x12 hc yc7 ff5 fs9 fc0 sc0 ls7 ws0">• 2x8 bits Shift register for Tx/Rx</div><div class="t m0 x12 hc ye8 ff5 fs9 fc0 sc0 ls7 ws0">• DMA-based or interrupt-based operation</div><div class="t m0 x12 hd ye9 ff4 fs4 fc0 sc0 lsf ws0">Camera Interface</div><div class="t m0 x12 hc yea ff5 fs9 fc0 sc0 ls7 ws0">• ITU-R BT 601/656 8-bit mode support</div><div class="t m0 x12 hc yeb ff5 fs9 fc0 sc0 ls7 ws0">• DZI (Digital Zoom In) capability</div><div class="t m0 x12 hc ycd ff5 fs9 fc0 sc0 ls7 ws0">• Programmable polarity of video sync signals</div><div class="t m0 x12 hc yce ff5 fs9 fc0 sc0 ls7 ws0">• Max. 4096 x 4096 pixels input support ( 2048 x</div><div class="t m0 x13 hb yec ff3 fs4 fc0 sc0 lsc ws0">2048 pixel input support for scaling)</div><div class="t m0 x12 hc yed ff5 fs9 fc0 sc0 ls7 ws0">• Image mirror and rotation (X-axis mirror, Y-axis</div><div class="t m0 x13 hb yee ff3 fs4 fc0 sc0 ls12 ws0">mirror, and 180° rotation)</div><div class="t m0 x12 hc yef ff5 fs9 fc0 sc0 ls7 ws0">• Camera output format (RGB 16/24-bit and YCbCr</div><div class="t m0 x13 hb yf0 ff3 fs4 fc0 sc0 ls27 ws0">4:2:0/4:2:2 format)</div><div class="t m0 x12 hd yf1 ff4 fs4 fc0 sc0 ls3c ws0">Operating Voltage Range</div><div class="t m0 x12 hc yf2 ff5 fs9 fc0 sc0 ls7 ws0">• Core : 1.20V for 300MHz</div><div class="t m0 x18 hb yf3 ff3 fs4 fc0 sc0 ls1e ws0">1.30V for 400MHz</div><div class="t m0 x18 hb yf4 ff3 fs4 fc0 sc0 ls1e ws0">1.35V for 533MHz</div><div class="t m0 x12 hc yf5 ff5 fs9 fc0 sc0 ls7 ws0">• Memory:1.8V/ 2.5V/3.0V/3.3V</div><div class="t m0 x12 hc yf6 ff5 fs9 fc0 sc0 ls7 ws0">• I/O : 3.3V</div><div class="t m0 x12 hd yf7 ff4 fs4 fc0 sc0 ls47 ws0">Operating Frequency</div><div class="t m0 x12 hc yf8 ff5 fs9 fc0 sc0 ls7 ws0">• Fclk Up to 533MHz</div><div class="t m0 x12 hc yf9 ff5 fs9 fc0 sc0 ls7 ws0">• Hclk Up to 136MHz</div><div class="t m0 x12 hc yfa ff5 fs9 fc0 sc0 ls7 ws0">• Pclk Up to 68MHz</div><div class="t m0 x12 hd yfb ff4 fs4 fc0 sc0 lsc ws0">Package</div><div class="t m0 x12 hc yfc ff5 fs9 fc0 sc0 ls7 ws0">• 289-FBGA</div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>