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嵌入式arm开发
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<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/62f651cdf97302478e3fa302/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/62f651cdf97302478e3fa302/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y6 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3 h2 y7 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3 h2 y8 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h2 y9 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m1 x5 h3 ya ff1 fs1 fc0 sc0 ls1 ws1">September 2009<span class="_ _0"> </span>Doc ID 14611 Rev <span class="_ _1"></span>7<span class="_ _2"> </span>1/123</div><div class="t m1 x6 h4 yb ff1 fs2 fc1 sc0 ls0 ws0">1</div><div class="t m1 x7 h5 yc ff2 fs3 fc0 sc0 ls2 ws2">STM32F103xC STM32F103xD</div><div class="t m1 x8 h5 yd ff2 fs3 fc0 sc0 ls3 ws0">STM32F103xE</div><div class="t m1 x9 h6 ye ff1 fs4 fc0 sc0 ls0 ws3">High-density perf<span class="_ _1"></span>ormance line AR<span class="ls4 ws4">M-based 32-bit MCU with 256 to</span></div><div class="t m2 x5 h6 yf ff1 fs4 fc0 sc0 ls5 ws5">512KB Flash, USB<span class="_ _1"></span>, CAN, 11 timers, <span class="ls6 ws6">3 ADCs<span class="_ _1"></span>, 13 comm<span class="_ _1"></span>unication interf<span class="_ _1"></span>aces</span></div><div class="t m1 x5 h7 y10 ff2 fs5 fc0 sc0 ls7 ws0">Features</div><div class="t m1 x5 h8 y11 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls8 ws7">Core: ARM 32-bit <span class="_ _1"></span><span class="ls9 ws0">Cortex&#8482;-M3 C<span class="_ _4"></span>PU</span></span></div><div class="t m1 xa h8 y12 ff1 fs7 fc0 sc0 lsa ws8">&#8211;<span class="_ _5"> </span>72 MHz maximum frequency<span class="_ _6"></span>, </div><div class="t m1 xb h8 y13 ff1 fs7 fc0 sc0 lsb ws9">1.25<span class="_"> </span>DMIPS/MHz (Dhrystone 2.1) </div><div class="t m1 xb h8 y14 ff1 fs7 fc0 sc0 lsc wsa">perf<span class="_ _1"></span>ormance at 0 wait stat<span class="_ _1"></span>e memory </div><div class="t m1 xb h8 y15 ff1 fs7 fc0 sc0 lsd ws0">access</div><div class="t m1 xa h8 y16 ff1 fs7 fc0 sc0 lse wsb">&#8211;<span class="_ _5"> </span>Single-cycle multiplication and hardware </div><div class="t m1 xb h8 y17 ff1 fs7 fc0 sc0 lsf ws0">division</div><div class="t m1 x5 h8 y18 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls10">Memories</span></div><div class="t m1 xa h8 y19 ff1 fs7 fc0 sc0 ls11 wsc">&#8211;<span class="_ _5"> </span>256 to 512 Kb<span class="_ _1"></span>yte<span class="_ _1"></span>s of Flash memory</div><div class="t m1 xa h8 y1a ff1 fs7 fc0 sc0 ls11 wsd">&#8211;<span class="_ _5"> </span>up to 64 Kb<span class="_ _1"></span>ytes of SRAM</div><div class="t m1 xa h8 y1b ff1 fs7 fc0 sc0 ls12 wse">&#8211;<span class="_ _5"> </span>Flexib<span class="_ _1"></span>le static memory controller with 4 </div><div class="t m1 xb h8 y1c ff1 fs7 fc0 sc0 ls13 wsf">Chip Select. <span class="_ _4"></span>Suppor<span class="_ _4"></span>ts C<span class="_ _4"></span>ompact Flash,<span class="_ _4"></span> </div><div class="t m3 xb h8 y1d ff1 fs7 fc0 sc0 ls14 ws10">SRAM, PSRAM, NOR and NAND</div><div class="t m1 xc h8 y1d ff1 fs7 fc0 sc0 ls10 ws11"> memories</div><div class="t m1 xa h8 y1e ff1 fs7 fc0 sc0 ls15 ws12">&#8211;<span class="_ _5"> </span>LCD parallel interf<span class="_ _1"></span>a<span class="_ _1"></span>ce, 8080/<span class="_ _1"></span>6800 modes</div><div class="t m1 x5 h8 y1f ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls16 ws13">Clock, reset and supply mana<span class="_ _1"></span>gement</span></div><div class="t m1 xa h8 y20 ff1 fs7 fc0 sc0 ls11 wsc">&#8211;<span class="_ _5"> </span>2.0 to 3.6<span class="_"> </span>V applica<span class="_ _1"></span>tion supply and I<span class="_ _1"></span>/Os </div><div class="t m1 xa h8 y21 ff1 fs7 fc0 sc0 lsc wsa">&#8211;<span class="_ _5"> </span>POR, PDR, and prog<span class="_ _1"></span>rammab<span class="_ _1"></span>le v<span class="_ _1"></span>olta<span class="_ _1"></span>ge </div><div class="t m1 xb h8 y22 ff1 fs7 fc0 sc0 ls17 ws14">detector (PVD)</div><div class="t m1 xa h8 y23 ff1 fs7 fc0 sc0 ls18 ws15">&#8211;<span class="_ _5"> </span>4-to-16 MHz cr<span class="_ _4"></span>ystal oscillator </div><div class="t m1 xa h8 y24 ff1 fs7 fc0 sc0 ls19 ws16">&#8211;<span class="_ _5"> </span>Inter<span class="_ _4"></span>nal 8 M<span class="_ _4"></span>Hz factory-t<span class="_ _4"></span>rimme<span class="_ _4"></span>d RC</div><div class="t m1 xa h8 y25 ff1 fs7 fc0 sc0 ls1a ws17">&#8211;<span class="_ _5"> </span>Inter<span class="_ _4"></span>nal 40 kHz RC with calibration </div><div class="t m1 xa h8 y26 ff1 fs7 fc0 sc0 ls1b ws18">&#8211;<span class="_ _5"> </span>32 kHz oscillator for R<span class="_ _7"></span>TC with calibration</div><div class="t m1 x5 h8 y27 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls1c ws19">Low power</span></div><div class="t m1 xa h8 y28 ff1 fs7 fc0 sc0 ls1d ws1a">&#8211;<span class="_ _5"> </span>Sleep<span class="_ _7"></span>, Stop and Standby mod<span class="_ _1"></span>es</div><div class="t m1 xa h8 y29 ff1 fs7 fc0 sc0 ls1e ws0">&#8211;V</div><div class="t m1 xd h9 y2a ff1 fs6 fc0 sc0 ls1f ws0">BA<span class="_ _6"></span>T</div><div class="t m1 xe h8 y2b ff1 fs7 fc0 sc0 ls16 ws13"> supply f<span class="_ _7"></span>or RTC and ba<span class="_ _1"></span>ckup re<span class="_ _1"></span>gisters</div><div class="t m1 x5 h8 y2c ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 lsb ws9">3 &#215; 12-bit, 1 &#181;s A/D converters (<span class="_ _1"></span>up to 21 </span></div><div class="t m1 xa h8 y2d ff1 fs7 fc0 sc0 ls20 ws0">channels)</div><div class="t m1 xa h8 y2e ff1 fs7 fc0 sc0 ls21 ws1b">&#8211;<span class="_ _5"> </span>Conversion range: 0 to 3.6 V</div><div class="t m1 xa h8 y2f ff1 fs7 fc0 sc0 ls12 wse">&#8211;<span class="_ _5"> </span>T<span class="_ _6"></span>riple-sample and hold capability</div><div class="t m1 xa h8 y30 ff1 fs7 fc0 sc0 ls22 ws1c">&#8211;<span class="_ _5"> </span>T<span class="_ _6"></span>empera<span class="_ _1"></span>ture sensor</div><div class="t m1 x5 h8 y31 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls23 ws1d">2 &#215; 12-bit D/A conver<span class="_ _1"></span>ters</span></div><div class="t m1 x5 h8 y32 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls1d ws1a">DMA: 12-channel<span class="ls24 ws1e"> DMA controller</span></span></div><div class="t m1 xa h8 y33 ff1 fs7 fc0 sc0 ls25 ws1f">&#8211;<span class="_ _5"> </span>Suppor<span class="_ _4"></span>ted peripheral<span class="_ _1"></span>s: timers<span class="_ _1"></span>, ADCs,<span class="_ _1"></span> D<span class="_ _7"></span>AC<span class="_ _7"></span>, </div><div class="t m1 xb h8 y34 ff1 fs7 fc0 sc0 ls0 ws20">SDIO<span class="_ _1"></span>, I</div><div class="t m1 xf h9 y35 ff1 fs6 fc0 sc0 ls0 ws0">2</div><div class="t m1 x10 h8 y36 ff1 fs7 fc0 sc0 ls26 ws21">Ss, SPIs, I</div><div class="t m1 x11 h9 y35 ff1 fs6 fc0 sc0 ls0 ws0">2</div><div class="t m1 x12 h8 y36 ff1 fs7 fc0 sc0 ls23 ws1d">Cs and USAR<span class="_ _7"></span>Ts</div><div class="t m1 x5 h8 y37 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls25 wsd">Debug mode</span></div><div class="t m1 xa h8 y38 ff1 fs7 fc0 sc0 ls27 ws22">&#8211;<span class="_ _5"> </span>Serial wire debug (SWD) &amp; JT<span class="_ _6"></span>AG interf<span class="_ _7"></span>aces</div><div class="t m1 xa h8 y39 ff1 fs7 fc0 sc0 ls28 ws23">&#8211;<span class="_ _5"> </span>Cor<span class="_ _4"></span>te<span class="_ _7"></span>x-M3 Embedded T<span class="_ _6"></span>r<span class="_ _1"></span>ace Macrocell<span class="_ _1"></span>&#8482;</div><div class="t m1 x13 h8 y3a ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls29 ws24">Up to 112 fa<span class="_ _4"></span>st I/O ports</span></div><div class="t m1 x14 h8 y3b ff1 fs7 fc0 sc0 ls2a ws25">&#8211;<span class="_ _5"> </span>51/80/112 I/<span class="_ _1"></span>Os, all ma<span class="_ _1"></span>ppabl<span class="_ _1"></span>e on 16 </div><div class="t m1 x15 h8 y3c ff1 fs7 fc0 sc0 ls20 ws26">e<span class="_ _1"></span>xternal interrupt vector<span class="_ _1"></span>s and almost all </div><div class="t m1 x15 h8 y3d ff1 fs7 fc0 sc0 ls2b ws0">5<span class="_"> </span>V<span class="_ _7"></span>-tolerant</div><div class="t m1 x13 h8 y3e ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls29 ws24">Up to 11 time<span class="_ _4"></span>rs</span></div><div class="t m1 x14 h8 y3f ff1 fs7 fc0 sc0 lsc wsa">&#8211;<span class="_ _5"> </span>Up to f<span class="_ _7"></span>our 16-bit timers<span class="_ _7"></span>, each with up to 4 </div><div class="t m1 x15 h8 y40 ff1 fs7 fc0 sc0 ls8 ws7">IC/OC/PWM or pu<span class="_ _1"></span>lse counter <span class="_ _1"></span>and </div><div class="t m1 x15 h8 y41 ff1 fs7 fc0 sc0 ls1d ws7">quadrat<span class="_ _1"></span>ure (incremental)<span class="_ _1"></span> encoder input</div><div class="t m1 x14 h8 y42 ff1 fs7 fc0 sc0 ls2c ws27">&#8211;<span class="_ _5"> </span>2 &#215; 16-bit <span class="_ _4"></span>motor cont<span class="_ _4"></span>rol PWM timers<span class="_ _4"></span> with </div><div class="t m1 x15 h8 y43 ff1 fs7 fc0 sc0 ls2a ws25">dead-time ge<span class="_ _1"></span>neration an<span class="_ _1"></span>d emergency stop</div><div class="t m1 x14 h8 y44 ff1 fs7 fc0 sc0 ls25 wsd">&#8211;<span class="_ _5"> </span>2 &#215; watchdog<span class="_ _1"></span> timers (Independ<span class="_ _1"></span>ent and </div><div class="t m1 x15 h8 y45 ff1 fs7 fc0 sc0 ls2d ws0">Window)</div><div class="t m1 x14 h8 y46 ff1 fs7 fc0 sc0 ls16 ws13">&#8211;<span class="_ _5"> </span>SysTick<span class="_ _1"></span> timer: a 24-bit downcounter</div><div class="t m1 x14 h8 y47 ff1 fs7 fc0 sc0 ls2e ws28">&#8211;<span class="_ _5"> </span>2 &#215; 16-bit basic timer<span class="_ _4"></span>s to drive the D<span class="_ _7"></span>AC</div><div class="t m1 x13 h8 y48 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls2c ws27">Up to 13 com<span class="_ _4"></span>munication inte<span class="_ _4"></span>rfaces</span></div><div class="t m1 x14 h8 y49 ff1 fs7 fc0 sc0 ls20 ws29">&#8211;<span class="_ _5"> </span>Up to 2 &#215; <span class="_ _1"></span>I</div><div class="t m1 x16 h9 y4a ff1 fs6 fc0 sc0 ls0 ws0">2</div><div class="t m1 x17 h8 y4b ff1 fs7 fc0 sc0 ls2d ws2a">C interf<span class="_ _7"></span>aces (SMBus/PMBus)</div><div class="t m1 x14 h8 y4c ff1 fs7 fc0 sc0 ls2e ws28">&#8211;<span class="_ _5"> </span>Up to 5 USARTs (ISO 7816 interface<span class="_ _1"></span>, LIN, </div><div class="t m1 x15 h8 y4d ff1 fs7 fc0 sc0 ls1b ws18">IrD<span class="_ _7"></span>A capability<span class="_ _7"></span>,<span class="_ _1"></span> modem control)</div><div class="t m1 x14 h8 y4e ff1 fs7 fc0 sc0 ls2c ws2b">&#8211;<span class="_ _5"> </span>Up to 3 SPIs (18 Mbit/s),<span class="_ _4"></span> 2 with I</div><div class="t m1 x18 h9 y4f ff1 fs6 fc0 sc0 ls0 ws0">2</div><div class="t m1 x19 h8 y50 ff1 fs7 fc0 sc0 ls1b ws0">S </div><div class="t m1 x15 h8 y51 ff1 fs7 fc0 sc0 ls18 ws15">interf<span class="_ _1"></span>ace multiple<span class="_ _7"></span>xed</div><div class="t m1 x14 h8 y52 ff1 fs7 fc0 sc0 ls2f ws2c">&#8211;<span class="_ _5"> </span>CAN interface (2.0B Active)</div><div class="t m1 x14 h8 y53 ff1 fs7 fc0 sc0 ls15 ws12">&#8211;<span class="_ _5"> </span>USB 2.0 full speed interf<span class="_ _7"></span>ace</div><div class="t m1 x14 h8 y54 ff1 fs7 fc0 sc0 ls30 ws2d">&#8211;<span class="_ _5"> </span>SDIO interf<span class="_ _7"></span>ace</div><div class="t m1 x13 h8 y55 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls31 ws2e">CRC calculation unit, 96-bit unique ID</span></div><div class="t m1 x13 h8 y56 ff3 fs6 fc0 sc0 ls0 ws0">&#9632;<span class="_ _3"> </span><span class="ff1 fs7 ls32">ECOPACK</span></div><div class="t m1 x1a h9 y57 ff1 fs6 fc0 sc0 ls0 ws0">&#174;</div><div class="t m1 x1b h8 y56 ff1 fs7 fc0 sc0 ls11 wsc"> packages</div><div class="t m1 x13 ha y58 ff1 fs8 fc0 sc0 ls33 ws0"> </div><div class="t m1 x13 hb y59 ff2 fs7 fc0 sc0 ls22 ws1c">T<span class="_ _8"></span>able 1.<span class="_ _9"> </span>Device<span class="_ _1"></span> summary</div><div class="t m1 x14 hc y5a ff2 fs1 fc0 sc0 ls34 ws2f">Reference<span class="_ _a"> </span>P<span class="_ _1"></span>art number</div><div class="t m1 x1c h3 y5b ff1 fs1 fc0 sc0 ls35 ws0">STM32F103xC</div><div class="t m1 x1d h3 y5c ff1 fs1 fc0 sc0 ls36 ws30">STM32F103RC STM32F103VC </div><div class="t m1 x1d h3 y5d ff1 fs1 fc0 sc0 ls37 ws0">STM32F103ZC</div><div class="t m1 x1c h3 y5e ff1 fs1 fc0 sc0 ls35 ws0">STM32F103xD</div><div class="t m1 x1d h3 y5f ff1 fs1 fc0 sc0 ls36 ws30">STM32F103RD STM32F103VD </div><div class="t m1 x1d h3 y60 ff1 fs1 fc0 sc0 ls37 ws0">STM32F103ZD</div><div class="t m1 x1c h3 y61 ff1 fs1 fc0 sc0 ls35 ws0">STM32F103xE</div><div class="t m1 x1d h3 y62 ff1 fs1 fc0 sc0 ls38 ws0">STM32F103RE <span class="ls36">STM32F103ZE </span></div><div class="t m1 x1d h3 y63 ff1 fs1 fc0 sc0 ls37 ws0">STM32F103VE</div><div class="c x1e y64 w2 hd"><div class="t m4 x1f he y65 ff1 fs9 fc1 sc0 ls39 ws0">FBGA</div></div><div class="c x13 y66 w3 hf"><div class="t m1 x20 h4 y67 ff1 fs2 fc0 sc0 ls3a ws31">LQFP64 10 &#215; 10 <span class="_ _1"></span>mm, </div><div class="t m1 x21 h4 y68 ff1 fs2 fc0 sc0 ls3a ws32">LQFP100 14 &#215; 14 mm, </div><div class="t m1 x22 h4 y69 ff1 fs2 fc0 sc0 ls3b ws32">LQFP144 20 &#215; 20 mm</div><div class="t m1 x23 h4 y6a ff1 fs2 fc0 sc0 ls3c ws33">LFBGA100 10 &#215; 10 <span class="_ _1"></span>mm</div><div class="t m1 x23 h4 y6b ff1 fs2 fc0 sc0 ls3c ws33">LFBGA144 10 &#215; 10 <span class="_ _1"></span>mm</div><div class="t m1 x24 h4 y6c ff1 fs2 fc0 sc0 ls3d ws0">WLCSP64</div></div><div class="t m1 x25 h10 yb ff4 fs2 fc2 sc0 ls3e ws0">www<span class="_ _7"></span>.st.c<span class="_ _4"></span>om</div><a class="l" rel='nofollow' onclick='return false;'><div class="d m5"></div></a><div class="d m5"></div></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div> </body> </html>
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