Zynq7000 User Guide合集.rar_ide_其他

<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/626601d44c65f41259243370/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626601d44c65f41259243370/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Z<span class="_ _0"></span>ynq-7000 <span class="_ _1"></span>SoC</div><div class="t m0 x1 h3 y2 ff2 fs1 fc0 sc0 ls1 ws1">Technical Reference Manual</div><div class="t m0 x1 h4 y3 ff1 fs2 fc0 sc0 ls2 ws0">UG585 (v1.12.2) July 1, 2018</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div> </body> </html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626601d44c65f41259243370/bg2.jpg"><div class="t m0 x2 h5 y4 ff3 fs2 fc0 sc0 ls3 ws0">Zynq-700<span class="_ _2"></span>0 SoC T<span class="_ _0"></span>echnical Re<span class="_ _2"></span>fer<span class="_ _2"></span>ence Manual<span class="_ _3"> </span><span class="ff4 fc1 ls4">www<span class="_ _4"></span>.xilinx.com<span class="_ _5"> </span><span class="ff3 fc0 ls5">2</span></span></div><div class="t m0 x2 h6 y5 ff4 fs2 fc0 sc0 ls6 ws0">UG585 (v1.12.2) July 1, 2018</div><div class="t m0 x2 h7 y6 ff1 fs3 fc0 sc0 ls7 ws0">Notice of Disclaimer</div><div class="t m0 x2 h8 y7 ff5 fs3 fc0 sc0 ls8 ws0">The <span class="_ _4"></span>information <span class="_ _4"></span>disclosed to <span class="_ _4"></span>you <span class="_ _4"></span>hereunder <span class="_ _4"></span>(the <span class="_ _4"></span>“Materials”) is<span class="ls9"> pr<span class="_ _6"></span>o<span class="_ _6"></span>vi<span class="_ _6"></span>d<span class="_ _6"></span>ed<span class="_ _6"></span> s<span class="_ _6"></span>o<span class="_ _6"></span>le<span class="_ _6"></span>l<span class="_ _6"></span>y f<span class="_ _6"></span>o<span class="_ _6"></span>r<span class="_ _6"></span> th<span class="_ _6"></span>e<span class="_ _6"></span> se<span class="_ _6"></span>l<span class="_ _6"></span>e<span class="_ _6"></span>ct<span class="_ _6"></span>i<span class="_ _6"></span>on<span class="_ _6"></span> a<span class="_ _6"></span>n<span class="_ _6"></span>d u<span class="_ _6"></span>s<span class="_ _6"></span>e o<span class="_ _6"></span>f<span class="_ _6"></span> Xi<span class="_ _6"></span>l<span class="_ _6"></span>i<span class="_ _6"></span>nx<span class="_ _6"></span> p<span class="_ _6"></span>ro<span class="_ _6"></span>d<span class="_ _6"></span>u<span class="_ _6"></span>ct<span class="_ _6"></span>s<span class="_ _6"></span>. To t<span class="_ _6"></span>h<span class="_ _6"></span>e m<span class="_ _6"></span>a<span class="_ _6"></span>xi<span class="_ _6"></span>m<span class="_ _6"></span>u<span class="_ _6"></span>m </span></div><div class="t m0 x2 h8 y8 ff5 fs3 fc0 sc0 lsa ws0">extent permitted <span class="_ _4"></span>by applicable law: (1) <span class="_ _2"></span>Materials are mad<span class="_ _4"></span>e avai<span class="lsb">lable “AS IS” and <span class="_ _6"></span>with all fault<span class="lsc">s, Xilin<span class="_ _4"></span>x hereby DISCLAIMS ALL <span class="lsd">WAR<span class="_ _6"></span>R<span class="_ _6"></span>AN<span class="_ _6"></span>T<span class="_ _6"></span>IE<span class="_ _6"></span>S<span class="_ _6"></span> </span></span></span></div><div class="t m0 x2 h8 y9 ff5 fs3 fc0 sc0 lse ws0">AND C<span class="_ _4"></span>ONDITIONS, EXPRESS,<span class="_ _2"></span> IMPLIED, O<span class="_ _4"></span>R ST<span class="_ _4"></span>A<span class="_ _4"></span>TUT<span class="_ _4"></span>ORY, INCL<span class="_ _4"></span>UDING BUT N<span class="lsf">O<span class="_ _4"></span>T LIMITED T<span class="_ _4"></span>O W<span class="_ _4"></span>ARRANTIES OF MER<span class="_ _4"></span>CHANT<span class="_ _4"></span>ABILITY, </span></div><div class="t m0 x2 h8 ya ff5 fs3 fc0 sc0 ls10 ws0">NON-INFRINGEMENT<span class="_ _4"></span>, OR FITNESS FOR <span class="_ _4"></span>ANY P<span class="_ _4"></span>AR<span class="_ _4"></span>TICUL<span class="_ _6"></span>AR <span class="_ _4"></span>PURPOSE; and (2<span class="ls11">) Xilinx shall not be liable (whether in contract or tort, incl<span class="ls12">uding </span></span></div><div class="t m0 x2 h8 yb ff5 fs3 fc0 sc0 ls13 ws0">n<span class="_ _6"></span>e<span class="_ _6"></span>g<span class="_ _7"></span>l<span class="_ _6"></span>i<span class="_ _6"></span>g<span class="_ _7"></span>e<span class="_ _6"></span>n<span class="_ _7"></span>c<span class="_ _6"></span>e<span class="_ _6"></span>,<span class="_ _7"></span> o<span class="_ _6"></span>r<span class="_ _7"></span> u<span class="_ _6"></span>n<span class="_ _6"></span>d<span class="_ _7"></span>e<span class="_ _6"></span>r<span class="_ _7"></span> a<span class="_ _6"></span>n<span class="_ _6"></span>y<span class="_ _7"></span> o<span class="_ _6"></span>t<span class="_ _6"></span>h<span class="_ _7"></span>e<span class="_ _6"></span>r<span class="_ _7"></span> t<span class="_ _6"></span>h<span class="_ _6"></span>e<span class="_ _7"></span>o<span class="_ _6"></span>r<span class="_ _7"></span>y<span class="_ _6"></span> o<span class="_ _6"></span>f<span class="_ _7"></span> l<span class="_ _6"></span>i<span class="_ _7"></span>a<span class="_ _6"></span>b<span class="_ _6"></span>i<span class="_ _7"></span>l<span class="_ _6"></span>i<span class="_ _6"></span>t<span class="_ _7"></span>y<span class="_ _6"></span>)<span class="_ _7"></span> f<span class="_ _6"></span>o<span class="_ _6"></span>r<span class="_ _7"></span> a<span class="_ _6"></span>n<span class="_ _7"></span>y<span class="_ _6"></span> l<span class="_ _6"></span>o<span class="_ _7"></span>s<span class="_ _6"></span><span class="ls14">s<span class="_ _6"></span> o<span class="_ _6"></span>r<span class="_ _6"></span> d<span class="_ _6"></span>a<span class="_ _7"></span>m<span class="_ _6"></span>a<span class="_ _6"></span>g<span class="_ _6"></span>e<span class="_ _6"></span> o<span class="_ _6"></span>f<span class="_ _6"></span> a<span class="_ _7"></span>n<span class="_ _6"></span>y<span class="_ _6"></span> k<span class="_ _6"></span>i<span class="_ _6"></span>n<span class="_ _6"></span>d<span class="_ _6"></span> o<span class="_ _7"></span>r<span class="_ _6"></span> n<span class="_ _6"></span>a<span class="_ _6"></span>t<span class="_ _6"></span>u<span class="_ _6"></span>r<span class="_ _6"></span><span class="ls15">e <span class="_ _4"></span>related <span class="_ _0"></span>to, <span class="_ _4"></span>arising <span class="_ _0"></span>under, <span class="_ _4"></span>or<span class="ls16"> <span class="_ _4"></span>in <span class="_ _0"></span>connection <span class="_ _4"></span>with, </span></span></span></div><div class="t m0 x2 h8 yc ff5 fs3 fc0 sc0 ls12 ws0">the Material<span class="_ _6"></span>s (including your us<span class="_ _6"></span>e of the Materials), inc<span class="_ _6"></span>luding <span class="ls17">for any di<span class="_ _4"></span>rect, indirect, specia<span class="_ _4"></span><span class="ls18">l, incidental, o<span class="_ _2"></span>r consequ<span class="_ _2"></span>ential<span class="ls19"> loss or damage </span></span></span></div><div class="t m0 x2 h8 yd ff5 fs3 fc0 sc0 ls14 ws0">(<span class="_ _6"></span>i<span class="_ _6"></span>n<span class="_ _6"></span>c<span class="_ _6"></span>l<span class="_ _6"></span>u<span class="_ _7"></span>d<span class="_ _6"></span>i<span class="_ _6"></span>n<span class="_ _6"></span>g<span class="_ _6"></span> l<span class="_ _6"></span>o<span class="_ _6"></span>s<span class="_ _7"></span>s<span class="_ _6"></span> o<span class="_ _6"></span>f<span class="_ _6"></span> d<span class="_ _7"></span>a<span class="_ _6"></span>t<span class="_ _6"></span>a<span class="_ _6"></span>,<span class="_ _6"></span> p<span class="_ _7"></span>r<span class="_ _6"></span>o<span class="_ _6"></span>f<span class="_ _6"></span>i<span class="_ _6"></span>t<span class="_ _6"></span>s<span class="_ _7"></span><span class="ls7">, <span class="_ _4"></span>goodwill, <span class="_ _4"></span>or <span class="_ _4"></span>any <span class="_ _4"></span>type <span class="_ _4"></span>of <span class="_ _4"></span>loss<span class="ls14"> o<span class="_ _6"></span>r<span class="_ _6"></span> <span class="_ _6"></span>d<span class="_ _6"></span>a<span class="_ _6"></span>m<span class="_ _6"></span>a<span class="_ _6"></span>g<span class="_ _6"></span>e<span class="_ _6"></span> s<span class="_ _6"></span>u<span class="_ _6"></span>f<span class="_ _7"></span>f<span class="_ _6"></span>e<span class="_ _6"></span>r<span class="_ _6"></span>e<span class="_ _6"></span>d<span class="_ _6"></span> a<span class="_ _7"></span>s<span class="_ _6"></span> a<span class="_ _6"></span> r<span class="_ _6"></span>e<span class="_ _7"></span>s<span class="_ _6"></span>u<span class="_ _6"></span>l<span class="_ _6"></span>t<span class="_ _6"></span> o<span class="_ _6"></span>f<span class="_ _6"></span> <span class="_ _6"></span>a<span class="_ _6"></span>n<span class="_ _6"></span>y<span class="_ _6"></span> a<span class="_ _6"></span>c<span class="_ _6"></span>t<span class="_ _6"></span>i<span class="_ _6"></span>o<span class="_ _6"></span>n<span class="_ _7"></span> b<span class="_ _6"></span>r<span class="_ _6"></span>o<span class="_ _6"></span>u<span class="_ _6"></span>g<span class="_ _7"></span>h<span class="_ _6"></span>t<span class="_ _6"></span> b<span class="_ _6"></span>y<span class="_ _6"></span> a<span class="_ _7"></span> t<span class="_ _6"></span>h<span class="_ _6"></span>i<span class="_ _6"></span>r<span class="_ _6"></span><span class="ls1a">d<span class="_ _6"></span> p<span class="_ _6"></span>a<span class="_ _6"></span>r<span class="_ _6"></span>t<span class="_ _6"></span>y<span class="_ _6"></span>)<span class="_ _6"></span> e<span class="_ _6"></span>v<span class="_ _6"></span>e<span class="_ _6"></span>n<span class="_ _6"></span> i<span class="_ _6"></span>f<span class="_ _6"></span> s<span class="_ _6"></span>u<span class="_ _6"></span>c<span class="_ _6"></span>h<span class="_ _6"></span> </span></span></span></div><div class="t m0 x2 h8 ye ff5 fs3 fc0 sc0 ls1b ws0">damage <span class="_ _4"></span>or <span class="_ _2"></span>loss <span class="_ _4"></span>was reas<span class="_ _2"></span>onably <span class="_ _4"></span>foreseeable <span class="_ _4"></span>or X<span class="_ _2"></span>ilinx <span class="_ _4"></span>had been <span class="_ _4"></span>ad<span class="ls1c">vi<span class="_ _6"></span>se<span class="_ _6"></span>d<span class="_ _6"></span> of<span class="_ _6"></span> th<span class="_ _6"></span>e p<span class="_ _6"></span>os<span class="_ _6"></span>s<span class="_ _6"></span>ib<span class="_ _6"></span>il<span class="_ _6"></span>i<span class="_ _6"></span>ty<span class="_ _6"></span> of<span class="_ _6"></span> th<span class="_ _6"></span>e s<span class="_ _6"></span>a<span class="_ _6"></span>me<span class="_ _6"></span>. X<span class="_ _6"></span>il<span class="_ _6"></span>i<span class="_ _6"></span>nx<span class="_ _6"></span> as<span class="_ _6"></span>su<span class="_ _6"></span>m<span class="_ _6"></span>es<span class="_ _6"></span> no<span class="_ _6"></span> ob<span class="_ _6"></span>li<span class="_ _6"></span>g<span class="_ _6"></span>at<span class="_ _6"></span><span class="ls1d">ion <span class="_ _4"></span>to <span class="_ _4"></span>correct </span></span></div><div class="t m0 x2 h8 yf ff5 fs3 fc0 sc0 ls1e ws0">any errors contained in<span class="_ _4"></span><span class="ls1f"> the Materials or to notify you of u<span class="_ _4"></span>pdat<span class="ls20">es to the Materials or<span class="ls21"> to product specificati<span class="_ _6"></span>ons. Y<span class="_ _0"></span>ou may not <span class="_ _6"></span>r<span class="ls22">eproduc<span class="_ _2"></span>e, </span></span></span></span></div><div class="t m0 x2 h8 y10 ff5 fs3 fc0 sc0 ls23 ws0">modify, dis<span class="_ _6"></span>tribute, or publicly <span class="ls24">display th<span class="_ _6"></span>e Materials without p<span class="ls25">rior written consent. Cer<span class="_ _6"></span>tain products are subje<span class="_ _6"></span>ct to the terms and conditions </span></span></div><div class="t m0 x2 h8 y11 ff5 fs3 fc0 sc0 ls26 ws0">of <span class="_ _4"></span>Xilinx’s <span class="_ _4"></span>limited <span class="_ _4"></span>warran<span class="_ _6"></span>ty, <span class="_ _0"></span>pl<span class="_ _6"></span>ease <span class="_ _0"></span>refer<span class="_ _6"></span> <span class="_ _0"></span>to <span class="_ _4"></span>Xil<span class="_ _6"></span>inx’s <span class="_ _4"></span>T<span class="_ _0"></span>erms <span class="_ _4"></span>of<span class="lsc"> <span class="_ _4"></span>Sale <span class="_ _4"></span>which <span class="_ _0"></span>can <span class="_ _4"></span>be <span class="_ _4"></span>viewe<span class="_ _4"></span>d <span class="_ _4"></span>at <span class="_ _4"></span><span class="fc1 ls27">http://www.xilinx.com/legal.htm#tos</span></span></div><div class="t m0 x3 h8 y12 ff5 fs3 fc0 sc0 ls14 ws0">;<span class="_ _6"></span> I<span class="_ _6"></span>P<span class="_ _6"></span> c<span class="_ _6"></span>o<span class="_ _6"></span>r<span class="_ _7"></span>e<span class="_ _6"></span>s<span class="_ _6"></span> m<span class="_ _6"></span>a<span class="_ _6"></span>y<span class="_ _6"></span> b<span class="_ _6"></span>e<span class="_ _6"></span> </div><div class="t m0 x2 h8 y13 ff5 fs3 fc0 sc0 ls28 ws0">subject to wa<span class="_ _6"></span>rranty and support <span class="_ _6"></span>terms contained in a <span class="_ _6"></span>license is<span class="ls11">sued to you by <span class="_ _6"></span>Xilinx. Xilinx products are n<span class="_ _6"></span>ot designed or inte<span class="ls29">nded to b<span class="_ _6"></span>e </span></span></div><div class="t m0 x2 h8 y14 ff5 fs3 fc0 sc0 ls2a ws0">fail-safe or<span class="_ _6"></span> for use in any <span class="_ _6"></span>appl<span class="ls2b">icat<span class="_ _2"></span>ion requir<span class="_ _4"></span>ing fail-safe per<span class="ls2c">formance; you assume sole risk and liability for use of Xilinx<span class="_ _6"></span> <span class="ls23">products in such </span></span></span></div><div class="t m0 x2 h8 y15 ff5 fs3 fc0 sc0 ls2d ws0">critical applicatio<span class="_ _6"></span>ns, please re<span class="ls2e">fer to Xilinx’s T<span class="_ _4"></span>erms of Sale w<span class="ls2f">hich can be<span class="_ _4"></span> viewed at <span class="fc1 ls27">http://www.xilinx.com/legal.htm#tos</span></span></span></div><div class="t m0 x4 h8 y16 ff5 fs3 fc0 sc0 ls5 ws0">.</div><div class="t m0 x2 h7 y17 ff1 fs3 fc0 sc0 ls22 ws0">Automotive Appli<span class="_ _2"></span>cations Disclaimer</div><div class="t m0 x2 h8 y18 ff5 fs3 fc0 sc0 ls30 ws0">AUT<span class="_ _4"></span>OMO<span class="_ _4"></span>TIVE PRODU<span class="_ _4"></span>CTS (IDENTIFIED AS<span class="_ _4"></span> "XA" IN THE P<span class="_ _4"></span>AR<span class="_ _4"></span>T NUMBER) ARE<span class="ls10"> NO<span class="_ _4"></span>T W<span class="_ _4"></span>ARRANTED FOR USE I<span class="_ _2"></span>N THE DEPL<span class="_ _4"></span>OYMENT OF AI<span class="_ _4"></span>RBAGS </span></div><div class="t m0 x2 h8 y19 ff5 fs3 fc0 sc0 ls25 ws0">OR FOR USE I<span class="_ _6"></span>N APPLICA<span class="_ _4"></span>TIONS THA<span class="_ _4"></span>T AFFECT <span class="_ _6"></span>C<span class="_ _4"></span>ONTROL <span class="_ _6"></span>OF A VEHICLE ("S<span class="ls2d">AFET<span class="_ _6"></span>Y APPLICA<span class="_ _4"></span>TION") UNLESS TH<span class="_ _6"></span>ERE IS A SAFETY CONCEPT OR </span></div><div class="t m0 x2 h8 y1a ff5 fs3 fc0 sc0 ls1b ws0">REDUNDAN<span class="_ _4"></span>CY FEA<span class="_ _4"></span>TURE CONSISTENT <span class="_ _4"></span>WITH THE ISO 26262 AUT<span class="_ _4"></span>OMO<span class="_ _4"></span>TIVE SAF<span class="ls22">ETY ST<span class="_ _4"></span>ANDARD ("SAFETY DESI<span class="ls31">GN"). CUS<span class="_ _4"></span>TOMER SHALL, </span></span></div><div class="t m0 x2 h8 y1b ff5 fs3 fc0 sc0 ls32 ws0">PRIOR TO USING OR DI<span class="_ _6"></span>STRIBUTING ANY<span class="_ _6"></span> SYSTEMS THA<span class="_ _4"></span>T <span class="_ _6"></span>INC<span class="_ _4"></span>OR<span class="_ _6"></span>PORA<span class="_ _0"></span>T<span class="_ _6"></span>E PRO<span class="ls17">DUCT<span class="_ _4"></span>S, THOROUGHL<span class="_ _4"></span>Y TEST S<span class="ls33">U<span class="_ _4"></span>CH SYSTEMS FOR SAFETY </span></span></div><div class="t m0 x2 h8 y1c ff5 fs3 fc0 sc0 ls14 ws0">P<span class="_ _6"></span>U<span class="_ _6"></span>R<span class="_ _6"></span>P<span class="_ _6"></span>O<span class="_ _6"></span>S<span class="_ _7"></span>E<span class="_ _6"></span>S<span class="_ _6"></span>.<span class="_ _6"></span> U<span class="_ _6"></span>S<span class="_ _7"></span>E<span class="_ _6"></span> O<span class="_ _6"></span>F<span class="_ _6"></span> P<span class="_ _6"></span>R<span class="_ _6"></span>O<span class="_ _6"></span>D<span class="_ _7"></span>U<span class="_ _6"></span>C<span class="_ _6"></span>T<span class="_ _6"></span>S<span class="_ _6"></span> I<span class="_ _6"></span>N<span class="_ _6"></span> A<span class="_ _6"></span> S<span class="_ _7"></span>A<span class="_ _6"></span>F<span class="_ _6"></span>E<span class="_ _6"></span>T<span class="_ _7"></span>Y<span class="_ _6"></span> A<span class="_ _6"></span>P<span class="_ _6"></span>P<span class="_ _6"></span>L<span class="_ _7"></span>I<span class="_ _6"></span>C<span class="_ _6"></span>AT<span class="_ _6"></span>I<span class="_ _6"></span>O<span class="_ _6"></span>N<span class="_ _6"></span> W<span class="_ _7"></span>I<span class="_ _6"></span>T<span class="_ _6"></span>H<span class="_ _6"></span>O<span class="_ _6"></span>U<span class="_ _6"></span>T<span class="_ _7"></span> A<span class="_ _6"></span> S<span class="_ _6"></span>A<span class="_ _6"></span>F<span class="_ _6"></span>E<span class="_ _7"></span>T<span class="_ _6"></span>Y<span class="_ _7"></span> D<span class="_ _6"></span>E<span class="_ _6"></span>S<span class="_ _6"></span>I<span class="_ _6"></span>G<span class="_ _6"></span>N<span class="_ _7"></span> I<span class="_ _6"></span>S<span class="_ _6"></span> F<span class="_ _6"></span>U<span class="_ _6"></span>L<span class="_ _7"></span>LY<span class="_ _6"></span> AT<span class="_ _6"></span> T<span class="_ _6"></span>H<span class="_ _6"></span>E<span class="_ _6"></span> R<span class="_ _7"></span>I<span class="_ _6"></span>S<span class="_ _6"></span>K<span class="_ _6"></span> O<span class="_ _6"></span>F<span class="_ _6"></span> <span class="_ _6"></span>C<span class="_ _6"></span>U<span class="_ _6"></span>S<span class="_ _6"></span>TO<span class="_ _6"></span>M<span class="_ _6"></span>E<span class="_ _7"></span>R<span class="_ _6"></span>,<span class="_ _6"></span> S<span class="_ _6"></span>U<span class="_ _6"></span>B<span class="_ _6"></span>J<span class="_ _7"></span>E<span class="_ _6"></span>C<span class="_ _6"></span>T<span class="_ _6"></span> O<span class="_ _6"></span>N<span class="_ _6"></span>L<span class="_ _6"></span>Y<span class="_ _6"></span> </div><div class="t m0 x2 h8 y1d ff5 fs3 fc0 sc0 ls23 ws0">T<span class="_ _4"></span>O APP<span class="_ _6"></span>LICABLE L<span class="_ _6"></span>A<span class="_ _0"></span>WS <span class="_ _6"></span>AND REGULA<span class="_ _4"></span>TI<span class="_ _6"></span>ONS GOVERNING LIMIT<span class="_ _4"></span>A<span class="_ _4"></span>TIONS ON<span class="_ _6"></span> PRODUCT LIABILIT<span class="_ _6"></span>Y.</div><div class="t m0 x2 h8 y1e ff5 fs3 fc0 sc0 ls34 ws0">© Copyright 2012-2017 X<span class="ls35">ilinx, Inc. Xilinx, the Xilinx logo, Ar<span class="_ _6"></span>tix, ISE, Kintex, Spartan, Virtex<span class="ls36">, Vivado, Zynq, <span class="ls21">and other designated bran<span class="_ _6"></span>ds </span></span></span></div><div class="t m0 x2 h8 y1f ff5 fs3 fc0 sc0 ls37 ws0">included h<span class="_ _4"></span>erein are trademarks o<span class="ls38">f Xilinx in the <span class="ls11">U<span class="_ _6"></span>nited S<span class="_ _4"></span>tates a<span class="_ _6"></span><span class="ls39">nd other countries. All ot<span class="_ _6"></span>her tr<span class="ls31">ademarks <span class="_ _2"></span>are the property of <span class="_ _4"></span>th<span class="ls3a">eir respective </span></span></span></span></span></div><div class="t m0 x2 h8 y20 ff5 fs3 fc0 sc0 ls27 ws0">owners.</div><div class="t m0 x2 h9 y21 ff5 fs2 fc0 sc0 ls3b ws0">The following table shows the re<span class="_ _6"></span><span class="ls3c">visi<span class="_ _4"></span>on history for this documen<span class="ls3d">t. Change bars indicate <span class="ls3e">the latest revisions.</span></span></span></div><div class="t m0 x2 ha y22 ff4 fs4 fc0 sc0 ls5 ws0"> </div><div class="t m0 x5 h5 y23 ff3 fs2 fc0 sc0 ls3f ws0">Date<span class="_ _8"> </span>V<span class="_ _4"></span>ersion<span class="_ _9"> </span>Revision</div><div class="t m0 x6 hb y24 ff5 fs5 fc0 sc0 ls40 ws0">04/08/2012<span class="_ _a"> </span>1.0<span class="_ _b"> </span>Xilinx initial release.</div><div class="t m0 x6 hb y25 ff5 fs5 fc0 sc0 ls41 ws0">06/25/2012<span class="_ _a"> </span>1.1<span class="_ _b"> </span>Removed <span class="_ _0"></span>Chapter <span class="_ _4"></span>30, <span class="_ _4"></span>B<span class="ls42">oard <span class="_ _4"></span>Design <span class="_ _4"></span>(now <span class="_ _0"></span>part <span class="_ _4"></span>of <span class="_ _4"></span>UG93<span class="ls40">3, <span class="_ _4"></span><span class="ff6 ls43 ws2">Zynq-7000 SoC PCB Design <span class="_ _6"></span>and </span></span></span></div><div class="t m0 x7 hc y26 ff6 fs5 fc0 sc0 ls44 ws3">Pin Planning Guide).</div><div class="t m0 x6 hb y27 ff5 fs5 fc0 sc0 ls42 ws0">08/08/2012<span class="_ _a"> </span>1.2<span class="_ _b"> </span>Added information about the </div><div class="t m0 x8 h9 y28 ff5 fs2 fc0 sc0 ls45 ws0">7z010 CL<span class="_ _4"></span>G225 device and references to section </div><div class="t m0 x7 h9 y29 ff5 fs2 fc1 sc0 ls46 ws0">2.5.4<span class="_ _c"> </span>MIO-at-a-Glance T<span class="_ _d"></span>able<span class="fc0 ls47"> throughout document. <span class="fs5 ls48">Added section headings </span></span></div><div class="t m0 x7 hb y2a ff5 fs5 fc1 sc0 ls48 ws0">1.1.1<span class="_ _e"> </span>Block <span class="_ _0"></span>Diagram<span class="fc0 ls49"> a<span class="_ _7"></span>n<span class="_ _6"></span>d<span class="_ _7"></span> </span><span class="ls4a">1.1.2<span class="_ _e"> </span>Documenta<span class="ls41">tion <span class="_ _4"></span>Resources<span class="fc0 ls4b">, <span class="_ _0"></span>added <span class="_ _4"></span>sections <span class="_ _0"></span><span class="fc1 ls4c">1.1.3<span class="_ _e"> </span>Notices<span class="fc0 ls5"> </span></span></span></span></span></div><div class="t m0 x7 hb y2b ff5 fs5 fc0 sc0 ls4d ws0">and <span class="fc1 ls4e">T<span class="_ _0"></span>rustZone Capabilities<span class="fc0">, and clarified </span><span class="ls4f">PS MIO I/Os <span class="_ _6"></span><span class="fc0 ls50">in </span><span class="ls4a">Chapter<span class="_"> </span>1<span class="fc0 ls4d">. Updated </span><span class="ls51">Ta<span class="_ _7"></span>b<span class="_ _1"></span>l<span class="_ _7"></span>e<span class="_ _f"> </span>2<span class="_ _7"></span>-<span class="_ _1"> </span>1<span class="_ _1"></span><span class="fc0 ls52">. </span></span></span></span></span></div><div class="t m0 x7 hb y2c ff5 fs5 fc0 sc0 ls53 ws0">Changed <span class="ff6 ls4f ws4">2.4.2 MIO-EMIO Connecti<span class="_ _6"></span>ons</span><span class="ls52"> heading to <span class="_ _2"></span><span class="fc1 ls54">2.5.2<span class="_ _e"> </span>IOP Interface <span class="_ _6"></span>Connections<span class="fc0 ls55"> and </span></span></span></div><div class="t m0 x7 hb y2d ff5 fs5 fc0 sc0 ls56 ws0">clarified <span class="_ _4"></span>first <span class="_ _4"></span>paragraph. <span class="_ _4"></span>Updated <span class="_ _4"></span><span class="fc1 ls57">Ta<span class="_ _1"></span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>2<span class="_ _1"></span>-<span class="_ _1"></span>4<span class="_ _1"></span><span class="fc0 ls58">. <span class="_ _4"></span>Added <span class="_ _2"></span>section <span class="_ _4"></span><span class="fc1 ls59">2.7.1<span class="_ _e"> </span>Clocks <span class="_ _4"></span>an<span class="_ _6"></span>d <span class="_ _4"></span>R<span class="_ _4"></span>e<span class="_ _6"></span>sets<span class="fc0 ls5a"> a<span class="_ _6"></span>nd<span class="_ _6"></span> </span></span></span></span></div><div class="t m0 x7 hb y2e ff5 fs5 fc1 sc0 ls57 ws0">Ta<span class="_ _1"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>2<span class="_ _7"></span>-<span class="_ _1"> </span>7<span class="_ _1"> </span><span class="fc0 ls4b">, and upd<span class="_ _2"></span>ated <span class="fc1 ls57">Ta<span class="_ _7"></span>b<span class="_ _1"></span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>2<span class="_ _7"></span>-<span class="_ _10"> </span>1<span class="_ _7"></span>3<span class="_ _1"> </span></span><span class="ls5"> <span class="_ _6"></span><span class="fc1 ls5b">PS<span class="_ _6"></span> MIO<span class="_ _6"></span> I/<span class="_ _6"></span>Os<span class="_ _6"></span> </span><span class="ls5c">in<span class="_ _6"></span> <span class="_ _4"></span><span class="fc1 ls4c">Chapter<span class="_"> </span>2<span class="fc0 ls53">. Added <span class="_ _4"></span>not<span class="_ _6"></span>e <span class="_ _4"></span>under <span class="fc1 ls42">Branch </span></span></span></span></span></span></div><div class="t m0 x7 hb y2f ff5 fs5 fc1 sc0 ls42 ws0">Prediction<span class="fc0 ls4f"> and </span><span class="ls51">Ta<span class="_ _1"></span>b<span class="_ _1"></span>l<span class="_ _7"></span>e<span class="_ _f"> </span>3<span class="_ _7"></span>-<span class="_ _1"> </span>8<span class="_ _1"> </span><span class="fc0 ls55"> in </span><span class="ls41">Chapter<span class="_"> </span>3<span class="fc0 ls5d">. Updat<span class="_ _4"></span>ed <span class="fc1 ls57">Ta<span class="_ _7"></span>b<span class="_ _1"> </span>l<span class="_ _10"> </span>e<span class="_ _f"> </span>4<span class="_ _7"></span>-<span class="_ _1"> </span>1<span class="_ _1"> </span></span><span class="ls5e"> in <span class="fc1 ls4a">Chapter<span class="_"> </span>4</span><span class="ls4c">. Added section </span></span></span></span></span></div><div class="t m0 x7 hb y30 ff5 fs5 fc1 sc0 ls53 ws0">5.1.7<span class="_ _e"> </span>R<span class="_ _2"></span>ead/Write R<span class="_ _4"></span>equest Capability<span class="fc0 ls55"> in </span><span class="ls5f">Chapter<span class="_ _11"> </span>5<span class="fc0 ls60">. Updated </span></span></div><div class="t m0 x9 h9 y31 ff5 fs2 fc1 sc0 ls61 ws0">NAND Boot<span class="_ _2"></span><span class="fc0 ls47"> MIO pin </span></div><div class="t m0 x7 h9 y32 ff5 fs2 fc0 sc0 ls45 ws0">assignments and </div><div class="t m0 xa hb y33 ff5 fs5 fc1 sc0 ls57 ws0">Ta<span class="_ _1"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>6<span class="_ _7"></span>-<span class="_ _1"> </span>6<span class="_ _1"> </span><span class="fc0 ls62"> in <span class="_ _6"></span></span><span class="ls4c">Chapter<span class="_"> </span>6<span class="fc0 ls58">. Upd<span class="_ _4"></span>a<span class="_ _6"></span>ted se<span class="_ _4"></span>ction <span class="fc1 ls63">7.1.5<span class="_ _e"> </span>CPU Interrupt Signa<span class="_ _4"></span>l </span></span></span></div><div class="t m0 x7 hb y34 ff5 fs5 fc1 sc0 ls64 ws0">P<span class="_ _4"></span>ass-t<span class="_ _6"></span>hrough<span class="fc0 ls55"> i<span class="_ _4"></span>n <span class="fc1 ls5f">Chapter<span class="_"> </span>7</span><span class="ls48">. Added section heading <span class="fc1 ls59">10.1.1<span class="_ _e"> </span>Features</span><span class="ls44"> and ad<span class="_ _2"></span>ded section </span></span></span></div><div class="t m0 x7 hb y35 ff5 fs5 fc1 sc0 ls50 ws0">10.1.3<span class="_ _e"> </span>Notices<span class="fc0 ls62"> in </span><span class="ls4c">Chapter<span class="_"> </span>10<span class="fc0 ls65">. Updated </span><span class="ls66">P<span class="_ _4"></span>arallel (SRAM/NOR) Interface<span class="fc0 ls43"> features list an<span class="_ _6"></span>d </span></span></span></div><div class="t m0 x7 hb y36 ff5 fs5 fc0 sc0 ls67 ws0">added section <span class="fc1 ls50">11.1.3<span class="_ _e"> </span>Notices</span><span class="ls62"> in <span class="fc1 ls4c">Chapter<span class="_"> </span>11</span><span class="ls58">. Reorg<span class="_ _2"></span>anized, clarified, and expanded </span></span></div><div class="t m0 x7 hb y37 ff5 fs5 fc1 sc0 ls4c ws0">Chapter<span class="_"> </span>12<span class="fc0 ls68"> to include <span class="_ _4"></span>programming <span class="ls56">models (adde<span class="_ _2"></span>d sections <span class="fc1 ls48">12.1.4<span class="_ _e"> </span>Notices<span class="fc0">, </span></span></span></span></div><div class="t m0 x7 hb y38 ff5 fs5 fc1 sc0 ls48 ws0">12.3<span class="_ _e"> </span>Programming Guide<span class="fc0 ls67">, and <span class="fc1">12.5.2<span class="_ _e"> </span>MIO Programming</span><span class="ls48">). Added last note in section </span></span></div><div class="t m0 x7 hb y39 ff5 fs5 fc1 sc0 ls42 ws0">13.3.4<span class="_ _e"> </span>Using ADMA<span class="_ _6"></span><span class="fc0 ls5e"> in </span><span class="ls69">Ch<span class="_ _2"></span>apter<span class="_"> </span>13<span class="_ _4"></span><span class="fc0 ls58">. Added <span class="fc1 ls6a">Re<span class="_ _6"></span>st<span class="_ _6"></span>ri<span class="_ _6"></span>ct<span class="_ _6"></span>io<span class="_ _6"></span>n<span class="_ _6"></span>s</span><span class="ls62"> in <span class="fc1 ls4c">Chapter<span class="_"> </span>14</span><span class="ls6b">. Clarified first </span></span></span></span></div><div class="t m0 x7 hb y3a ff5 fs5 fc0 sc0 ls62 ws0">paragraph, added section<span class="_ _6"></span> <span class="fc1 ls4d">15.1.3<span class="_ _e"> </span>Notices<span class="_ _4"></span><span class="fc0 ls5c">,<span class="_ _6"></span> and clar<span class="_ _6"></span>ified <span class="fc1 ls4b">Figure<span class="_"> </span>15-7</span><span class="ls6c"> through </span></span></span></div><div class="t m0 x7 hb y3b ff5 fs5 fc1 sc0 ls6d ws0">Figure<span class="_"> </span>15-17<span class="fc0 ls62"> in </span><span class="ls4c">Chapter<span class="_"> </span>15<span class="fc0 ls4d">. Added section </span><span class="ls48">16.1.4<span class="_ _e"> </span>Notices<span class="fc0 ls6e"> in </span></span>Chapter<span class="_"> </span>16<span class="fc0 ls60">. Clarified </span></span></div><div class="t m0 x7 hb y3c ff5 fs5 fc0 sc0 ls62 ws0">sections <span class="fc1">17.2.5<span class="_ _e"> </span>SPI FIFOs<span class="_ _6"></span></span><span class="ls52">, <span class="fc1 ls41">17.2.6<span class="_ _e"> </span>SPI Clocks</span><span class="ls67">, and <span class="fc1 ls42">17.2.7<span class="_ _e"> </span>SPI EMIO Considerations</span></span></span> in </div><div class="t m0 x7 hb y3d ff5 fs5 fc1 sc0 ls4c ws0">Chapter<span class="_"> </span>17<span class="fc0 ls53">. Reorg<span class="_ _4"></span>a<span class="_ _6"></span>nized, clarified, and e<span class="_ _4"></span>x<span class="_ _6"></span>panded <span class="_ _4"></span><span class="fc1 ls41">Ch<span class="_ _6"></span>apter<span class="_"> </span>18<span class="fc0 ls6c"> to include programming </span></span></span></div><div class="t m0 x7 hb y3e ff5 fs5 fc0 sc0 ls56 ws0">models (added se<span class="_ _2"></span>ctions <span class="fc1 ls48">18.1.4<span class="_ _e"> </span>Notices</span><span class="ls55"> and<span class="_ _2"></span> <span class="fc1 ls66">18.5.1<span class="_ _e"> </span>MIO Programming</span><span class="ls63">).</span></span></div><div class="c xb y3f w2 hd"><div class="t m1 xc he y40 ff7 fs6 fc2 sc0 ls5 ws0"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 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<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626601d44c65f41259243370/bg3.jpg"><div class="t m0 x2 h5 y4 ff3 fs2 fc0 sc0 ls3 ws0">Zynq-700<span class="_ _2"></span>0 SoC T<span class="_ _0"></span>echnical Re<span class="_ _2"></span>fer<span class="_ _4"></span>ence Manual<span class="_ _12"> </span><span class="ff4 fc1 ls4">www<span class="_ _4"></span>.xilinx.com<span class="_ _5"> </span><span class="ff3 fc0 ls5">3</span></span></div><div class="t m0 x2 h6 y5 ff4 fs2 fc0 sc0 ls6 ws0">UG585 (v1.12.2) July 1, 2018</div><div class="t m0 x6 hb y41 ff5 fs5 fc0 sc0 ls6f ws0">08/08/2012<span class="_ _a"> </span>1.2</div><div class="t m0 xd hb y42 ff5 fs5 fc0 sc0 ls5 ws0">(<span class="_ _6"></span><span class="ff6 ls64">Cont’d)</span></div><div class="t m0 x7 hb y41 ff5 fs5 fc0 sc0 ls48 ws0">R<span class="_ _2"></span>eorganized, clarified, and expanded <span class="fc1 ls4c">Chapter<span class="_"> </span>19</span><span class="ls70"> to include p<span class="_ _6"></span>rogramming mo<span class="_ _6"></span>dels </span></div><div class="t m0 x7 hb y42 ff5 fs5 fc0 sc0 ls52 ws0">(added sections <span class="fc1 ls62">19.1.3<span class="_ _e"> </span>Notices</span>, <span class="fc1 ls71">19.3<span class="_ _e"> </span>Progr<span class="_ _6"></span>amming Guide</span><span class="ls67">, and <span class="fc1 ls59">19.5.1<span class="_ _e"> </span>MIO<span class="_ _6"></span> </span></span></div><div class="t m0 x7 hb y43 ff5 fs5 fc1 sc0 ls6f ws0">Programming<span class="fc0 ls6d">). Updated </span><span class="ls4a">T<span class="_ _d"></span>able<span class="_ _13"> </span>22-2<span class="fc0 ls55"> and </span><span class="ls4f">T<span class="_ _d"></span>able<span class="_"> </span>22-3<span class="_ _6"></span><span class="fc0 ls6e"> in </span><span class="ls4c">Chapter<span class="_"> </span>22<span class="fc0 ls4d">. Added sec<span class="_ _4"></span>t<span class="_ _6"></span>ion <span class="fc1 ls72">CP<span class="_ _4"></span>U </span></span></span></span></span></div><div class="t m0 x7 hb y44 ff5 fs5 fc1 sc0 ls73 ws0">Clock Divisor Restriction<span class="fc0 ls62"> in </span><span class="ls4c">Chapter<span class="_"> </span>25<span class="fc0 ls65">. Updated<span class="_ _4"></span> <span class="fc1 ls4f">T<span class="_ _0"></span>able<span class="_"> </span>26-4<span class="_ _6"></span><span class="fc0 ls62"> in </span><span class="ls4c">Chapter<span class="_"> </span>26<span class="fc0 ls60">. Clarified </span></span></span></span></span></div><div class="t m0 x7 hb y45 ff5 fs5 fc0 sc0 ls74 ws0">section <span class="fc1 ls75">27.3<span class="_ _e"> </span>I/O Signals<span class="_ _6"></span></span><span class="ls62"> in <span class="fc1 ls4c">Chapter<span class="_"> </span>27</span><span class="ls76">. Added <span class="_ _6"></span>section <span class="fc1 ls40">28.1.2<span class="_ _e"> </span>Notices</span><span class="ls5e"> in <span class="fc1 ls69">Chapter<span class="_ _11"> </span>28</span><span class="ls52">. </span></span></span></span></div><div class="t m0 x7 hb y46 ff5 fs5 fc0 sc0 ls6d ws0">Clarified <span class="fc1">Mapping Summary</span><span class="ls77"> a<span class="_ _4"></span>nd updated <span class="fc1 ls57">Ta<span class="_ _7"></span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>2<span class="_ _1"></span>9<span class="_ _1"></span>-<span class="_ _1"></span>1<span class="_ _1"> </span></span><span class="ls52">, <span class="fc1 ls4a">T<span class="_ _0"></span>able<span class="_"> </span>29-3<span class="fc0 ls5c">, <span class="_ _6"></span>and </span><span class="ls57">Ta<span class="_ _7"></span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>2<span class="_ _1"> </span>9<span class="_ _1"> </span>-<span class="_ _1"></span>5<span class="_ _1"> </span><span class="fc0 ls6e"> in </span></span></span></span></span></div><div class="t m0 x7 hb y47 ff5 fs5 fc1 sc0 ls4c ws0">Chapter<span class="_"> </span>29<span class="fc0">. <span class="_ _4"></span>Added <span class="_ _0"></span>section <span class="_ _4"></span><span class="fc1 ls78">30.1.3<span class="_ _e"> </span>Notices<span class="fc0 ls49"> i<span class="_ _6"></span>n<span class="_ _6"></span> </span><span class="ls41">Ch<span class="_ _6"></span>apter<span class="_"> </span>30<span class="fc0 ls67">. <span class="_ _0"></span>Updated <span class="_ _4"></span>data <span class="_ _4"></span>sheet <span class="_ _0"></span>references </span></span></span></span></div><div class="t m0 x7 hb y48 ff5 fs5 fc0 sc0 ls4e ws0">in section <span class="fc1 ls42">A.3.1<span class="_ _e"> </span>Z<span class="_ _4"></span>ynq-<span class="_ _6"></span>7000 SoC Documents<span class="fc0 ls79"> of </span><span class="ls7a">Appendix<span class="_"> </span>A<span class="fc0 ls60">. Updated register database </span></span></span></div><div class="t m0 x7 hb y49 ff5 fs5 fc0 sc0 ls52 ws0">in sections <span class="fc1 ls7b">B.3<span class="_ _e"> </span>Modul<span class="_ _4"></span>e Summary<span class="fc0 ls7c"> through<span class="_ _6"></span> </span><span class="ls7d">B.34<span class="_ _14"> </span>USB Control<span class="_ _2"></span>ler (usb)<span class="fc0 ls62"> in </span><span class="ls4b">Appendix<span class="_"> </span>B<span class="fc0 ls5">.</span></span></span></span></div><div class="t m0 x6 hb y4a ff5 fs5 fc0 sc0 ls66 ws0">10/30/2012<span class="_ _a"> </span>1.3<span class="_ _b"> </span>Changed product name <span class="ls43">from Extensible Processing Pl<span class="ls7e">atform (EPP) to SoC (AP<span class="_"> </span>SoC) </span></span></div><div class="t m0 x7 hb y4b ff5 fs5 fc0 sc0 ls41 ws0">throughout document. Added <span class="_ _4"></span><span class="fc1 ls57">Ta<span class="_ _1"> </span>b<span class="_ _10"> </span>l<span class="_ _1"></span>e<span class="_ _f"> </span>1<span class="_ _7"></span>-<span class="_ _1"> </span>1<span class="_ _1"> </span><span class="fc0 ls4e">. Added </span><span class="ls62">2.1.1<span class="_ _14"> </span>Notices<span class="fc0 ls52">, </span><span class="ls7f">2.<span class="_ _6"></span>4<span class="_ _e"> </span>PS<span class="_ _6"></span>–PL<span class="_ _6"></span> V<span class="_ _4"></span>olt<span class="_ _6"></span>age<span class="_ _6"></span> Lev<span class="_ _6"></span>el </span></span></span></div><div class="t m0 x7 hb y4c ff5 fs5 fc1 sc0 ls58 ws0">Shifter <span class="_ _2"></span>Enables<span class="fc0 ls52">, <span class="_ _4"></span><span class="fc1 ls5b">A<span class="_ _6"></span> su<span class="_ _6"></span>mm<span class="_ _6"></span>ar<span class="_ _6"></span>y o<span class="_ _6"></span>f th<span class="_ _6"></span>e d<span class="_ _6"></span>ed<span class="_ _6"></span>ic<span class="_ _6"></span>at<span class="_ _6"></span>ed P<span class="_ _6"></span>S s<span class="_ _6"></span>ig<span class="_ _6"></span>na<span class="_ _6"></span>l p<span class="_ _6"></span>ins<span class="_ _6"></span> is<span class="_ _6"></span> sh<span class="_ _6"></span>ow<span class="_ _6"></span>n i<span class="_ _6"></span>n T<span class="_ _0"></span>a<span class="_ _6"></span>bl<span class="_ _6"></span>e<span class="_"> </span>2<span class="_ _6"></span>-2<span class="_ _6"></span>.<span class="fc0 ls52">, <span class="fc1">VREF </span></span></span></span></div><div class="t m0 x7 hb y4d ff5 fs5 fc1 sc0 ls80 ws0">Source Con<span class="_ _4"></span>siderations<span class="fc0 ls63">, updated </span><span class="ls57">Ta<span class="_ _7"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>2<span class="_ _7"></span>-<span class="_ _1"> </span>2<span class="_ _1"> </span><span class="fc0 ls52">, and added warning to </span><span class="ls81">2.5.7<span class="_ _e"> </span>MIO Pin<span class="_ _2"></span> </span></span></div><div class="t m0 x7 hb y4e ff5 fs5 fc1 sc0 ls4e ws0">Electrical P<span class="_ _4"></span>arameters<span class="fc0 ls78">. Added </span><span class="ls77">Initializa<span class="_ _4"></span>tion of L1 Cach<span class="_ _2"></span>es<span class="fc0 ls52">, </span><span class="ls40">3.2.4<span class="_ _e"> </span>Memory Ordering<span class="fc0 ls52">, </span></span></span></div><div class="t m0 x7 hb y4f ff5 fs5 fc0 sc0 ls7b ws0">expanded <span class="fc1 ls73">3.2.5<span class="_ _14"> </span>Memory Manage<span class="ls59">ment U<span class="_ _6"></span>nit (MMU)</span></span><span class="ls82">, ad<span class="_ _2"></span>ded <span class="fc1 ls53">Cache Lockdown by W<span class="_ _4"></span>ay </span></span></div><div class="t m0 x7 hb y50 ff5 fs5 fc1 sc0 ls53 ws0">Sequence<span class="fc0 ls83"> a<span class="_ _6"></span>nd<span class="_ _6"></span> </span><span class="ls64">3.9<span class="_ _e"> </span>CPU <span class="_ _4"></span>I<span class="_ _6"></span>nitialization <span class="_ _4"></span>Sequence<span class="fc0 ls44">. Added <span class="_ _4"></span><span class="fc1 ls64">7z007s and <span class="_ _4"></span>7z010 Device <span class="_ _2"></span>Notice<span class="fc0 ls5"> </span></span></span></span></div><div class="t m0 x7 hb y51 ff5 fs5 fc0 sc0 ls4e ws0">and <span class="_ _4"></span>expanded <span class="_ _4"></span><span class="fc1 ls57">Ta<span class="_ _7"></span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>4<span class="_ _1"></span>-<span class="_ _1"></span>7<span class="_ _1"></span><span class="fc0 ls58">. <span class="_ _4"></span>Updated <span class="_ _4"></span>and <span class="_ _4"></span>expanded <span class="_ _0"></span>tables <span class="_ _4"></span>in <span class="_ _4"></span><span class="fc1 ls62">6.3.4<span class="_ _e"> </span>Quad-SPI <span class="_ _4"></span>Boot<span class="_ _6"></span><span class="fc0 ls43"> <span class="_ _0"></span>through </span></span></span></span></div><div class="t m0 x7 hb y52 ff5 fs5 fc1 sc0 ls84 ws0">6.3.13<span class="_ _e"> </span>P<span class="_ _4"></span>ost<span class="_ _6"></span> BootROM S<span class="_ _4"></span>tate<span class="fc0 ls6b">, reworked </span><span class="ls50">6.3.6<span class="_ _e"> </span>Debug Status<span class="fc0 ls4e">, and a<span class="_ _2"></span>dded <span class="fc1 ls40">6.3.13<span class="_ _e"> </span>P<span class="_ _4"></span>ost </span></span></span></div><div class="t m0 x7 hb y53 ff5 fs5 fc1 sc0 ls7c ws0">BootROM State<span class="fc0 ls55"> and<span class="_ _4"></span> <span class="fc1 ls73">AXI and DMA Done Status Interrupts</span><span class="ls60">. R<span class="_ _4"></span>eworked <span class="fc1 ls57">Ta<span class="_ _1"></span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>7<span class="_ _1"></span>-<span class="_ _1"></span>4<span class="_ _1"></span></span><span class="ls85">. Added </span></span></span></div><div class="t m0 x7 hb y54 ff5 fs5 fc1 sc0 ls62 ws0">8.1.2<span class="_ _e"> </span>Notices<span class="fc0 ls52">, </span><span class="ls66">Interrupt to PS In<span class="ls75">te<span class="_ _6"></span>rrupt Controller<span class="fc0 ls86">, and </span><span class="ls6a">Res<span class="_ _6"></span>et<span class="_ _6"></span><span class="fc0 ls50">. R<span class="_ _4"></span>eorganized and </span></span></span></span></div><div class="t m0 x7 hb y55 ff5 fs5 fc0 sc0 ls7b ws0">expanded <span class="fc1 ls87">Chapter<span class="_"> </span>9, DMA Controller</span><span class="ls67">. Added <span class="fc1 ls50">10.1.3<span class="_ _e"> </span>Notices</span>, expanded <span class="fc1 ls64">10.1.6<span class="_ _e"> </span>I/O </span></span></div><div class="t m0 x7 hb y56 ff5 fs5 fc1 sc0 ls88 ws0">Signals<span class="fc0 ls82">, added </span><span class="ls4e">10.6.12<span class="_ _e"> </span>DRAM Write Latency R<span class="_ _4"></span>estriction<span class="fc0 ls52">, </span><span class="ls7e">10.8.1<span class="_ _e"> </span>EC<span class="_ _2"></span>C Initialization<span class="_ _4"></span><span class="fc0 ls52">, </span></span></span></div><div class="t m0 x7 hb y57 ff5 fs5 fc1 sc0 ls89 ws0">1<span class="_ _6"></span>0<span class="_ _6"></span>.<span class="_ _6"></span>8<span class="_ _6"></span>.<span class="_ _6"></span>4<span class="_ _c"> </span>E<span class="_ _7"></span>CC<span class="_ _7"></span> P<span class="_ _6"></span>r<span class="_ _6"></span>o<span class="_ _6"></span>g<span class="_ _6"></span>r<span class="_ _6"></span>a<span class="_ _6"></span>m<span class="_ _7"></span>m<span class="_ _6"></span>i<span class="_ _6"></span>n<span class="_ _6"></span>g<span class="_ _6"></span> M<span class="_ _6"></span>o<span class="_ _6"></span>d<span class="_ _7"></span>e<span class="_ _6"></span>l<span class="_ _6"></span><span class="fc0 ls4e">, <span class="_ _4"></span>and <span class="_ _4"></span><span class="fc1 ls4c">10.9.1<span class="_ _e"> </span>Operating <span class="_ _4"></span>Modes<span class="fc0 ls4d">. <span class="_ _4"></span>Added <span class="_ _4"></span><span class="fc1 ls74">12.2.4<span class="_ _14"> </span>I/O<span class="_ _6"></span> <span class="_ _0"></span>Mod<span class="_ _6"></span>e </span></span></span></span></div><div class="t m0 x7 hb y58 ff5 fs5 fc1 sc0 ls8a ws0">Consider<span class="_ _6"></span>ations<span class="fc0 ls8b"> and upd<span class="_ _4"></span>ated <span class="fc1 ls63">12.3.5<span class="_ _e"> </span>Rx/T<span class="_ _0"></span>x FIFO R<span class="_ _4"></span>esponse to I/O Comm<span class="_ _4"></span>and Sequences<span class="fc0 ls52">. </span></span></span></div><div class="t m0 x7 hb y59 ff5 fs5 fc0 sc0 ls6a ws0">Re<span class="_ _6"></span>wo<span class="_ _6"></span>rk<span class="_ _6"></span>ed<span class="_ _6"></span> <span class="fc1 ls4d">16.3.3<span class="_ _e"> </span>I/O Configuration<span class="fc0">, added </span><span class="ls6f">16.4<span class="_ _14"> </span>IEEE <span class="_ _6"></span>1588 Time S<span class="_ _4"></span>tamping<span class="fc0 ls4f"> and </span></span></span></div><div class="t m0 x7 hb y5a ff5 fs5 fc1 sc0 ls53 ws0">16.6.7<span class="_ _e"> </span>MIO Pin Considerations<span class="fc0 ls67">. Added </span><span class="ls4f">18.2.7<span class="_ _14"> </span>C<span class="_ _6"></span>AN0-to-CAN1 Connection<span class="fc0 ls4c">. Expanded </span></span></div><div class="t m0 x7 hb y5b ff5 fs5 fc1 sc0 ls4c ws0">19.1<span class="_ _e"> </span>Introduction<span class="fc0 ls52">, <span class="_ _0"></span><span class="fc1 ls40">19.1.3<span class="_ _e"> </span>No<span class="_ _6"></span>tices<span class="fc0 ls5c">, <span class="_ _0"></span>and <span class="_ _4"></span><span class="fc1 ls57">Ta<span class="_ _1"> </span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>1<span class="_ _1"> </span>9<span class="_ _1"></span>-<span class="_ _1"></span>1<span class="_ _1"> </span><span class="fc0 ls60">. <span class="_ _4"></span>Added <span class="_ _0"></span><span class="fc1 ls3">Receiver <span class="_ _4"></span>Timeo<span class="_ _6"></span>ut <span class="_ _0"></span>Mech<span class="_ _6"></span>anism<span class="fc0 ls52">, </span></span></span></span></span></span></span></div><div class="t m0 x7 hb y5c ff5 fs5 fc0 sc0 ls63 ws0">updated <span class="fc1 ls4b">Figure<span class="_"> </span>19-7</span><span class="ls56">. Add<span class="_ _4"></span>ed <span class="fc1 ls48">19.2.9<span class="_ _e"> </span>UAR<span class="_ _4"></span>T0-to-UAR<span class="_ _4"></span>T1 Connection<span class="fc0 ls55"> and<span class="_ _4"></span> <span class="fc1 ls6f">19.2.<span class="_ _6"></span>10<span class="_ _14"> </span>Status </span></span></span></span></div><div class="t m0 x7 hb y5d ff5 fs5 fc1 sc0 ls64 ws0">and Interrupts<span class="fc0 ls58">, expand<span class="_ _2"></span>ed <span class="fc1 ls4a">19.2.11<span class="_ _14"> </span>Modem Control</span><span class="ls86">, reworked <span class="fc1 ls88">19.3<span class="_ _e"> </span>Programm<span class="_ _6"></span>ing Guide</span><span class="ls5"> </span></span></span></div><div class="t m0 x7 hb y5e ff5 fs5 fc0 sc0 ls4d ws0">and <span class="fc1 ls42">19.4.2<span class="_ _14"> </span>Resets</span><span class="ls44">. <span class="_ _2"></span>Added <span class="_ _2"></span><span class="fc1 ls41">20.2.7<span class="_ _e"> </span>I2C0-to-I2C1 Connection<span class="fc0 ls4e">. Added <span class="_ _4"></span><span class="fc1 ls50">21.1.2<span class="_ _e"> </span>PL Resources </span></span></span></span></div><div class="t m0 x7 hb y5f ff5 fs5 fc1 sc0 ls82 ws0">by Device T<span class="_ _0"></span>ype<span class="fc0 ls52">, </span><span class="ls8a">V<span class="_ _4"></span>olt<span class="_ _6"></span>age Level Shift<span class="_ _6"></span>ers<span class="fc0 ls41"> and reorganized content of </span><span class="ls6c">Chapter<span class="_"> </span>21, </span></span></div><div class="t m0 x7 hb y60 ff5 fs5 fc1 sc0 ls6c ws0">Programmable Logic Description<span class="fc0 ls78">. Added </span><span class="ls75">25.7.1<span class="_ _e"> </span>Clock Throttle<span class="fc0 ls8c">. Expanded </span><span class="ls4c">26.4.1<span class="_ _14"> </span>PL </span></span></div><div class="t m0 x7 hb y61 ff5 fs5 fc1 sc0 ls52 ws0">General Purpose User R<span class="_ _4"></span>esets<span class="fc0">. Updated register database in sections </span><span class="ls50">B.3<span class="_ _e"> </span>Module </span></div><div class="t m0 x7 hb y62 ff5 fs5 fc1 sc0 ls67 ws0">Summary<span class="fc0 ls8d"> through<span class="_ _4"></span> <span class="fc1 ls8e">B.34<span class="_ _e"> </span>USB Controll<span class="_ _4"></span>er (usb)<span class="fc0 ls62"> in </span><span class="ls4d">Appendix<span class="_"> </span>B<span class="fc0 ls5">.</span></span></span></span></div><div class="t m0 x6 hb y63 ff5 fs5 fc0 sc0 ls73 ws0">11/16/2012<span class="_ _a"> </span>1.4<span class="_ _b"> </span>Changed <span class="_ _0"></span>second <span class="_ _0"></span>bullet <span class="_ _4"></span>under <span class="_ _0"></span><span class="fc1 ls8f">N<span class="_ _7"></span>A<span class="_ _7"></span>N<span class="_ _7"></span>D<span class="_ _1"></span> F<span class="_ _7"></span>l<span class="_ _7"></span>a<span class="_ _7"></span>s<span class="_ _1"></span>h<span class="_ _7"></span> I<span class="_ _7"></span>n<span class="_ _7"></span>t<span class="_ _1"></span>e<span class="_ _7"></span>r<span class="_ _7"></span>f<span class="_ _7"></span>a<span class="_ _1"></span>c<span class="_ _7"></span>e<span class="_ _7"></span><span class="fc0 ls90"> f<span class="_ _7"></span>r<span class="_ _7"></span>o<span class="_ _7"></span>m<span class="_ _7"></span> “</span></span></div><div class="t m0 xe h9 y64 ff5 fs2 fc0 sc0 ls91 ws0">U<span class="_ _7"></span>p<span class="_ _1"></span> t<span class="_ _7"></span>o<span class="_ _1"></span> a<span class="_ _7"></span> 4<span class="_ _1"></span> G<span class="_ _7"></span>B<span class="_ _1"></span> d<span class="_ _1"></span>e<span class="_ _7"></span>v<span class="_ _1"></span>i<span class="_ _7"></span>c<span class="_ _1"></span>e<span class="_ _7"></span>”<span class="_ _1"></span> t<span class="_ _7"></span>o<span class="_ _1"></span> <span class="fs5 ls5">“<span class="_ _6"></span></span><span class="ls92">Up </span></div><div class="t m0 x7 h9 y65 ff5 fs2 fc0 sc0 ls93 ws0">to a 1 GB device” in </div><div class="t m0 xf hb y66 ff5 fs5 fc1 sc0 ls94 ws0">Chapter<span class="_"> </span>1<span class="_ _4"></span>1, Stati<span class="_ _4"></span>c Memory Controller<span class="_ _2"></span><span class="fc0 ls5">.</span></div><div class="t m0 x5 h5 y67 ff3 fs2 fc0 sc0 ls3f ws0">Date<span class="_ _8"> </span>V<span class="_ _4"></span>ersion<span class="_ _9"> </span>Revision</div><div class="c xb y3f w2 hd"><div class="t m1 xc he y40 ff7 fs6 fc2 sc0 ls5 ws0"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' 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<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626601d44c65f41259243370/bg4.jpg"><div class="t m0 x2 h5 y4 ff3 fs2 fc0 sc0 ls3 ws0">Zynq-700<span class="_ _2"></span>0 SoC T<span class="_ _0"></span>echnical Re<span class="_ _2"></span>fer<span class="_ _4"></span>ence Manual<span class="_ _12"> </span><span class="ff4 fc1 ls4">www<span class="_ _4"></span>.xilinx.com<span class="_ _5"> </span><span class="ff3 fc0 ls5">4</span></span></div><div class="t m0 x2 h6 y5 ff4 fs2 fc0 sc0 ls6 ws0">UG585 (v1.12.2) July 1, 2018</div><div class="t m0 x6 hb y1 ff5 fs5 fc0 sc0 ls43 ws0">03/07/2013<span class="_ _a"> </span>1.5<span class="_ _b"> </span>Added 7z100 device a<span class="ls73">nd made minor clarifications t<span class="ls95">o <span class="fc1 ls66">Chapter<span class="_"> </span>1, Introduction</span><span class="ls6d">. Made </span></span></span></div><div class="t m0 x7 hb y68 ff5 fs5 fc0 sc0 ls85 ws0">minor clarifications <span class="_ _4"></span>to <span class="fc1 ls58">Chapter<span class="_"> </span>2, Signals, Interfaces, and Pins</span><span class="ls52">, <span class="fc1 ls6d">Cha<span class="_ _4"></span>p<span class="_ _6"></span>ter<span class="_"> </span>3, App<span class="_ _4"></span>lication </span></span></div><div class="t m0 x7 hb y69 ff5 fs5 fc1 sc0 ls64 ws0">Processing Unit<span class="fc0 ls52">, </span>Chapter<span class="_"> </span>4, System Addresses<span class="fc0 ls5c">, and </span><span class="ls42">Chapter<span class="_"> </span>5, Interconnect<span class="_ _6"></span><span class="fc0 ls70">. Clarified<span class="_ _6"></span> </span></span></div><div class="t m0 x7 hb y6a ff5 fs5 fc0 sc0 ls74 ws0">section <span class="fc1 ls6c">6.1<span class="_ _e"> </span>Introduction</span><span class="ls42"> and other sec<span class="_ _6"></span>tions, and added <span class="fc1 ls73">PS Independent JT<span class="_ _0"></span>AG </span></span></div><div class="t m0 x7 hb y6b ff5 fs5 fc1 sc0 ls62 ws0">Non-Secure Boot<span class="_ _6"></span><span class="fc0"> section in </span><span class="ls77">Chapter<span class="_"> </span>6, Boot<span class="_ _4"></span> and Configurati<span class="_ _2"></span>on<span class="fc0 ls67">. Made minor </span></span></div><div class="t m0 x7 hb y6c ff5 fs5 fc0 sc0 ls4e ws0">clarifications to <span class="fc1 ls66">Chapter<span class="_"> </span>7, Interrupts</span><span class="ls52">, <span class="fc1 ls50">Chapter<span class="_"> </span>8, Timers</span>, <span class="fc1 ls40">Chapter<span class="_"> </span>9, DMA Controller</span>, </span></div><div class="t m0 x7 hb y6d ff5 fs5 fc1 sc0 ls40 ws0">Chapter<span class="_"> </span>10, DDR Memory Controller<span class="fc0 ls52">, </span><span class="ls5f">Chapter<span class="_"> </span>11, S<span class="_ _4"></span>tatic Mem<span class="_ _4"></span>ory Controller<span class="fc0 ls86">, and </span></span></div><div class="t m0 x7 hb y6e ff5 fs5 fc1 sc0 ls52 ws0">Chapter<span class="_"> </span>12, Quad-SPI Flash Controller<span class="fc0 ls8c">. Ex<span class="_ _2"></span>panded <span class="fc1 ls6f">12.2<span class="_ _14"> </span>Funct<span class="_ _6"></span>ional Description</span><span class="ls62"> in </span></span></div><div class="t m0 x7 hb y6f ff5 fs5 fc1 sc0 ls52 ws0">Chapter<span class="_"> </span>12, Quad-SPI Flash Controller<span class="fc0 ls7a">. Made minor cla<span class="ls59">rifications to </span></span><span class="ls6c">Chapter<span class="_"> </span>13, </span></div><div class="t m0 x7 hb y70 ff5 fs5 fc1 sc0 ls53 ws0">SD/SDIO Control<span class="_ _2"></span>ler<span class="fc0 ls8e">. <span class="_ _4"></span>Made major <span class="_ _4"></span>clarification<span class="_ _4"></span>s/updates <span class="_ _4"></span>to <span class="fc1 ls50">Chapter<span class="_"> </span>14, <span class="_ _4"></span>General Purpose </span></span></div><div class="t m0 x7 hb y71 ff5 fs5 fc1 sc0 ls77 ws0">I/O <span class="_ _4"></span>(GPIO)<span class="fc0 ls96">. <span class="_ _6"></span>Rew<span class="_ _6"></span>or<span class="_ _6"></span>k<span class="_ _6"></span>ed<span class="_ _6"></span> an<span class="_ _6"></span>d<span class="_ _6"></span> ex<span class="_ _6"></span>pa<span class="_ _6"></span>n<span class="_ _6"></span>de<span class="_ _6"></span>d </span><span class="ls83">C<span class="_ _6"></span>h<span class="_ _6"></span>ap<span class="_ _6"></span>te<span class="_ _6"></span>r<span class="_ _13"> </span>1<span class="_ _6"></span>5,<span class="_ _6"></span> US<span class="_ _6"></span>B H<span class="_ _6"></span>os<span class="_ _6"></span>t<span class="_ _6"></span>, D<span class="_ _6"></span>ev<span class="_ _6"></span>i<span class="_ _6"></span>ce<span class="_ _6"></span>, a<span class="_ _6"></span>nd<span class="_ _6"></span> OT<span class="_ _2"></span>G<span class="_ _6"></span> Co<span class="_ _6"></span>nt<span class="_ _6"></span>ro<span class="_ _6"></span>l<span class="_ _6"></span>le<span class="_ _6"></span>r<span class="fc0 ls52">. </span></span></div><div class="t m0 x7 hb y72 ff5 fs5 fc0 sc0 ls7b ws0">Made minor c<span class="_ _4"></span>larifications to <span class="fc1 ls6d">Chapter<span class="_"> </span>16, Gigabit Etherne<span class="_ _2"></span>t Controller<span class="fc0 ls4b">. R<span class="_ _4"></span>eworked and </span></span></div><div class="t m0 x7 hb y73 ff5 fs5 fc0 sc0 ls7b ws0">expanded <span class="fc1 ls8c">Chap<span class="_ _2"></span>ter<span class="_"> </span>17, SP<span class="_ _4"></span>I Controller<span class="fc0 ls7a">. Made minor cla<span class="ls59">rifications to </span></span><span class="ls50">Chapter<span class="_"> </span>18, CAN </span></span></div><div class="t m0 x7 hb y74 ff5 fs5 fc1 sc0 ls66 ws0">Controller<span class="fc0 ls67">, and </span><span class="ls42">Chapter<span class="_"> </span>19, UAR<span class="_ _4"></span>T Controller<span class="fc0 ls52">. Made major clarifications/updates to </span></span></div><div class="t m0 x7 hb y75 ff5 fs5 fc1 sc0 ls8e ws0">Chapter<span class="_"> </span>2<span class="_ _2"></span>0, <span class="_ _0"></span>I2C <span class="_ _4"></span>Contro<span class="_ _2"></span>ller<span class="fc0 ls4b"> <span class="_ _0"></span>(added <span class="_ _4"></span>new <span class="_ _0"></span>sections, <span class="_ _4"></span><span class="fc1">20.3<span class="_ _e"> </span>Programmer’s <span class="_ _0"></span>Guide<span class="fc0">, <span class="_ _4"></span><span class="fc1 ls50">20.4<span class="_ _14"> </span>System </span></span></span></span></div><div class="t m0 x7 hb y76 ff5 fs5 fc1 sc0 ls40 ws0">Functions<span class="fc0 ls86">, and </span><span class="ls8e">20.5<span class="_ _14"> </span>I/O Interface<span class="fc0 ls85">). Mad<span class="_ _4"></span>e minor clarifications to <span class="fc1 ls5f">Chap<span class="_ _4"></span>ter<span class="_"> </span>21, </span></span></span></div><div class="t m0 x7 hb y77 ff5 fs5 fc1 sc0 ls86 ws0">Programmable <span class="_ _d"></span>Logic <span class="_ _0"></span>Description<span class="fc0 ls6c"> <span class="_ _0"></span>and <span class="_ _0"></span>added <span class="_ _0"></span>new <span class="_ _0"></span>sections <span class="_ _0"></span><span class="fc1 ls4b">21.1.2<span class="_ _e"> </span>PL <span class="_ _0"></span>Resources <span class="_ _d"></span>by <span class="_ _0"></span>Device </span></span></div><div class="t m0 x7 hb y78 ff5 fs5 fc1 sc0 ls97 ws0">Ty<span class="_ _6"></span>p<span class="_ _6"></span>e<span class="_ _6"></span><span class="fc0 ls98"> a<span class="_ _6"></span>nd<span class="_ _6"></span> </span><span class="ls62">21.1.3<span class="_ _e"> </span>Notices<span class="fc0 ls64">. Made <span class="_ _4"></span>minor <span class="_ _4"></span>clarif<span class="_ _6"></span>ications <span class="_ _4"></span>to <span class="_ _4"></span><span class="fc1 ls86">Chapter<span class="_"> </span>22, Progr<span class="_ _4"></span>ammable Logic </span></span></span></div><div class="t m0 x7 hb y79 ff5 fs5 fc1 sc0 ls52 ws0">Design Guide<span class="fc0 ls7d"> and </span><span class="ls86">Chapter<span class="_ _11"> </span>23, Programmable Logic <span class="_ _4"></span>T<span class="_ _4"></span>est and Debug<span class="_ _2"></span><span class="fc0 ls58">. R<span class="_ _2"></span>eworked and </span></span></div><div class="t m0 x7 hb y7a ff5 fs5 fc0 sc0 ls7b ws0">expanded <span class="fc1 ls80">Chap<span class="_ _2"></span>ter<span class="_"> </span>24, P<span class="_ _4"></span>ower Ma<span class="_ _4"></span>n<span class="_ _6"></span>a<span class="_ _4"></span>gement<span class="fc0 ls62">. Made minor c<span class="_ _6"></span>larifications to </span><span class="ls6c">Chapter<span class="_"> </span>25, </span></span></div><div class="t m0 x7 hb y7b ff5 fs5 fc1 sc0 ls4c ws0">Clocks<span class="fc0 ls52">, </span><span class="ls6d">Chapter<span class="_"> </span>26, R<span class="_ _4"></span>eset System<span class="fc0 ls52">, </span><span class="ls99">Chapter<span class="_"> </span>27, JT<span class="_ _4"></span>AG and DAP Subsystem<span class="fc0 ls52">, </span><span class="ls4c">Chapter<span class="_"> </span>28, </span></span></span></div><div class="t m0 x7 hb y7c ff5 fs5 fc1 sc0 ls4e ws0">S<span class="_ _2"></span>ystem T<span class="_ _0"></span>est and Debug<span class="fc0 ls5c">, and </span><span class="ls7c">Chapter<span class="_ _13"> </span>29, On-Chip Mem<span class="_ _6"></span>ory (OCM)<span class="fc0 ls66">. R<span class="_ _2"></span>eworked and </span></span></div><div class="t m0 x7 hb y7d ff5 fs5 fc0 sc0 ls7b ws0">expanded <span class="fc1 ls4f">Chapter<span class="_"> </span>30, XADC Interface</span><span class="ls48">. Made minor cla<span class="ls40">rifications to </span></span></div><div class="t m0 x10 hb y7e ff5 fs5 fc1 sc0 ls6c ws0">Chapter<span class="_"> </span>31, PCI </div><div class="t m0 x7 hb y7f ff5 fs5 fc1 sc0 ls48 ws0">Express<span class="fc0 ls9a">.<span class="_ _6"></span> R<span class="_ _6"></span>e<span class="_ _7"></span>w<span class="_ _7"></span>o<span class="_ _7"></span>r<span class="_ _6"></span>k<span class="_ _7"></span>e<span class="_ _7"></span>d<span class="_ _7"></span> a<span class="_ _7"></span>n<span class="_ _6"></span>d<span class="_ _7"></span> e<span class="_ _7"></span>x<span class="_ _7"></span>p<span class="_ _7"></span>a<span class="_ _6"></span>n<span class="_ _7"></span>d<span class="_ _7"></span>e<span class="_ _7"></span>d<span class="_ _6"></span> </span><span class="ls52">Chapter<span class="_"> </span>32, <span class="_ _4"></span>Device <span class="_ _0"></span>Secure <span class="_ _4"></span>Boot<span class="fc0 ls6b">. <span class="_ _0"></span>Updated <span class="_ _4"></span><span class="fc1 ls67">Appendix<span class="_"> </span>A, </span></span></span></div><div class="t m0 x7 hb y80 ff5 fs5 fc1 sc0 ls81 ws0">Additional<span class="_ _4"></span> Resourc<span class="_ _4"></span>es<span class="fc0 ls56">. Updated register database in sections <span class="_ _4"></span><span class="fc1 ls81">B.3<span class="_ _e"> </span>Module Summary<span class="fc0 ls5"> </span></span></span></div><div class="t m0 x7 hb y81 ff5 fs5 fc0 sc0 ls9b ws0">through <span class="_ _4"></span><span class="fc1 ls5e">B.34<span class="_ _e"> </span>USB Controller (usb)<span class="_ _4"></span><span class="fc0 ls62"> in <span class="fc1 ls4b">Appendix<span class="_"> </span>B</span><span class="ls5">.</span></span></span></div><div class="t m0 x6 hb y82 ff5 fs5 fc0 sc0 ls64 ws0">06/28/2013<span class="_ _a"> </span>1.6<span class="_ _b"> </span>Added icons <span class="_ _4"></span>where ap<span class="ls4c">plicable. <span class="_ _4"></span>Enhanced first <span class="_ _4"></span>sente<span class="ls6c">nce under <span class="fc1 ls59">Quad-SPI <span class="_ _4"></span>Cont<span class="_ _6"></span>roller<span class="fc0 ls5b"> i<span class="_ _6"></span>n c.<span class="_ _6"></span> </span></span></span></span></div><div class="t m0 x7 hb y83 ff5 fs5 fc0 sc0 ls4d ws0">Clarified <span class="_ _4"></span>first <span class="_ _4"></span>paragraph, added<span class="_ _4"></span> step <span class="_ _4"></span>2, <span class="_ _4"></span>and <span class="_ _4"></span>clarified step <span class="_ _4"></span>5 <span class="_ _4"></span>i<span class="ls64">n <span class="_ _4"></span>section <span class="fc1 ls73">2.4<span class="_ _14"> </span>PS–PL V<span class="_ _0"></span>oltage </span></span></div><div class="t m0 x7 hb y84 ff5 fs5 fc1 sc0 ls9c ws0">Level Shifter <span class="_ _6"></span>Enables<span class="fc0 ls79">. Change<span class="_ _6"></span>d “drive strength” <span class="_ _6"></span>t<span class="ls58">o “slew ra<span class="_ _2"></span>te” <span class="ls4e">in section <span class="fc1 ls7d">2.5.7<span class="_ _14"> </span>MIO Pin </span></span></span></span></div><div class="t m0 x7 hb y85 ff5 fs5 fc1 sc0 ls4e ws0">Electrical P<span class="_ _4"></span>arameters<span class="fc0 ls82">. Added second sentence and<span class="_ _2"></span> updated <span class="fc1 ls57">Ta<span class="_ _7"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>2<span class="_ _7"></span>-<span class="_ _1"> </span>1<span class="_ _1"> </span>1<span class="_ _10"> </span></span><span class="ls99"> in section </span></span></div><div class="t m0 x7 hb y86 ff5 fs5 fc1 sc0 ls53 ws0">2.7.4<span class="_ _e"> </span>Idle AXI, DDR Urgent/A<span class="ls4f">rb, SRAM Interrupt Signals<span class="fc0 ls6c">. Corrected Note 4 in </span><span class="ls51">Ta<span class="_ _7"></span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>4<span class="_ _7"></span>-<span class="_ _1"></span>1<span class="_ _1"></span><span class="fc0 ls5"> </span></span></span></div><div class="t m0 x7 hb y87 ff5 fs5 fc0 sc0 ls4d ws0">and <span class="fc1 ls57">Ta<span class="_ _7"></span>b<span class="_ _10"> </span>l<span class="_ _1"></span>e<span class="_ _f"> </span>4<span class="_ _7"></span>-<span class="_ _1"> </span>2<span class="_ _1"> </span></span><span class="ls9d">. Mad<span class="_ _6"></span>e minor clarific<span class="_ _6"></span>ations and added ne<span class="_ _6"></span>w <span class="fc1 ls6f">RSA Authentication Time</span><span class="ls5"> </span></span></div><div class="t m0 x7 hb y88 ff5 fs5 fc0 sc0 ls74 ws0">section to <span class="fc1 ls40">Chapter<span class="_"> </span>6, Boo<span class="_ _6"></span>t and Configuration</span><span class="ls85">. Made mi<span class="_ _4"></span>n<span class="_ _6"></span>or<span class="_ _4"></span> clarifi<span class="ls42">cations to section<span class="_ _6"></span>s </span></span></div><div class="t m0 x7 hb y89 ff5 fs5 fc1 sc0 ls85 ws0">7.2.2<span class="_ _e"> </span>CPU Priva<span class="_ _2"></span>te P<span class="_ _4"></span>eripheral Interrupts (PPI)<span class="_ _2"></span><span class="fc0 ls4f"> and <span class="fc1 ls64">7.2.3<span class="_ _e"> </span>Shared P<span class="_ _2"></span>eripheral Interrupts </span></span></div><div class="t m0 x7 hb y8a ff5 fs5 fc1 sc0 ls43 ws0">(SPI)<span class="fc0 ls70">, and <span class="_ _6"></span>updated </span><span class="ls57">Ta<span class="_ _1"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>7<span class="_ _7"></span>-<span class="_ _1"> </span>4<span class="_ _1"> </span><span class="fc0 ls7d"> and </span>Ta<span class="_ _1"> </span>b<span class="_ _1"> </span>l<span class="_ _1"> </span>e<span class="_ _f"> </span>7<span class="_ _1"></span>-<span class="_ _1"></span>5<span class="_ _1"></span><span class="fc0 ls6b">. Clarified first row in </span>Ta<span class="_ _7"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>9<span class="_ _7"></span>-<span class="_ _1"> </span>1<span class="_ _10"> </span>2<span class="_ _7"></span><span class="fc0 ls4e">. Added tip </span></span></div><div class="t m0 x7 hb y8b ff5 fs5 fc0 sc0 ls84 ws0">to <span class="_ _0"></span>sectio<span class="_ _6"></span>n <span class="_ _d"></span><span class="fc1 ls67">10.4.3<span class="_ _e"> </span>Aging <span class="_ _4"></span>Counter<span class="fc0 ls4b">, <span class="_ _0"></span>added <span class="_ _0"></span>sentence <span class="_ _0"></span>to <span class="_ _4"></span><span class="fc1 ls6d">Write <span class="_ _0"></span>Leveling<span class="fc0 ls43">, <span class="_ _0"></span>and <span class="_ _0"></span>step <span class="_ _4"></span>2 <span class="_ _0"></span>in <span class="_ _4"></span>section </span></span></span></span></div><div class="t m0 x7 hb y8c ff5 fs5 fc1 sc0 ls7c ws0">10.9.2<span class="_ _e"> </span>Changing Cl<span class="_ _6"></span><span class="ls4c">ock Frequencies<span class="fc0 ls71">, and moved sect<span class="_ _6"></span>ion </span>10.9.6<span class="_ _e"> </span>DDR P<span class="_ _4"></span>ower Reduction<span class="fc0 ls5"> </span></span></div><div class="t m0 x7 hb y8d ff5 fs5 fc0 sc0 ls6f ws0">from <span class="fc1 ls48">Chapter<span class="_"> </span>24, P<span class="_ _4"></span>ower Management<span class="fc0 ls94"> to this chap<span class="_ _4"></span>ter. Added tip to sec<span class="_ _4"></span>tion </span></span></div><div class="t m0 x7 hb y8e ff5 fs5 fc1 sc0 ls9e ws0">11.2.2<span class="_ _e"> </span>Clocks<span class="fc0 ls4b">. Added <span class="_ _0"></span><span class="fc1 ls4a">T<span class="_ _0"></span>able<span class="_"> </span>12-<span class="_ _6"></span>8<span class="fc0 ls4e">. <span class="_ _4"></span>Added </span></span></span></div><div class="t m0 x11 h9 y8f ff5 fs2 fc0 sc0 ls9f ws0">MMC3.31 <span class="_ _4"></span>standard <span class="_ _4"></span>information <span class="_ _4"></span>to <span class="_ _4"></span>section </div><div class="t m0 x7 hb y90 ff5 fs5 fc1 sc0 ls67 ws0">13.1<span class="_ _e"> </span>Introduction<span class="_ _6"></span><span class="fc0 ls64">. Added step 6 to section </span><span class="ls8e">14.3.1<span class="_ _e"> </span>S<span class="_ _4"></span>tart-up Sequenc<span class="_ _2"></span>e<span class="fc0 ls53">, added section </span></span></div><div class="t m0 x7 hb y91 ff5 fs5 fc1 sc0 ls53 ws0">14.3.5<span class="_ _e"> </span>GPIO as W<span class="_ _4"></span>ake-up Event<span class="fc0 ls82">, added second paragraph to <span class="_ _4"></span><span class="fc1 ls7e">14.4.1<span class="_ _e"> </span>Clocks<span class="fc0 ls85">. Added </span></span></span></div><div class="t m0 x7 hb y92 ff5 fs5 fc0 sc0 ls74 ws0">section <span class="fc1 ls41">16.7<span class="_ _e"> </span>Known Issues<span class="_ _6"></span></span><span class="ls4b">. Ad<span class="_ _2"></span>ded note to <span class="fc1 ls53">17.4.2<span class="_ _14"> </span>Clocks</span><span class="ls67">. Changed value of 107<span class="_"> </span>Mb to </span></span></div><div class="t m0 x7 hb y93 ff5 fs5 fc0 sc0 ls87 ws0">140<span class="_"> </span>Mb in second sentence <span class="_ _6"></span>under section <span class="fc1 lsa0">21.4<span class="_ _14"> </span>Configuration</span><span class="ls4b">. Added values for the </span></div><div class="t m0 x7 hb y94 ff5 fs5 fc0 sc0 ls6f ws0">7z100 device in <span class="fc1 ls4a">T<span class="_ _0"></span>able<span class="_"> </span>21-2<span class="fc0 ls52">. Clarified first paragraph in section </span><span class="ls43">24.2.2<span class="_ _e"> </span>PL Po<span class="_ _2"></span>wer-down </span></span></div><div class="t m0 x7 hb y95 ff5 fs5 fc1 sc0 ls43 ws0">Control<span class="_ _6"></span><span class="fc0 ls77"> and<span class="_ _4"></span> updated <span class="fc1 ls57">Ta<span class="_ _1"></span>b<span class="_ _7"></span>l<span class="_ _10"> </span>e<span class="_ _f"> </span>2<span class="_ _7"></span>4<span class="_ _1"> </span>-<span class="_ _1"> </span>2<span class="_ _1"> </span></span><span class="ls41">. Added not<span class="_ _6"></span>e to section <span class="fc1">25.6.1<span class="_ _e"> </span>USB Clocks</span><span class="ls6b">, clarified </span></span></span></div><div class="t m0 x7 hb y96 ff5 fs5 fc0 sc0 ls66 ws0">second paragraph in section <span class="fc1 ls6c">25.10.4<span class="_ _e"> </span>PLLs</span><span class="ls48">, and added sentence to steps 2 and 3 in </span></div><div class="t m0 x7 hb y97 ff5 fs5 fc1 sc0 ls4d ws0">Software-Controlled PLL Update<span class="fc0 ls66"> section. Changed “RESET_REASON” to </span></div><div class="t m0 x7 hb y98 ff5 fs5 fc0 sc0 ls87 ws0">“REBOO<span class="_ _4"></span>T_ST<span class="_ _4"></span>A<span class="_ _4"></span>TUS <span class="_ _4"></span>in <span class="_ _4"></span>section <span class="fc1 ls4b">26.2.3<span class="_ _14"> </span>System <span class="_ _0"></span>Software <span class="_ _4"></span>Reset<span class="fc0">, <span class="_ _4"></span>added <span class="_ _4"></span>section <span class="_ _4"></span><span class="fc1">26.5<span class="_ _e"> </span>R<span class="_ _4"></span>egister </span></span></span></div><div class="t m0 x7 hb y99 ff5 fs5 fc1 sc0 lsa1 ws0">Overview<span class="fc0 ls40">, <span class="_ _4"></span>deleted <span class="_ _4"></span>first <span class="_ _4"></span>two <span class="_ _4"></span>rows <span class="_ _4"></span>from <span class="_ _4"></span><span class="fc1 ls51">Ta<span class="_ _1"> </span>b<span class="_ _1"> </span>l<span class="_ _1"></span>e<span class="_ _f"> </span>2<span class="_ _7"></span>6<span class="_ _1"></span>-<span class="_ _7"></span>2<span class="_ _1"> </span><span class="fc0 ls4d"> <span class="_ _4"></span>and <span class="_ _4"></span>modified <span class="_ _4"></span>last <span class="_ _4"></span>paragraph <span class="_ _4"></span>in <span class="_ _0"></span>section </span></span></span></div><div class="t m0 x7 hb y9a ff5 fs5 fc1 sc0 ls40 ws0">26.5.1<span class="_ _e"> </span>P<span class="_ _4"></span>ersist<span class="_ _6"></span>ent <span class="_ _0"></span>Registers<span class="fc0 ls6d">. <span class="_ _4"></span>Clarified <span class="_ _0"></span>section <span class="_ _4"></span><span class="fc1 ls88">29.1<span class="_ _e"> </span>Introdu<span class="_ _6"></span>ction<span class="fc0 ls58">, <span class="_ _4"></span>added <span class="_ _0"></span>three <span class="_ _4"></span>paragraphs </span></span></span></div><div class="t m0 x7 hb y9b ff5 fs5 fc0 sc0 ls84 ws0">to <span class="_ _4"></span><span class="fc1 ls43">S<span class="_ _4"></span>tarvation<span class="_ _6"></span> <span class="_ _0"></span>Scenarios<span class="fc0 ls58"> <span class="_ _4"></span>section, <span class="_ _4"></span>and <span class="_ _4"></span>added <span class="_ _0"></span><span class="fc1">29.2.5<span class="_ _e"> </span>Address <span class="_ _4"></span>Mapping<span class="fc0 ls56"> <span class="_ _0"></span>heading. <span class="_ _4"></span>Corrected </span></span></span></span></div><div class="t m0 x7 hb y9c ff5 fs5 fc0 sc0 ls7a ws0">spelling of “MCTRL” to “MCTL” in sections <span class="fc1">30.4<span class="_ _14"> </span>Programming Guide for the PS-XADC </span></div><div class="t m0 x7 hb y9d ff5 fs5 fc1 sc0 ls54 ws0">Interface<span class="_ _6"></span><span class="fc0 ls7d"> and </span><span class="ls4c">30.7.2<span class="_ _14"> </span>Resets<span class="fc0 ls52">. </span></span></div><div class="t m0 x5 h5 y9e ff3 fs2 fc0 sc0 ls3f ws0">Date<span class="_ _8"> </span>V<span class="_ _4"></span>ersion<span class="_ _9"> </span>Revision</div><div class="c xb y3f w2 hd"><div class="t m1 xc he y40 ff7 fs6 fc2 sc0 ls5 ws0"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return 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<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/626601d44c65f41259243370/bg5.jpg"><div class="t m0 x2 h5 y4 ff3 fs2 fc0 sc0 ls3 ws0">Zynq-700<span class="_ _2"></span>0 SoC T<span class="_ _0"></span>echnical Re<span class="_ _2"></span>fer<span class="_ _4"></span>ence Manual<span class="_ _12"> </span><span class="ff4 fc1 ls4">www<span class="_ _4"></span>.xilinx.com<span class="_ _5"> </span><span class="ff3 fc0 ls5">5</span></span></div><div class="t m0 x2 h6 y5 ff4 fs2 fc0 sc0 ls6 ws0">UG585 (v1.12.2) July 1, 2018</div><div class="t m0 x6 hb y1 ff5 fs5 fc0 sc0 ls6f ws0">06/28/2013<span class="_ _a"> </span>1.6</div><div class="t m0 xd hb y68 ff5 fs5 fc0 sc0 ls5 ws0">(<span class="_ _6"></span><span class="ff6 ls75">Cont’d</span>)</div><div class="t m0 x7 hb y1 ff5 fs5 fc0 sc0 ls53 ws0">Added <span class="_ _4"></span>section <span class="_ _4"></span><span class="fc1 ls40">31.5<span class="_ _14"> </span>Root <span class="_ _4"></span>Complex <span class="_ _4"></span>Use <span class="_ _4"></span>Case<span class="fc0 lsa2">.<span class="_ _6"></span> A<span class="_ _6"></span>d<span class="_ _7"></span>d<span class="_ _6"></span>e<span class="_ _6"></span>d<span class="_ _7"></span> F<span class="_ _6"></span>I<span class="_ _6"></span>P<span class="_ _7"></span>S<span class="_ _6"></span> s<span class="_ _6"></span>t<span class="_ _7"></span>a<span class="_ _6"></span>n<span class="_ _6"></span>d<span class="_ _7"></span>a<span class="_ _6"></span>r<span class="_ _6"></span>d<span class="_ _7"></span>s<span class="_ _6"></span> a<span class="_ _7"></span>n<span class="_ _6"></span>d<span class="_ _6"></span> c<span class="_ _7"></span>l<span class="_ _6"></span>a<span class="_ _6"></span>r<span class="_ _7"></span>i<span class="_ _6"></span>f<span class="_ _7"></span>i<span class="_ _6"></span>e<span class="_ _6"></span>d<span class="_ _7"></span> s<span class="_ _6"></span>e<span class="_ _6"></span>c<span class="_ _7"></span>t<span class="_ _6"></span>i<span class="_ _6"></span>o<span class="_ _7"></span>n<span class="_ _6"></span> </span></span></div><div class="t m0 x7 hb y68 ff5 fs5 fc1 sc0 ls64 ws0">32.1.2<span class="_ _e"> </span>Features<span class="fc0 ls43">, updated configuration file and<span class="_ _6"></span> secure boot pro<span class="ls6c">cess steps in </span></span></div><div class="t m0 x7 hb y69 ff5 fs5 fc1 sc0 ls4d ws0">Figure<span class="_"> </span>32-1<span class="fc0 ls71">, <span class="_ _4"></span>added <span class="_ _4"></span>boot <span class="_ _4"></span>time <span class="_ _4"></span>penalt<span class="_ _6"></span>y <span class="_ _0"></span>to <span class="_ _4"></span><span class="fc1 ls78">P<span class="_ _2"></span>ower <span class="_ _0"></span>on <span class="_ _4"></span>Reset<span class="fc0 ls6c"> <span class="_ _0"></span>section, <span class="_ _4"></span>changed <span class="_ _4"></span>“Secure <span class="_ _0"></span>Boo<span class="_ _6"></span>t” </span></span></span></div><div class="t m0 x7 hb y6a ff5 fs5 fc0 sc0 lsa3 ws0">heading to ”<span class="fc1 ls87">Secure FSBL Decryption</span><span class="ls66">”, changed “RO<span class="_ _2"></span>M code” <span class="_ _4"></span>t<span class="_ _6"></span>o <span class="_ _4"></span>“OCM ROM Memory” in </span></div><div class="t m0 x7 hb y6b ff5 fs5 fc1 sc0 ls4d ws0">Figure<span class="_"> </span>32-2<span class="fc0 ls99"> and “ROM” to “OCM ROM” in<span class="_ _6"></span> </span><span class="ls73">T<span class="_ _d"></span>able<span class="_"> </span>32-3<span class="fc0 ls52">, updated sections </span><span class="ls4d">32.2.7<span class="_ _e"> </span>Boot </span></span></div><div class="t m0 x7 hb y6c ff5 fs5 fc1 sc0 lsa4 ws0">Image an<span class="_ _6"></span>d Bitstream Decry<span class="_ _6"></span>p<span class="ls75">tion and Authentication<span class="fc0 ls52">, </span><span class="ls67">32.2.8<span class="_ _e"> </span>HMAC Signature<span class="fc0 ls52">, </span></span></span></div><div class="t m0 x7 hb y6d ff5 fs5 fc1 sc0 ls54 ws0">32.2.9<span class="_ _e"> </span>AES Key Management<span class="fc0 ls52">, <span class="_ _6"></span></span><span class="ls74">32.3.1<span class="_ _14"> </span>Non-Secu<span class="_ _6"></span>re Boot S<span class="_ _4"></span>tate<span class="fc0 ls52">, </span><span class="ls73">32.3.4<span class="_ _e"> </span>Boot Partition </span></span></div><div class="t m0 x7 hb y6e ff5 fs5 fc1 sc0 ls48 ws0">Search<span class="fc0 ls5c">, and </span><span class="ls59">32<span class="_ _6"></span>.3.7<span class="_ _14"> </span>Secure Boot <span class="_ _6"></span>Modes of Operation<span class="_ _6"></span><span class="fc0 ls58"> (dele<span class="_ _4"></span>ted T<span class="_ _0"></span>able 32-4, “Non-secure </span></span></div><div class="t m0 x7 hb y6f ff5 fs5 fc0 sc0 ls73 ws0">Boot Options”). Updated regi<span class="ls60">ster database in sections <span class="fc1 ls64">B.3<span class="_ _14"> </span>Module Summary</span><span class="ls7c"> through<span class="_ _6"></span> </span></span></div><div class="t m0 x7 hb y70 ff5 fs5 fc1 sc0 ls59 ws0">B.34<span class="_ _e"> </span>USB Controller (usb<span class="_ _6"></span>)<span class="fc0 ls5e"> in<span class="_ _4"></span> <span class="fc1 ls8d">Appendix<span class="_"> </span>B</span><span class="ls5">.</span></span></div><div class="t m0 x6 hb y9f ff5 fs5 fc0 sc0 ls43 ws0">02/11/2014<span class="_ _a"> </span>1.7<span class="_ _b"> </span>Added <span class="_ _4"></span>7z015 <span class="_ _4"></span>dev<span class="_ _6"></span>ice, <span class="_ _0"></span>updated device <span class="_ _4"></span>notices, <span class="_ _4"></span>and <span class="_ _4"></span>ma<span class="ls66">de <span class="_ _4"></span>minor <span class="_ _4"></span>c<span class="_ _6"></span>larifications <span class="_ _4"></span>throughout </span></div><div class="t m0 x7 hb ya0 ff5 fs5 fc0 sc0 ls4e ws0">document (denoted with chan<span class="ls6d">ge bar<span class="_ _2"></span>s). Added section <span class="fc1 ls65">3.10<span class="_ _14"> </span>Implementation-Defined </span></span></div><div class="t m0 x7 hb ya1 ff5 fs5 fc1 sc0 lsa5 ws0">Configur<span class="_ _4"></span>ations<span class="fc0 ls58">. <span class="_ _0"></span>Added <span class="_ _d"></span>sections <span class="_ _0"></span><span class="fc1 ls87">5.7<span class="_ _e"> </span>L<span class="_ _6"></span>oopback<span class="fc0 lsa6"> a<span class="_ _7"></span>n<span class="_ _7"></span>d<span class="_ _7"></span> </span><span class="ls73">5.8<span class="_ _e"> </span>Exclusive <span class="_ _0"></span>AXI <span class="_ _0"></span>Accesses<span class="fc0 ls4d">. <span class="_ _0"></span>Reworked </span></span></span></span></div><div class="t m0 x7 hb ya2 ff5 fs5 fc1 sc0 ls8e ws0">Chapter<span class="_"> </span>6<span class="_ _2"></span>, Bo<span class="_ _2"></span>ot a<span class="_ _4"></span>nd Configur<span class="_ _2"></span>ation<span class="fc0 ls67">. <span class="_ _4"></span>Added section <span class="fc1 ls6c">7.2.4<span class="_ _14"> </span>Interrupt Sensitivity, T<span class="_ _d"></span>argeting </span></span></div><div class="t m0 x7 hb ya3 ff5 fs5 fc1 sc0 ls65 ws0">and <span class="_ _4"></span>Handling<span class="fc0 ls79">. <span class="_ _4"></span>Added <span class="_ _4"></span>sections <span class="_ _2"></span><span class="fc1 ls6c">8.4.6<span class="_ _e"> </span>Clock <span class="_ _4"></span>Input <span class="_ _4"></span>Option <span class="_ _4"></span>for <span class="_ _4"></span>SWD<span class="_ _4"></span>T<span class="fc0 ls89"> a<span class="_ _6"></span>n<span class="_ _7"></span>d<span class="_ _6"></span> </span><span class="ls42">8.5.6<span class="_ _e"> </span>Clock <span class="_ _4"></span>Input </span></span></span></div><div class="t m0 x7 hb ya4 ff5 fs5 fc1 sc0 ls75 ws0">Option for Counter/Timer<span class="fc0 ls71">. Up<span class="_ _6"></span>dated section </span><span class="ls44">10.7<span class="_ _e"> </span>Regist<span class="_ _4"></span>er Overview<span class="fc0 ls6c">. Added section </span></span></div><div class="t m0 x7 hb ya5 ff5 fs5 fc1 sc0 ls78 ws0">11.7<span class="_ _14"> </span>N<span class="_ _6"></span>O<span class="_ _2"></span>R Flash Bandwidth<span class="fc0 lsa7">. Added sections <span class="_ _6"></span></span><span class="ls7b">AXI <span class="_ _4"></span>Read Comma<span class="_ _2"></span>nd Processing<span class="_ _2"></span><span class="fc0 ls7d"> and </span></span></div><div class="t m0 x7 hb ya6 ff5 fs5 fc1 sc0 ls81 ws0">12.2.7<span class="_ _14"> </span>Supported Memor<span class="_ _4"></span>y Read and<span class="_ _2"></span> Write Com<span class="_ _4"></span>mands<span class="fc0 ls4d">. Added section </span><span class="ls53">16.1.4<span class="_ _14"> </span>Clock </span></div><div class="t m0 x7 hb ya7 ff5 fs5 fc1 sc0 lsa8 ws0">Domains<span class="fc0 ls4c"> <span class="_ _6"></span>and reworked section </span><span class="ls42">16.7<span class="_ _14"> </span>Known Issues<span class="fc0 lsa9"> <span class="_ _6"></span>(previously tit<span class="_ _6"></span>led “Limitat<span class="_ _6"></span>ions”. </span></span></div><div class="t m0 x7 hb ya8 ff5 fs5 fc0 sc0 ls71 ws0">Updated <span class="_ _6"></span>section <span class="fc1 ls52">21.1.2<span class="_ _e"> </span>PL R<span class="_ _4"></span>esources by Device T<span class="_ _4"></span>ype<span class="fc0 ls4e"> and added section </span><span class="ls56">21.3.4<span class="_ _e"> </span>G<span class="_ _4"></span>TP </span></span></div><div class="t m0 x7 hb ya9 ff5 fs5 fc1 sc0 ls58 ws0">Low-P<span class="_ _4"></span>ower Serial T<span class="_ _0"></span>ransceivers<span class="fc0 ls78">. Added </span><span class="ls4d">P<span class="_ _4"></span>eripheral Clock Gating<span class="fc0 ls73"> subsection. Updated </span></span></div><div class="t m0 x7 hb yaa ff5 fs5 fc1 sc0 ls4a ws0">T<span class="_ _d"></span>able<span class="_ _13"> </span>26-1<span class="fc0 ls5a"> a<span class="_ _6"></span>n<span class="_ _6"></span>d<span class="_ _6"></span> </span>T<span class="_ _d"></span>able<span class="_"> </span>26-4<span class="fc0 ls58">. <span class="_ _2"></span>Updated <span class="_ _4"></span>register <span class="_ _4"></span>database <span class="_ _4"></span>in <span class="_ _4"></span>sections <span class="_ _4"></span><span class="fc1 ls66">B.3<span class="_ _e"> </span>Module Summary<span class="fc0 ls5"> </span></span></span></div><div class="t m0 x7 hb yab ff5 fs5 fc0 sc0 ls9b ws0">through <span class="_ _4"></span><span class="fc1 ls5e">B.34<span class="_ _e"> </span>USB Controller (usb)<span class="_ _4"></span><span class="fc0 ls62"> in <span class="fc1 ls4b">Appendix<span class="_"> </span>B</span><span class="ls5">.</span></span></span></div><div class="t m0 x6 hb yac ff5 fs5 fc0 sc0 ls40 ws0">09/16/2014<span class="_ _a"> </span>1.8<span class="_ _b"> </span>Added </div><div class="t m0 x12 h9 yad ff5 fs2 fc0 sc0 lsaa ws0">po<span class="_ _6"></span>si<span class="_ _6"></span>ti<span class="_ _6"></span>on<span class="_ _6"></span> in<span class="_ _6"></span>fo<span class="_ _6"></span>rm<span class="_ _6"></span>at<span class="_ _6"></span>io<span class="_ _6"></span>n fo<span class="_ _6"></span>r<span class="_ _6"></span> av<span class="_ _6"></span>ail<span class="_ _6"></span>ab<span class="_ _6"></span>le<span class="_ _6"></span> de<span class="_ _6"></span>vi<span class="_ _6"></span>ce<span class="_ _6"></span> an<span class="_ _6"></span>d p<span class="_ _6"></span>ac<span class="_ _6"></span>ka<span class="_ _6"></span>ge<span class="_ _6"></span> co<span class="_ _6"></span>mb<span class="_ _6"></span>in<span class="_ _6"></span>at<span class="_ _6"></span>i<span class="ls3c">ons <span class="_ _2"></span>for </span></div><div class="t m0 x7 h9 yae ff5 fs2 fc0 sc0 lsab ws0">the signals associated<span class="lsac"> with each GT serial tran<span class="_ _6"></span>sceiver channel <span class="lsad">to sections </span></span></div><div class="t m0 x7 hb yaf ff5 fs5 fc1 sc0 ls7a ws0">21.3.3<span class="_ _e"> </span>G<span class="_ _2"></span>TX Low-P<span class="_ _4"></span>ower Serial T<span class="_ _4"></span>ransceivers<span class="fc0 ls7d"> and </span><span class="ls6d">21.3.4<span class="_ _e"> </span>G<span class="_ _2"></span>TP Low-P<span class="_ _4"></span>ower Serial </span></div><div class="t m0 x7 hb yb0 ff5 fs5 fc1 sc0 lsae ws0">Tr<span class="_ _7"></span>a<span class="_ _7"></span>n<span class="_ _7"></span>s<span class="_ _7"></span>c<span class="_ _7"></span>e<span class="_ _7"></span>i<span class="_ _7"></span>v<span class="_ _7"></span>e<span class="_ _7"></span>r<span class="_ _1"></span>s<span class="_ _7"></span><span class="fc0 ls5">.</span></div><div class="t m0 x6 hb yb1 ff5 fs5 fc0 sc0 ls75 ws0">09/19/2014<span class="_ _b"> </span>1.8<span class="_ _6"></span>.1<span class="_ _15"> </span>Removed erroneous banner from <span class="fc1 ls56">Chapter<span class="_"> </span>21, Progr<span class="_ _4"></span>ammabl<span class="ls58">e Logic Description<span class="fc0 ls52">. </span></span></span></div><div class="t m0 x7 hb yb2 ff5 fs5 fc0 sc0 ls52 ws0">Corrected <span class="ff6 ls4d ws5">send feedback</span><span class="ls40"> button clarity issue in footers.</span></div><div class="t m0 x6 hb yb3 ff5 fs5 fc0 sc0 ls43 ws0">11/17/2014<span class="_ _a"> </span>1.9<span class="_ _b"> </span>Added <span class="_ _4"></span>7z035 <span class="_ _4"></span>dev<span class="_ _6"></span>ice, <span class="_ _0"></span>updated device <span class="_ _4"></span>notices, <span class="_ _4"></span>and <span class="_ _4"></span>ma<span class="ls66">de <span class="_ _4"></span>minor <span class="_ _4"></span>c<span class="_ _6"></span>larifications <span class="_ _4"></span>throughout </span></div><div class="t m0 x7 hb yb4 ff5 fs5 fc0 sc0 ls4e ws0">document (denoted with change bars).</div><div class="t m0 x6 hb yb5 ff5 fs5 fc0 sc0 ls75 ws0">11/19/2014<span class="_ _b"> </span>1.9<span class="_ _6"></span>.1<span class="_ _15"> </span>Corrected document date.</div><div class="t m0 x6 hb yb6 ff5 fs5 fc0 sc0 ls42 ws0">02/23/2015<span class="_ _16"> </span>1.10<span class="_ _17"> </span>Added clarification on the </div><div class="t m0 x13 h9 yb7 ff5 fs2 fc0 sc0 lsaf ws0">timing relationship be<span class="ls3d">tween PL power up and <span class="fs5 ls5f">the PS </span></span></div><div class="t m0 x7 h9 yb8 ff5 fs2 fc0 sc0 lsb0 ws0">POR reset signal to section <span class="fc1 ls46">2.2<span class="_ _c"> </span>P<span class="_ _4"></span>ower Pins<span class="fc0 ls47"> and section </span><span class="lsaf">6.3.3<span class="_ _c"> </span>BootROM </span></span></div><div class="t m0 x7 h9 yb9 ff5 fs2 fc1 sc0 lsb1 ws0">Pe<span class="_ _6"></span>r<span class="_ _6"></span>fo<span class="_ _6"></span>r<span class="_ _6"></span>m<span class="_ _6"></span>a<span class="_ _6"></span>nc<span class="_ _6"></span>e<span class="_ _6"></span><span class="fc0 lsb2">: </span><span class="lsb0">PS_POR_B De-assertion Guidelines<span class="fc0 ls5">.</span></span></div><div class="t m0 x6 hb yba ff5 fs5 fc0 sc0 ls41 ws0">09/27/2016<span class="_ _16"> </span>1.11<span class="_ _17"> </span>Added 7z007s, 7z012<span class="ls62">s, and 7<span class="_ _6"></span>z014s single-core devi<span class="ls9e">ces an<span class="_ _6"></span>d updated the respectiv<span class="_ _6"></span>e </span></span></div><div class="t m0 x7 hb ybb ff5 fs5 fc0 sc0 ls59 ws0">device notices throughout documen<span class="_ _6"></span>t<span class="ls54"> (denoted with change bars). <span class="ls82">Updated <span class="fc1 ls56">Figure<span class="_"> </span>2-1</span><span class="ls52">, </span></span></span></div><div class="t m0 x7 hb ybc ff5 fs5 fc1 sc0 ls4a ws0">T<span class="_ _d"></span>able<span class="_ _13"> </span>21-1<span class="fc0 ls67">, and </span><span class="ls57">Ta<span class="_ _1"></span>b<span class="_ _1"></span>l<span class="_ _1"></span>e<span class="_ _f"> </span>2<span class="_ _1"></span>1<span class="_ _1"></span>-<span class="_ _7"></span>2<span class="_ _1"> </span><span class="fc0 ls63">. Updated device codes in <span class="_ _2"></span><span class="fc1 ls6d">R<span class="_ _2"></span>egister PSS_IDC<span class="_ _4"></span>ODE Details<span class="fc0 ls5">.</span></span></span></span></div><div class="t m0 x6 hb ybd ff5 fs5 fc0 sc0 ls75 ws0">10/20/2017<span class="_ _16"> </span>1.12<span class="_ _17"> </span>Made minor clarifi<span class="ls59">cations throughout<span class="_ _6"></span></span> document (denoted with change bars).</div><div class="t m0 x6 hb ybe ff5 fs5 fc0 sc0 ls41 ws0">12/06/2017<span class="_ _17"> </span>1<span class="_ _6"></span>.12.1<span class="_ _18"> </span>Removed internal review comment from <span class="fc1 ls86">6-bit Programmable Divider</span><span class="ls75"> section.</span></div><div class="t m0 x6 hb ybf ff5 fs5 fc0 sc0 ls66 ws0">07/01/2018<span class="_ _17"> </span>1<span class="_ _6"></span>.12.2<span class="_ _18"> </span>Editorial updates <span class="ls43">only. No technical content up<span class="ls48">dates.</span></span></div><div class="t m0 x5 h5 y9e ff3 fs2 fc0 sc0 ls3f ws0">Date<span class="_ _8"> </span>V<span class="_ _4"></span>ersion<span class="_ _9"> </span>Revision</div><div class="c xb y3f w2 hd"><div class="t m1 xc he y40 ff7 fs6 fc2 sc0 ls5 ws0"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><div class="d m2"></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d m2"></div></a><a class="l" rel='nofollow' onclick='return false;'><div class="d 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