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Xilinx ISE中文简明教程、Xilinx术语中文.pdf、Virtex 系列 FPGA 的配置和回读、FPGA设计检查清单.pdf、设计注意.pdf、逻辑设计注意列表.pdf
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内容介绍
<html xmlns="http://www.w3.org/1999/xhtml"> <head> <meta charset="utf-8"> <meta name="generator" content="pdf2htmlEX"> <meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"> <link rel="stylesheet" href="https://static.pudn.com/base/css/base.min.css"> <link rel="stylesheet" href="https://static.pudn.com/base/css/fancy.min.css"> <link rel="stylesheet" href="https://static.pudn.com/prod/directory_preview_static/633cf391272bb74d442e4cff/raw.css"> <script src="https://static.pudn.com/base/js/compatibility.min.js"></script> <script src="https://static.pudn.com/base/js/pdf2htmlEX.min.js"></script> <script> try{ pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({}); }catch(e){} </script> <title></title> </head> <body> <div id="sidebar" style="display: none"> <div id="outline"> </div> </div> <div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://static.pudn.com/prod/directory_preview_static/633cf391272bb74d442e4cff/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">XAPP138 (v2.8) 2002<span class="_ _0"> </span><span class="ff2 ls1 ws1">&#24180;<span class="_ _0"> </span><span class="ff1 ls2">10<span class="_"> </span></span>&#26376;<span class="_ _0"> </span><span class="ff1 ls2">31<span class="_ _0"> </span></span>&#26085;<span class="_ _1"> </span><span class="ff3 fc1 ls3">www<span class="_ _2"></span>.xilinx.<span class="_ _2"></span>com<span class="_ _3"> </span><span class="ff1 fc0 ls1">1</span></span></span></div><div class="t m0 x2 h3 y2 ff1 fs0 fc0 sc0 ls4 ws1">1-800-255-7778</div><div class="t m0 x1 h4 y3 ff1 fs1 fc0 sc0 ls5 ws2">&#169; 2002 Xilinx, Inc. All right<span class="_ _2"></span>s reserved. All Xilinx trademarks, registered trademarks, p<span class="_ _2"></span>atents, and further disclaimers are as <span class="ls6 ws3">liste<span class="_ _2"></span>d at <span class="ff3 fc1 ls7 ws1">http<span class="_ _4"></span>://www.xilinx.com/le<span class="_ _4"></span>gal.htm</span><span class="ls8 ws4">. All other </span></span></div><div class="t m0 x1 h4 y4 ff1 fs1 fc0 sc0 ls9 ws5">trademarks and registered trademarks are th<span class="_ _2"></span>e property of their re<span class="lsa ws6">spective own<span class="_ _2"></span>ers. All specificat<span class="ls9 ws5">ions are subject to change with<span class="_ _2"></span><span class="lsb ws7">out notice.</span></span></span></div><div class="t m0 x1 h4 y5 ff1 fs1 fc0 sc0 lsc ws8">NOTICE OF DISCLAIMER: Xilinx is providing <span class="lsd ws9">this design, code, or infor<span class="_ _2"></span>mation "as is." <span class="ls9 ws5">By providing the design, code, or informa<span class="_ _2"></span>t<span class="lse wsa">ion as one possible implementation of th<span class="_ _2"></span>is fea-</span></span></span></div><div class="t m0 x1 h4 y6 ff1 fs1 fc0 sc0 lsf wsb">ture, application, or st<span class="_ _2"></span>andard, Xilinx makes no representati<span class="_ _2"></span>on that <span class="ls10 wsc">this implementation is free from any claims of infringe<span class="_ _2"></span>ment<span class="lse wsd">. Y<span class="_ _2"></span>ou are responsi<span class="_ _2"></span>ble for obtaining any right<span class="_ _2"></span>s you may </span></span></div><div class="t m0 x1 h4 y7 ff1 fs1 fc0 sc0 ls8 wse">require for your implement<span class="_ _2"></span>ation. Xilinx expressly disclaims a<span class="_ _2"></span>ny warranty whatsoever with respect to the adequacy of t<span class="_ _2"></span>he impleme<span class="ls9 wsf">ntation, including but not limi<span class="_ _2"></span>ted to any warran-</span></div><div class="t m0 x1 h4 y8 ff1 fs1 fc0 sc0 ls5 ws2">ties or representa<span class="_ _2"></span>tions that this implement<span class="lsa ws10">ation is free from claims of<span class="_ _2"></span> infringement and any implied warranties of merchant<span class="_ _2"></span>abil<span class="ls11 ws11">ity or fitness for a <span class="_ _2"></span>particular purpose.</span></span></div><div class="t m0 x1 h5 y9 ff4 fs2 fc2 sc1 ls1 ws1">&#32508;&#36848;<span class="_ _5"> </span><span class="fs3 fc0 sc0">&#26412;&#24212;&#29992;&#31508;&#35760;&#21487;&#20197;<span class="_ _4"></span>&#20316;&#20026;<span class="_ _6"> </span>Virtex<span class="ff5 ls12">&#8482; </span><span class="ls13">&#30340;&#25968;&#25454;&#25163;&#20876;&#20013;&#30340;&#37197;&#32622;&#21333;&#20803;&#30340;<span class="_ _2"></span>&#34917;&#20805;&#25991;&#26412;&#12290;&#24378;&#28872;&#24314;&#35758;&#22312;&#38405;&#35835;&#26412;&#24212;&#29992;</span></span></div><div class="t m0 x3 h6 ya ff4 fs3 fc0 sc0 ls14 ws1">&#31508;&#35760;&#21069;&#27983;&#35272;&#19968;&#19979;<span class="_ _6"> </span>Virtex<span class="_ _0"> </span>&#30340;&#25968;&#25454;&#25163;&#20876;&#12290;<span class="_ _7"></span>Virtex<span class="_ _6"> </span>&#31995;&#21015; <span class="_ _2"></span><span class="ls15">FPGA<span class="_ _6"> </span>&#25552;&#20379;&#20102;&#27604;&#21069;&#20960;&#20195;<span class="_ _6"> </span>Xilinx<span class="_ _0"> </span>&#30340;<span class="_ _6"> </span>FPGA<span class="_ _6"> </span>&#26356;&#23485;&#33539;</span></div><div class="t m0 x3 h6 yb ff4 fs3 fc0 sc0 ls13 ws1">&#22260;&#30340;&#37197;&#32622;&#21644;&#22238;&#35835;&#33021;&#21147;&#12290;&#26412;&#31508;&#35760;&#39318;<span class="_ _2"></span>&#20808;&#32473;&#20986;&#20102;<span class="_ _6"> </span>Virte<span class="_ _2"></span>x<span class="_ _6"> </span>&#30340;&#37197;&#32622;&#19982;&#20197;&#21069;&#30340; Xil<span class="_ _2"></span>inx<span class="_ _6"> </span>&#30340;<span class="_ _0"> </span>FPGA<span class="_ _6"> </span>&#22914;&#20309;&#19981;&#21516;&#30340;</div><div class="t m0 x3 h6 yc ff4 fs3 fc0 sc0 ls13 ws1">&#27604;&#36739;&#65292;&#28982;&#21518;&#32473;&#20986;&#20102;&#37197;&#32622;&#36807;&#31243;&#21644;&#27969;<span class="_ _2"></span>&#31243;&#30340;&#23436;&#25972;&#25551;&#36848;&#12290;&#27599;&#20010;&#37197;&#32622;&#27169;&#24335;&#22343;&#26377;&#27010;&#36848;&#21644;&#35814;&#32454;&#30340;<span class="_ _2"></span>&#35752;&#35770;&#65292;&#26368;&#21518;&#26159;</div><div class="t m0 x3 h6 yd ff4 fs3 fc0 sc0 ls13 ws1">&#25968;&#25454;&#27969;&#26684;&#24335;&#12289;&#22238;&#35835;&#21151;&#33021;&#21644;&#25805;&#20316;&#30340;<span class="_ _2"></span>&#23436;&#25972;&#25551;&#36848;&#12290;</div><div class="t m0 x1 h5 ye ff4 fs2 fc2 sc1 ls1 ws1">&#31616;&#20171;<span class="_ _5"> </span><span class="fs3 fc0 sc0 ls16">&#37197;&#32622;&#26159;&#23558;&#35774;&#35745;&#30340;&#20301;&#27969;&#36733;&#20837;&#21040;<span class="_ _6"> </span>FPGA<span class="_ _0"> </span>&#30340;&#20869;&#37096;&#37197;&#32622;&#23384;<span class="ls17">&#20648;&#22120;&#20869;&#30340;&#19968;&#20010;&#36807;&#31243;&#12290;&#22238;&#35835;&#23601;&#26159;<span class="ls18">&#35835;&#20986;&#36825;&#20123;&#25968;&#25454;&#30340;</span></span></span></div><div class="t m0 x3 h6 yf ff4 fs3 fc0 sc0 ls13 ws1">&#36807;&#31243;&#12290;</div><div class="t m0 x3 h6 y10 ff4 fs3 fc0 sc0 ls1 ws1">Virtex &#30340;&#37197;&#32622;&#36923;<span class="_ _4"></span>&#36753;&#19982;<span class="_ _6"> </span>XC4000<span class="_ _6"> </span>&#31995;&#21015;&#26377;&#30528;&#24456;&#22823;&#30340;<span class="_ _4"></span>&#19981;&#21516;&#65292;&#20294;&#20173;&#28982;&#20445;&#25345;<span class="_ _4"></span>&#20102;&#19982;<span class="_ _6"> </span>Xilinx<span class="_ _6"> </span>&#30340;&#25152;&#26377; FPGA<span class="_ _6"> </span>&#31995;&#21015;</div><div class="t m0 x3 h6 y11 ff4 fs3 fc0 sc0 ls1 ws1">&#30340;&#30456;&#24403;&#22810;&#30340;&#20860;&#23481;<span class="_ _4"></span>&#24615;&#12290;&#36825;&#20010;&#20449;&#24687;<span class="_ _4"></span>&#26159;&#32771;&#34385;&#21040;<span class="_ _6"> </span>XC4000<span class="_ _6"> </span>&#31995;&#21015;&#29992;&#25143;&#32780;&#20934;&#22791;<span class="_ _4"></span>&#30340;&#65292;&#20294;&#26159;<span class="_ _6"> </span>Xilinx<span class="_ _6"> </span>&#30340;<span class="_ _6"> </span>FPGA<span class="_ _6"> </span>&#30340;&#26032;</div><div class="t m0 x3 h6 y12 ff4 fs3 fc0 sc0 ls1 ws1">&#29992;&#25143;&#19981;&#24517;&#21435;&#30475;&#19982;<span class="_ _6"> </span>XC400<span class="_ _4"></span>0<span class="_ _6"> </span>&#31995;&#21015;&#37197;&#32622;&#30456;&#20851;&#30340;&#36164;&#26009;<span class="_ _4"></span>&#12290;</div><div class="t m0 x1 h5 y13 ff4 fs2 fc2 sc1 ls19 ws1">Virtex<span class="_ _8"> </span>&#31995;&#21015;&#19982; </div><div class="t m0 x1 h5 y14 ff4 fs2 fc2 sc1 ls19 ws1">XC4000<span class="_ _8"> </span>&#31995;&#21015;&#37197;&#32622;</div><div class="t m0 x1 h5 y15 ff4 fs2 fc2 sc1 ls1 ws1">&#30340;&#27604;&#36739;</div><div class="t m0 x3 h6 y13 ff4 fs3 fc0 sc0 ls1 ws1">&#26412;&#21333;&#20803;&#35752;&#35770;&#30340;&#26159;<span class="_ _6"> </span>Virte<span class="_ _4"></span>x<span class="_ _6"> </span>&#31995;&#21015;&#21644;<span class="_ _6"> </span>Xilinx<span class="_ _6"> </span>&#30340;&#20197;&#21069;&#30340;<span class="_ _6"> </span>FPGA<span class="_ _0"> </span>&#31995;<span class="_ _4"></span>&#21015;&#22312;&#37197;&#32622;&#26041;&#38754;<span class="_ _4"></span>&#30340;&#20027;&#35201;&#30340;&#24046;&#21035;<span class="_ _4"></span>&#12290;</div><div class="t m0 x3 h7 y16 ff4 fs4 fc2 sc1 ls1 ws1">&#37197;&#32622;&#27169;&#24335;&#21644;&#33738;&#33457;&#38142;</div><div class="t m0 x3 h6 y17 ff4 fs3 fc0 sc0 ls1 ws1">&#22914;<span class="_ _6"> </span><span class="fc3">Table<span class="_"> </span>1<span class="_ _6"> </span></span>&#25152;&#31034;&#65292;Virtex<span class="_ _6"> </span>&#31995;&#21015;&#30340;<span class="_ _6"> </span>FPGA<span class="_ _6"> </span>&#21487;&#20197;&#29992;&#20843;&#31181;&#19981;&#21516;<span class="_ _4"></span>&#30340;&#27169;&#24335;&#36827;&#34892;&#37197;&#32622;&#12290;<span class="_ _9"></span> &#26377;&#22235;&#31181;&#22522;&#26412;&#30340;<span class="_ _4"></span>&#27169;&#24335;</div><div class="t m0 x4 h6 y18 ff4 fs3 fc0 sc0 ls1 ws1">&#65288;&#20027;&#20018;<span class="_ _6"> </span>&#65288;Master Seri<span class="_ _4"></span>al&#65289;<span class="_ _9"></span>&#12289;&#20174;&#20018;<span class="_ _0"> </span>&#65288;<span class="_ _4"></span> Slave Serial&#65289;<span class="_ _9"></span>&#12289;SelectMAP&#65292;<span class="_ _9"></span> &#21644;&#36793;&#30028;&#25195;&#25551;<span class="_ _6"> </span>&#65288;Boundary </div><div class="t m0 x3 h6 y19 ff4 fs3 fc0 sc0 ls13 ws1">Scan&#65289;<span class="_ _a"></span>&#65289;<span class="_ _a"></span>&#65292;&#27599;&#19968;&#31181;&#27169;&#24335;&#22343;&#26377;&#36873;&#25321;&#20351;<span class="_ _0"> </span>I/O<span class="_ _6"> </span>&#22312;&#37197;&#32622;&#26399;&#38388;&#22788;&#20110;&#30830;&#23450;&#29366;&#24577;&#25110;&#28014;<span class="_ _2"></span>&#31354;&#29366;&#24577;&#12290;<span class="_ _9"></span> </div><div class="t m0 x3 h6 y1a ff4 fs3 fc0 sc0 ls13 ws1">&#22914;&#26524;&#37197;&#32622;&#26102;&#19978;&#25289;<span class="_ _0"> </span>&#65288;pull-up&#65289;&#34987;&#36873;&#20013;&#65292;<span class="_ _2"></span>&#23427;&#20204;&#21482;&#22312;&#37197;&#32622;&#26399;&#38388;&#26377;&#25928;&#12290;&#37197;&#32622;&#23436;&#25104;&#21518;&#65292;&#19981;&#29992;&#30340;<span class="_ _0"> </span>I/O<span class="_ _0"> </span>&#23558;&#20250;</div><div class="t m0 x3 h6 y1b ff4 fs3 fc0 sc0 ls13 ws1">&#34987;&#28014;&#31354;&#12290;<span class="_ _a"></span> </div><div class="t m0 x3 h6 y1c ff4 fs3 fc0 sc2 ls13 ws1">&#20018;&#34892;&#27169;&#24335;</div><div class="t m0 x3 h6 y1d ff4 fs3 fc0 sc0 ls13 ws1">&#20027;&#20018;&#21644;&#20174;&#20018;&#27169;&#24335;&#19982;&#20197;&#21069;&#30340;<span class="_ _0"> </span>FPGA<span class="_ _0"> </span>&#31995;&#21015;&#34920;&#29616;&#22522;&#26412;&#30456;&#21516;&#12290;&#26356;&#35814;&#32454;&#30340;&#25551;&#36848;&#21487;&#20197;&#21442;&#35265;<span class="_ _0"> </span><span class="fc3">"<span class="_ _6"> </span>&#20027;<span class="_ _0"> </span>/<span class="_ _6"> </span>&#20174;&#20018;&#34892;&#27169;&#24335;</span></div><div class="t m0 x3 h6 y1e ff4 fs3 fc3 sc0 ls1 ws1">"on page 9 <span class="fc0">.</span></div><div class="t m0 x5 h8 y1f ff3 fs3 fc2 sc0 ls16 ws12">Application Note:<span class="_ _2"></span> Virtex<span class="_ _0"> </span><span class="ff2 sc1 ls13 ws1">&#31995;&#21015;</span></div><div class="t m0 x1 h8 y20 ff1 fs3 fc0 sc0 ls1a ws13">XAPP138 (v2.8) 2002<span class="_"> </span><span class="ff2 ls1 ws1">&#24180;<span class="_ _0"> </span><span class="ff1 ls1b">10<span class="_"> </span></span>&#26376;<span class="_ _0"> </span><span class="ff1 ls1b">31<span class="_"> </span></span>&#26085;</span></div><div class="t m0 x6 h9 y21 ff3 fs5 fc2 sc0 ls1c ws1">Vi<span class="_ _4"></span>r<span class="_ _4"></span>t<span class="_ _b"></span>e<span class="_ _4"></span>x<span class="_ _c"> </span><span class="ff2 sc1 ls1">&#31995;&#21015;</span><span class="ls1d ws14"> FPGA<span class="_ _d"> </span></span><span class="ff2 sc1 ls1">&#30340;&#37197;&#32622;&#21644;&#22238;&#35835;</span></div><div class="t m0 x7 ha y22 ff6 fs6 fc0 sc0 ls1 ws1">R</div><div class="t m0 x3 h6 y23 ff7 fs3 fc0 sc0 ls1e ws15">T<span class="_ _7"></span>able 1: <span class="ff4 sc2 ls13 ws1">Virtex<span class="_ _6"> </span>&#30340;&#37197;&#32622;&#27169;&#24335;</span></div><div class="t m0 x8 h8 y24 ff2 fs3 fc0 sc2 ls13 ws1">&#37197;&#32622;&#27169;&#24335;<span class="_ _e"> </span><span class="ff3 sc0 ls1f">M2<span class="_ _f"> </span>M1<span class="_ _10"> </span>M0<span class="_ _11"> </span></span>&#19978;&#25289;</div><div class="t m0 x9 h8 y25 ff2 fs3 fc0 sc0 ls13 ws1">&#20027;&#20018;<span class="_ _12"> </span><span class="ff1 ls20">00<span class="_ _13"> </span>0<span class="_ _14"> </span></span><span class="ls1">&#21542;</span></div><div class="t m0 x9 h8 y26 ff2 fs3 fc0 sc0 ls13 ws1">&#20174;&#20018;<span class="ff1 ls20 ws16"> 11<span class="_ _13"> </span>1<span class="_ _14"> </span></span><span class="ls1">&#21542;</span></div><div class="t m0 x9 h8 y27 ff1 fs3 fc0 sc0 ls21 ws17">SelectMAP 1<span class="_ _15"> </span>1<span class="_ _16"> </span>0<span class="_ _17"> </span><span class="ff2 ls1 ws1">&#21542;</span></div><div class="t m0 x9 h8 y28 ff2 fs3 fc0 sc0 ls13 ws1">&#36793;&#30028;&#25195;&#25551;<span class="ff1 ls20 ws18"> 10<span class="_ _13"> </span>1<span class="_ _14"> </span></span><span class="ls1">&#21542;</span></div><div class="t m0 x9 h8 y29 ff2 fs3 fc0 sc0 ls13 ws1">&#20027;&#20018;<span class="ff1 ls22"> (<span class="_ _6"> </span></span>&#21152;&#19978;&#19978;&#25289;<span class="_ _0"> </span><span class="ff1 ls23">)1<span class="_ _18"></span>0<span class="_ _19"></span>0<span class="_ _1a"></span><span class="ff2 ls1">&#26159;</span></span></div><div class="t m0 x9 h8 y2a ff2 fs3 fc0 sc0 ls13 ws1">&#20174;&#20018;<span class="ff1 ls22"> (<span class="_ _6"> </span></span>&#21152;&#19978;&#19978;&#25289;<span class="_ _0"> </span><span class="ff1 ls23">)0<span class="_ _18"></span>1<span class="_ _19"></span>1<span class="_ _1a"></span><span class="ff2 ls1">&#26159;</span></span></div><div class="t m0 x9 h8 y2b ff1 fs3 fc0 sc0 ls21 ws19">SelectMAP (<span class="_"> </span><span class="ff2 ls13 ws1">&#21152;<span class="_ _2"></span>&#19978;&#19978;&#25289;<span class="_ _6"> </span><span class="ff1 ls24">)0<span class="_ _1b"></span>1<span class="_ _1c"></span>0<span class="_ _1d"></span><span class="ff2 ls1">&#26159;</span></span></span></div><div class="t m0 x9 h8 y2c ff2 fs3 fc0 sc0 ls13 ws1">&#36793;&#30028;&#25195;&#25551;<span class="ff1 ls22"> (<span class="_ _0"> </span></span>&#21152;&#19978;&#19978;&#25289;<span class="_ _6"> </span><span class="ff1 ls25">)0<span class="_ _1e"></span>0<span class="_ _1f"></span>1<span class="_ _20"></span><span class="ff2 ls1">&#26159;</span></span></div><a class="l" rel='nofollow' onclick='return false;'><div class="d m1"></div></a><a class="l" rel='nofollow' onclick='return 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评论
  • PUDN用户 2011-10-28 21:59:55
    内容很丰富,就是版本比较老
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